electrical characteristics NEGATIVE LOGIC (Note 5)

T A within operating temperature range, Vss = +5.0V ±5%, V GG = Voo = -12V ±5%, unless otherwise noted.

PARAMETER CONDITIONS MIN TYP MAX UNITS

Output Voltage Levels

Logical "1" IL = 1.6 mA sink .4 V

Logical "0" IL = l00pA source 2.4 V

Input Voltage Levels

Logical "1" Vss - 4.0 V

Logical "0" Vss - 2.0 V

Power Supply Current

Iss (Note 4) Vss = 5, VGG = -12, VLL = -12, TA = 25°C 23 37 mA

Iss (Note 4) Vss = 5, VGG = -12. VLL = -3.TA =125°C 20 mA

Input Leakage VIN = Vss - lOV 1 jlA

Input Capacitance (Note 1) f= 1.0 MHz, V

,N

= OV 5 15 pF

Output Capacitance (Note 1) f= 1.0 MHz. V

,N

=OV 4 10 pF

Address Time (Note 2) TA = 25°C, Vss = 5 150 700 900 ns

T ACCESS VGG

=

V Ll = -12V

Output AND Connections (Note 3) 20

Note 1: Address time is measured from the change of data olJ any input or Chip Enable line to the output of a TTL gate.

(See Timing Diagram.) See curves for guaranteed limit over temperature.

Note 2: Capacitances are measured periodically only,

Note 3:. The address time follows the following equation: T ACCESS

=

the specified limit + (N - 1) x 25 ns where N

=

Number of AND connections.

Note 4: Outputs open.

Note 5: All addresses and outputs are in negative true logic with the exception of LO. Ll. and L2 which are in positive logic.

performance characteristics

1400 1200 1000

J800 .

.... BOO 400 200

Typical Access Time vs Supply Voltage

VLL '" VGG

tZ5°C IT.=71I"C 25°C

1&.2 11.0 11.8 Vss + IVGG I IV)

Powe, Supply Current

VI Temperature

811 H

~1=l+l+fi;-;:ri~"1

Vss=5.OV

10~~~~~tv~G;G:=~VL~L~=~-I~ZV~

~++tt~++tt~

-5°B

1

⁴⁰ ^MAXIMUM

~ 30

TYPICAL ZO

-50 -25 0 25 50 15 100 125 TEMPERATURE 1°C)

timing diagram/address time

Eo"

EOUT

1400

Guaranteed Access Time vs Supply Voltage

1200 IZ5°C

~.= 10°C _ 1000 Z5°C

.! or; 800 ....

&00 400 200

16.2 11.0 11.8 Vss+IVGol (V)

Powe, Supply Current

V5 Voltage

&0 C 50 .540

~ 30 20 10

IB.2

TIME

MAXIMUM TYPICAL

11.0 I1.B Vss + IVoG I (V)

3-61

RAMs

MM1101lMM110111MM1101A/MM1101AlIMM1101A2, MM4250 256-bit fully decoded static random access memory

general description

The MMll0l family of fully decoded 256 word x l-bit random access memories are monolithic MOS integrated circuits using silicon gate low threshold technology to achieve bipolar compatibility. They are static, require no clocks, and hold information indefinitely, subject to the integrity of the power supply voltages.

features

• Fast access times MMll01A2 500 ns max 1.0 j.ls max 1.5 j.lS max 650 ns max MM 11011, MM 11 01 A 1

MMl101, MMll01A MM4250

• Improved speed/power product MM1101A2 1/3 of 1101A 1.5 mW/bit

• Low power operation

block and connection diagrams

A, A, A, A,

DATA OUT

RIW DATA IN

,

16 15 12

X INPUT BUffERS

OUTPUT BUffER

Vee'" PIN 5 Vo"'PIN4 Voo '" PIN 8

Z56 BIT RAM PLANE

• Fewer system components - bipolar compatible input and output

• Secondsourceflexibility-MMll0l, MMll01A MM11011, MM1101A 1 second sources avail-able

• TRI-STATETM output - wired OR capability

• Specified ambient temperature O°C to + 70°C, for MMll01 family; _55°C to +125°C for MM4250

applications

• High speed buffer memories

• Local memory store

Dual-In-Line Package

INPUT As 1 16 CHIP SElECT

INPUTA7 2 15

READIWRITE INPUT A& ³ 14 DATA OUT

Vo 13 DATA OUT

V~ 12

DATA IN

INPUT A4 11

INPUT A3

INPUT Ao 10

INPUT A,

Voo

,

INPUT A2

TOP VIEW Order Number MM1101 D, MM1101AD. MM1101A1D, MM1101A2D, MM11011D

or MM4250D See Package 3 Order Number MM1101N.

MM1101AN. MM1101A1N.

MM1101A2N or MM11011N See Package 15

4-1

absolute maximum ratings

All Input or Output Voltages with Respect to the Most Positive Supply

Voltage, V ss +0.3V to -20V

Supply Voltages Voo and Vo with -16V

Respect to Vss

Power Dissipation at Room Temperature Operating Temperature

MMll0l Family MM4250 Storage Temperature

Lead Temperature (Soldering, 10 sec)

dc characteristics

SYMBOL TEST CONDITIONS

MIN TVP MAX

I " Input Load Current VIN = 0.0 0.001

(All Input Pins)

"0 Output Leakage Current VOUT = O.OV, CS = Vss - 2.0V 0.001

r

Power Supply Current, Voo

"-~' )

Read Cycle MMll0l, MMll01A 1.5

MMll0ll, MMll01Al 1.0

MMll01A2 500.0

MM4250 650.0

,~ Address to Chip Select Delay MM1101, MMll01A, MM11011, MMll01Al MMll01A MM4250

'.

Access Time MMll0l, MMll01A

MMll0ll, MMll01Al

Note 3: Capacitances are measured periodically only.

TYP

ac characteristics (con't)

WRITE CYCLE IMM1101, MMll0l1, MM1101A, MM1101Al, MMll01A2)

SYMBOL TEST MIN TYP

MAX UNITS

INote 2)

twe Write Cycle O.B iJ.S

two Address to Write Pulse Delay 0.3 iJ.S

twp Write Pulse Width 0.4 iJ.s

tow Data Set up Time 0.3 iJ.S

'OH Data Hold Time 0.1 iJ.S

WRITE CYCLE IMM4250)

'wo Write Cycle 1.0 iJ.s

'wd Address to Write Pulse Delay 0.35 iJ.S

twp Write Pulse Width 0.50 iJ.S

'dw Data Set-up Time 0.35 iJ.S

'dh Data Hold Time 0.15 iJ.s

CHIP SELECT AND DESELECT IMM1101, MMll011, MM1101A, MMll01Al, MM1101A2, MM4250)

'ew Chip Select Pulse Width 0.4 iJ.S

'cs

Access Time Through Chip 0.2 0.3 iJ.S

Select Input

teo Chip Deselect Time 0.1 0.3 iJ.S

Note 1: All voltage measurements are referenced to ground.

Note 2: Typical values are at T A ::= +25°C and nominal supply voltages.

Note 3: Capacitances are measured periodically only.

Note 4: Maximum value for tac measured at minimum read cycle.

typical performance characteristics

MM1101A, MM1101A1,

Typical Access Time vs Typical Access Time vs MM1101A2, MM4250

Voltage Temperature Operating Region

MM1101A

VDO-Jovr

¹⁴⁰⁰ TA -25"C

1000 Vcc - 5.0V

t7yoo',-9V,C

^{1200 C}^l^{=20 pF} ¹⁸

!

⁸⁰⁰ ^Vuo--IV

'"

1 TTL LOAD MM1101A,-:- I

-Q ..

;Df>--UIV ..s 1000 _MM1101Ai 11

!i!

100 ^MM1101Aj~ ^~

!i!

~

¹⁶

;: rs!-~" ;: 800 C> TYPICAL OPERATING

~

⁶⁰⁰ ^~:~~~~

^~ ^~

.voo--g~_=t±

~

⁶⁰⁰

- _...

^{- t -} ^~ ^~^>^o ¹⁵¹⁴^{- l -}^{- I -}

^I

,,"GUARANTEE ^REGION.l

^17V1

..

⁴⁰⁰ • Voo-1 .... v ~

,

_ OPi~ATINGt: :.l

r+~;ov

_{VDD --9V} ^"- ⁴⁰⁰ ^~ ^~¹³12

-t

^REGION

l' ₂₀₀1-- MMll01A2,MM4250 - l -

I

200 ~VDD~-'V

" .

¹¹

^I ^I

-1 -6 -9 -10 -11 -30 -10 10 30 50 10 8 10 12 14 16

Vo (V) TEMPERATURE 1°C) Vss- VOD (VI

ac test circuit

Test Setup for MM1101A and MM1101A Speed Measurement 'SV

ADDRESS

Iv~ ^{IVD IVDD}

^oATA

^{.. v}

+3:n

ÎNPUT ^MM1101A^MMll01/ ÔUTPUT ¹ÔUTPUT

,~

^ANY

CONDITIONS OF TEST

-=

^{tTL GAT.}

Input pulse amplitudes: OV to +5.0V.

Input pulse (lse and fall times:::; 10 liS.

Speed measuremelltsare referenced to the 1.SV level (unless otherwise noted);

at the OUt(:lllt of the TTL gate (t"" s; 10 ns) Cl So 20 pF.

4·3

... 0

"'\,0 c(N

oo:t

;::E :E:E :E .

... N

C(C(

...

0 0

...

:E:E :E:E

... ... ... _o ... ...

:E :E

...

... o

... ...

:E :E

switching time waveforms

Read Cvcle Chip Select and Deselect

I---,,,---~.j

AEAO/WRITE

ADDRESSES

'-v-i(

.~~l

(r:r- ____________

____

________ '_':r-L

AODRESSES

'.---IJT-r-OUTPUTS

OUTPUTS

. ---'

Write Cvcle Power Switching For Reduced Power Applications

ADDRESSES

ADDR,SSES :

--r ____________________ _

---./~2:'Dns

v" ---7.:~

Vo AND CS LEAD V.

REAOIWRITE ',<,:; lOOns

OUTPUTS

DATA IN

Voo :-9Vt5"

Note 1: All inputs of the MM1101 A accept standard TTL outputs with Vce = +5.0V ±5%.

Note 2: Maximum value for tAC measured at minimum read cycle.

RAMs

MM2102 1024-t;)it fully decodetJ static random access memory

Dans le document Edge Index by Product Family (Page 141-148)

electrical characteristics NEGATIVE LOGIC (Note 5)

,N

,N

=

=

=

performance characteristics

J800 .

~1=l+l+fi;-;:ri~"1

~++tt~++tt~

-5°B

1

timing diagram/address time

RAMs

MM1101lMM110111MM1101A/MM1101AlIMM1101A2, MM4250 256-bit fully decoded static random access memory

general description

features

block and connection diagrams

,

applications

,

absolute maximum ratings

dc characteristics

r

"-~' )

'.

ac characteristics (con't)

'cs

typical performance characteristics

VDO-Jovr

t7yoo',-9V,C

!

'"

-Q ..

!i!

!i!

~

~

~ ~

~

- ...

I

17V1

..

,

r+~;ov

-t

I

" .

I I

ac test circuit

Iv~ IVD IVDD

.. v

+3:n

,~

-=

... 0

oo:t

;::E :E:E :E .

C(C(

...

0 0

...

...

:E:E :E:E

... ... ... o ... ...

:E :E

...

... o

... ...

:E :E

switching time waveforms

'-v-i(

(r:r- ____________

______ __

________ '_':r-L

. ---'

--r ____________________ _

---./~2:'Dns

RAMs

^~ ^~

- _...

^I

^17V1

^I ^I

Iv~ ^{IVD IVDD}

^{.. v}

... ... ... _o ... ...

____