CURRENTS - Positive current is defined as conventional current flow into a device. Negative current is defined as con-ventional current flow out of a device.
liN - (Input Current) - The current flowing into a device at specified input voltage and VDD.
IOH - (Output HIGH Current) - The drive current flowing out of the device at specified HIGH output voltage and VDD.
IOL - (Output LOW Current) - The drive current flowing into the device at specified LOW output voltage and VDD.
IDD - (Quiescent Power Supply Current) - The current flowing into the VDD lead at specified input and VDD conditions.
IOZH - (Output OFF Current HIGH) - The leakage current flowing into the output of a 3-state device in the "OFF" state at a specified HIGH output voltage and VDD.
IOZL - (Output OFF Current LOW) - The leakage current flowing out of a 3-state device in the "OFF" state at a specified HIGH output voltage and VDD.
IlL - (Input Current LOW) - The current flowing into a device at a specified LOW level input voltage and a specified VDD.
IIH - (Input Current HIGH) - The current flowing into a device at a specified HIGH level input voltage and a specified VDD·
IDDL - (Quiescent Power Supply Current LOW) - The current flowing into the VDD lead with a specified LOW level input voltage on all inputs and specified VDD conditions.
IDDH - (Quiescent Power Supply Current HIGH) - The current flowing into the VDD lead with a specified HIGH level in-put voltage on a/l inin-puts and specified VDD conditions.
IZ - (OFF State Leakage Current) - The leakage current flowing into the output of a 3-state device in the "OFF" state at a specified output voltage and VDD.
VOLTAGES - All voltages are referenced to V SS (or VEE) which is the most negative potential applied to the device.
VDD - (Drain Voltage) - The most positive potential on the device.
VIH - (Input HIGH Voltage) - The range of input voltages that represents a logic HIGH level in the system.
VIL - (Input LOW Voltage) - The range of input voltages that represents a logic LOW level in the system.
VIH (min) - (Minimum Input HIGH Voltage) - The minimum allowed input HIGH 1evel in a logic system.
VIL (max) - (Maximum Input LOW Voltage) - The maximum allowed input LOW level in a system.
VOH - (Output HIGH Voltage) - The range of voltages at an output terminal with specified output loading and supply voltage. Device inputs are conditioned to establish a HIGH level at the output.
VOL - (Output LOW Voltage) - The range of voltages at an output terminal with specified output loading and supply volt-age. Device inputs are conditioned to establish a LOW level at the output.
VSS - (Source Voltage) - For a device with a single negative power supply, the most negative power supply, used as the reference level for other voltages. Typically ground.
VEE - (Source Voltage) - One of two (VSS and VEE) negative power supplies. For a device with dual negative power sup-plies, the most negative power supply used as a reference level for other voltages.
ANALOG TERMS
RON - (ON Resistance) - The effective "ON" state resistance of an analog transmission gate, at specified input voltage, output load and VDD.
f':,. RON -
("fl"
ON Resistance) - The difference in effective "ON" resistance between any two transmission gates of an analog device at specified input voltage, output load and VDD.DEFINITION OF SYMBOLS AND TERMS USED IN DATA SHEETS AC SWITCHING PARAMETERS
fMAX - (Toggle Frequency/Operating Frequency) - The maximum rate at which clock pulses may be applied to a sequen-tial circuit with the output of the circuit changing between 30% of VDD and 70% of VDD' Above this frequency the device may cease to function. See Figure 3-15.
tpLH - (Propagation Delay Time) - The time between the specified reference points. normally 50% points on the input and output voltage waveforms. with the output changing from the defined LOW level to the defined HIGH level. See Fig-ure 3-14.
tpHL - (Propagation Delay Time) - The time between the specified reference points. normally 50% points on the input and output voltage waveforms. with the output changing from the defined HIGH level to the defined LOW level. See Fig-ure 3-14.
tTLH - (Transition Time. LOW to HIGH) - The time between two specified reference points on a waveform. normally 10%
to 90% of VDD. which is changing from LOW to HIGH. See Figure 3-14.
tTHL - (Transition Time. HIGH to LOW) - The time between two specified reference points on a waveform. normally 90%
to 10% of VDD. which is changing from HIGH to LOW. See Figure 3-14.
tw - (Pulse Width) - The time between 50% amplitude points on the leading and trailing edges of pulse.
th - (Hold Time) - The interval immediately following the active transition of the timing pulse (usually the clock pulse) or following the transition of the control input to its latching level. during which interval the data to be recognized must be maintained at the input to ensure its continued recognition. A negative hold time indicates that the correct logic level may be released prior to the active transition of the timing pulse and still be recognized.
ts - (Set-up Time) - The interval immediately preceding the active transition of the timing pulse (usually the clock pulse) or preceding the transition of the control input to its latching level. during which interval the data to be recognized must be maintained at the input to ensure its recognition. A negative set-up time indicates that the correct logic level may be initi-ated sometime after the active transition of the timing pulse and still be recognized.
tpHZ - (3-State Output Disable Time. HIGH to Z) - The time between the specified reference points. normally the 50%
point on the Output Enable input voltage waveform and a point representing a 0.1 VDD drop on the Output voltage wave-form of a 3-state device. with the output changing from the defined HIGH level to a high impedance OFF state.
tpLZ - (3-State Output Disable Time. LOW to Z) - The time between the specified reference points. normally the 50%
point on the Output Enable input voltage waveform and a point representing a 0.1 VDD rise on the Output voltage wave-form of a 3-state device. with, the output changing from the defined LOW level to a high impedance OFF state.
tpZH - (3-State Output Enable Time. Z to HIGH) - The time between the specified reference points. normally the 50%
point on the Output Enable input voltage waveform and a point representing 0.5 VDD on the Output voltage waveform of a 3-state device. with the output changing from a high impedance OFF state to the defined HIGH level.
tpZL - (3-State Output Enable Time. Z to LOW) - The time between the specified reference points. normally the 50%
point on the Output Enable input voltage waveform and a point representing 0.5 VDD on the Output voltage waveform of a 3-state device. with the output changing from a high impedance OFF state to the defined LOW level.
trec - (Recovery Time) - The time between the end of an overriding asynchronous input. typically a Clear or Reset input.
and the earliest allowable beginning of a synchronous control input. typically a Clock input. normally measured at 50%
points on both input voltage waveforms.
tcw-
(Clock Period) - The time between 50% amplitude points on the leading edges of a clock pulse.1- -I
- ' T H l~
INPUT
I ,---90%
- - - f - - - s O %
_____ 11--- \ ---10% Vss
INVERTING OUTPUT
--i
90%11---:: Vss
Fig. 3-14. Propagation Delay, Transition Time
CP
'"
4-43
I~
l/fMAX-I
t
o% \ f%
I~
l/fMAX~I
I
\0% 50\
Fig, 3-15. Maximum Operating Frequency
•
FAIRCHILD CMOS. F4001/34001 • F4002/34002
F4001 QUAD 2-INPUT NOR GATE. F4002 DUAL 4-INPUT NOR GATE
DESCRIPTION - These CMOS logic elements provide the positive input NOR function. The outputs are fully buffered for highest noise immunity and pattern insensitivity of output impedance.
F4001
LOGIC AND CONNECTION DIAGRAM DIP (TOP VIEW)
NOTE:
The Flatpak'versions have the same pinouts (Connection Diagram) as the Dual In-line Package.
DC CHARACTERISTICS: VDD as shown, VSS ~ 0 V LIMITS
SYMBOL PARAMETER VDD - 5 V VDD~10V VDD -15V
MIN TYP MAX MIN TYP MAX MIN TYP MAX
Quiescent 0.5 5.0 1.0
Power XC 15.0 30.0 6.0
IDD Supply 0.05 0.1 0.02
Current XM 3.0 6.0 1.2
AC CHARACTERISTICS: VDD as shown, VSS = 0 V, T A = 25°C, F4001 only (See Note 2) LIMITS
SYMBOL PARAMETER VDD ~ 5 V VDD~10V VDD =15V
F4002
LOGIC AND CONNECTION DIAGRAM DIP (TOP VI EW)
UNITS TEMP TEST CONDITIONS See Note 1 MIN,25°C All inputs common pA MAX and at 0 V or VDD
MIN,25°C
~A MAX
UNITS TEST CONDITIONS MIN TYP MAX MIN TYP MAX MIN TYP MAX See Note 2
tpLH Propagation Delay 40 75 20 40 15 ns
tpHL 40 75 20 40 15 ns CL ~ 15 pF
tTLH Output Transition 25 75 10 40 8 25 ns Input Transition Times.;; 20 ns
tTHL Time 25 75 10 40 8 25 ns
tpLH Propagation Delay 60 110 25 60 20 ns
tpHL 60 110 25 60 20 ns CL ~ 50 pF
tTLH Output Transition 60 135 30 70 20 45 ns Input Transition Times.;; 20 ns
tTHL Time 60 135 30 70 20 45 ns
AC CHARACTERISTICS: VDD as shown, VSS = 0 V, T A = 25°C, F4002 only LIMITS
SYMBOL PARAMETER VDD ~ 5 V VDD ~ 10 V VDD=15V UNITS TEST CONDITIONS
MIN TYP MAX MIN TYP MAX MIN TYP MAX See Note 2
tpLH Propagation Delay 50 75 20 40 15 ns
tpHL 50 75 23 40 17 ns CL = 15 pF
tTLH Output Transition 30 75 15 40 11 25 ns Input Transition Times';; 20 ns
tTHL Time 25 75 10 40 7 25 ns
tpLH Propagation Delay 65 110 30 60 20 ns
tpHL 70 110 30 60 23 ns CL ~ 50 pF
tTLH Output Transition 75 135 40 70 30 45 ns Input Transition Times.;; 20 ns
tTHL Time 60 135 23 70 15 45 ns
NOTES:
1. Additional DC Characteristics are listed in this secti(;m under F4000 Series CMOS-Family Characteristics.
2. Propagation delays and 'output transition times are graphically described ·in this section under F400Q Series CMOS Family Characteristics.