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VZF defines the vertical zoom factor. The ACRTC performs the vertical zoom by modifying is video memory address so that

Dans le document GENERAL INFORMATION (Page 127-135)

---ZFR determines the horizontal and vertical multipliers

(1-16)

for zooming up. Zooming can only applied to the Base screen. HZF and VZF should be set to 0 for no-zoom and $F for

16

times zoom.

Note that zooming and scrolling horizontally together only can be done due to the following equations:

No. pixel/raster

--- = N

4

* (HZF

+ 1)

(4 bit/pixel mode)

No. pixel/raster

--- = N (8 bit/pixel mode)

2

* (HZF

+ 1)

With N must be an integer value.

• Horizontal Zoom Factor (HZF: bit

15 -

bit

12)

HZF defines the horizontal zoom factor in units of memory cycles. The ACRTC will output a single display address HZF times.

• Vertical Zoom Factor (VZF: bit

11 -

bit 8)

VZF defines the vertical zoom factor. The ACRTC performs the vertical zoom by modifying is video memory address so that multiples of the same raster data are displayed.

VZF/HZF Magnitude

=

HZF

+ 1

0

o

0 0 1

0

o

0 1 2

I 1

1 1

1 1 1 0 15

1 1 1 1 16

4-91

4.9.18 Light Pen Address Register (LPAR: rEC - rEF)

High-order Low-order

1 1 1 1 1 1 I 1 1 1 1 1 1 1 1 1 1

1

15

1

14

1

13

1

12

1

11

1

10

1

9

1

8

1

7

1

6

1

5

1

4

1

3

1

2

1

1

1

0

1

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

1---1

1 1 1 1 1 1 1 1 1 1 1 1 1 1

1 X 1 X 1 X 1 X 1 X 1 X 1 X 1 X 1 0 1 X 1 X 1 X 1 L P A H 1

1 1 1 1 1 1 1 I 1 1 1 1 1 1

High-order Low-order

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

1

15

1

14

1

13

1

12

1

11

1

10

1

9

1

8

1

7

1

6

1

5

1

4

1

3

1

2

1

1

1

0

1

I I 1 1 1 1 I 1 1 1 1 1 1 1 1 1 1

1---1

1 1

1 L PAL 1

1 1

LPAR is a read only register. When the ACRTC LPSTB input is asserted, the current display address is latched into the LPAR.

The value in LPAR will differ from the actual display address under the light pen depending on various hardware delay times.

Thus., the LPAR value should be adjusted by host software depending on system configuration.

*

Light Pen Address High (LPAH: rED bit 3 - bit 0) LPAH is only

significant 4 address.

valid if bit 7

=

0 and contains the most bits of the 20 bit graphic screen display

*

Light Pen Address Low (LPAL: rEE - rEF)

LPAL contains the least significant bits of the 20 bit graphic screen display address.

4.10 Drawing Control Registers

The ACRTC refers to a number of registers during graphic drawing operations.

a) Pattern RAM

b) Drawing Parameter Registers

The Pattern (RPTN, WPTN) Registers are Register (RPR,

Colour 0 Register (CL0) Colour 1 Register (CLl)

Colour Comparison Register (CMP) Edge Colour Register (EDG)

Mask Register (MASK)

Pattern RAM Control Regiser (PRC) Area Definition Register (ADR) Read/Write Pointer (RWP)

Drawing Pointer (DP) Current Pointer (CP)

RAM is accessed using the Read and Write Pattern commands (see Appendix I). The Drawing Parameter accessed using the Read and Write Parameter WPR) commands.

Table 4-13 shows the Drawing Parameter Register locations.

Abbre. ~~~~~D'-OA,,,"TA~(7H-'-,.)-=-,...-o-o--=---+-~ DATA (L)

15 I 14 I 13 I 12 I 11 I 10 I 9 I 8 7 I 6 I 5 I 4 I 3 I 2 I 1 I a

CS RS ~W Reg. No. Register Name 1 - -

-0 -0 a AR Address Register AR Address

0 a 1 SR Status Register SR CERIARDJCEDjLPDjRFFLRFRjWFRJWFE

V6 rOO FIFO Entry FE FE

1. ra2 Command Control CCR ABTIPSEIDDMICDMIDRCI GBM CREIAREICEEILPEIRFEIRREIWREIWEE

1/0 r04 Oper alion Mode OMR M/SI STRIACPIWSSI CSK I DSK RAMI GAl I ACM I RSM

,.

/0 r06 Display Control DCR DSPI SEll SEa I SE2 I SE3 I AT R

- rOB

rlE (undefined)

1 r80 Raster Count R C R · · · · ... I R C

~,.~0~r~8~2~H~o=ri~ro~n~ta·71~S~~~c~.---~H~SR~~---~H~C~---~-'---~"~'~"-'-"-lr---~H~S~W~---~ r86 yertic;al_--,S+-yn_co-' ______ -+c'-V~S'='R-I---.-. -_. _' '_' ._._. ~~~ I

Va r88 Vertical Display VDR V D S

r84 Horizontal Display HDR H D S I . __ ~.~.____ I H D W V S W

j

~

Split Screen Width SSW

~--:::~~:-:--+-:! ---. - H ~ 9'

i-;-,-"o+-' ..;r9;;O+-Bc-lin-;-k---,C:;co--:n-;-tr--:col,---hBC"'R~+---,B"'OCO-;N71-__t__-ElOFF 1 ---I---SO~--I--ElOFF2

"'01 r92 HOrIZontal Window DISPlay, __

+H"-W::..R"-+_---.:.:H~W;:_::S'---~----...J---...,~_;c__-'-H~W'-'--'W'---l1.oi r94 ... I V W S ~

~ Vertical Window Display VWR ... J V W W _

~

!l~' r98 --+-,--+---C'X&.E,---,I---~~~C'X S

L,,: r9A Graphic Cursor I GCR -- -- -- -- -- I C Y S ~

Vb' r9C i --- I C Y E I

Note; 1 .. · .. High" level

: a .. ·"Low" level

4.10.1 Pattern RAM

The ACRTC contains a 32 byte pattern RAM. The Pattern RAM is used for pre-defining data for the graphic drawing operations.

A 16 by 16 bit pattern (or 16 sets of 16 by 1 bit) can be stored in the Pattern RAM as a binary representation of screen data. In this case, a two entry colour 'palette' corresponding to 0 and 1 data values is defined using the Colour 0 (CL0) and Colour 1

(CLl) registers.

To store colour patterns in the Pattern RAM it is divided into four equal segments of either 4 by 4 bit patterns or 4 sets of 4 by 1 bit patterns. In this case, during drawing the colour coded contents of the Pattern RAM are directly written to the video memory. The particular segment used is defined by the Pattern RAM Control register (PRC).

When multiple continuity can pointer.

drawing commands use a common be achieved by adjusting the

4-95

pattern,

pattern pattern scanning

4.1~.2 Colour ~ Register (CL~: Pr~~)

I I I I I 1 1 I 1 1 1 I 1 I I 1 I

I 15 I 14 I 13 1 12 I 11 1 l~ 1 9 1 8 I 7 1 6 I 5 1 4 1 3 I 2 I 1 1 ~ 1

I I I I I I I I , , 1 , , 1 , 1 ,

,---1

'I C L ~

I

, ,

When logical drawing data =~, the contents of CL~ are stored in the video memory. The value of CL~ corresponds with the bits/pixel mode used. For example in 4 bits/pixel mode CL~

contains the colour value for 4 pixel. If all pixel should be painted in the same colour, it is necessary to store the respective colour 4 times in the Colour ~ register.

4.1~.3 Colour

1

Register (CLl: Pr~l)

I I , , , I , I , I I 1 , , 1 , I

, 15 , 14 1 13 , 12 , 11 I l~ I 9 , 8 1 7 I 6 1 5 I 4 I 3 , 2 1 1 I ~ ,

I , 1 I 1 1 I 1 , 1 1 , , I 1 I I

,---1

1 ,

, C L 1 ,

1 ,

When logical drawing data = 1, the contents of CLI are stored in the video memory. The value of CLI corresponds with the bits/pixel mode used. For example in 4 bits/pixel mode CLI contains the colour value for 4 pixel. If all pixel should be painted in the same colour, it is necessary to store the respective colour 4 times in the Colour 1 register.

4.10.4 Colour Comparison Register ~MP: Pr02)

---I I I I I I I I I I I I I I I I I

I

15

I

14

I

13

I

12

I

11

I

10

I

9

I

8

I

7

I

6

I

5

I

4

I

3

I

2

I

1

I

0

I

I I I I I I I I I I I I I I I I I

1---1

II C C M P I

I I

---CMP defines a comparison colour for use with conditional drawing operations. Conditional drawing applies various logical comparisons between the drawing data and CCMP to determine if drawing should occur (refer to Appendix J-3). The value of CMP corresponds with the bits/pixel mode used and has to be programmed as the Colour registers respectively.

4.10.5 Edge Colour Register n;DG: Pr03)

I I I I I I I I I I I I I I I I I

I

15

I

14

I

13

I

12

I

11

I

10

I

9

I

8

I

7

I

6

I

5

I

4

I

3

I

2

I

1

I

0

I

I I I I I I I I I I I I I I I I I

1---1

I I

l E D G

I

I I

EDG defines the boundary edge colour for use with the PAINT command. In one mode, the edge is defined as the colour contained in the EDG. In another mode, the edge is defined as any colour except the colour contained in the EDG register. The values of EDG corresponds with the bits/pixel mode used and has to be programmed as the Colour registers respectively.

4-97

4.10.6 Mask Register (MASK: Pr04)

---, ---, ---, , , , , , , , , , , , , , ,

, 15 , 14 , 13 , 12 , 11 , 10 , 9 , 8 , 7 , 6 , 5 , 4 , 3 , 2 , 1 , 0 ,

, , , , , , , , , , , , , , , , ,

,---_._---,

I

M S K

"

, ,

---When performing data transfer and drawing of the video memory, MSK is used to mask bits upon which drawing and other logical operations should not be performed. If MSK bit is 0, the corresponding video memory bit is excluded from any logical operation. The values of EDG corresponds with the bits/pixel mode used and has to be programmed as the Colour registers

respectively.

4.10.7 Pattern RAM Control Register (PRC: Pr05

~

Pr07)

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

1 15 1 14 1 13 1 12 1 11 1 10 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 1

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

1---1

1 1 1 1 1

1 P P Y i p z C y i P P X 1 P P Y 1

1 1 1 1 1

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

1 15 1 14 1 13 1 12 1 11 1 10 1

9

1

8

1 7 1 6 1 5 1

4

1 3 1 2 1 1 1 0 1

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

1---1

1 1 1 1 1 1 1 1 1 1 1

1 PSY 1 0 1 0 1 0 1 0 1 PSX 1 0 1 0 1 0 1 0 1

1 1 1 1 1 1 1 1 1 1 1

---1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

I

1 15 1 14 1 13 1 12 1 11 1 10 1

9

1

8

1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 1

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

1---1

1 1 1 1 I

1 P

E

y i p z y i p

E

X 1 P

Z

X 1

1 I 1 1 I

- PRC specifies the size of the patterns used for drawing and the start point within the Pattern RAM for the pattern scan. The pattern size can be independently specified in X and

Y

dimemsions

(maximum 16 by 16 bits) •

* Pattern Start X (PSX: Pr06 bit 7 - bit 4) Pattern Start Y (PSY: Pr06 bit 15 - bit 12)

PSX and PSY specify the pattern scan starting point

Dans le document GENERAL INFORMATION (Page 127-135)

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