These sections describe the individual DEC21040 Ethernet Controller tests. These tests are not available on the MVME130x boards.
Entering DEC21040 without parameters causes all DEC21040 tests to run in the order shown in the table below, except as noted.
To run an individual test, add that test name to the DEC21040 command.
The individual tests are described in alphabetical order on the following pages.
None of these tests need any external hardware hooked up to the Ethernet port with the exception of the CNCTR test, which needs external loopback ÒplugsÓ in the AUI connector.
Table 3-5. DEC21040 Test Group Name Description
REGA Register Access
XREGA Extended Register Access
SPACK Single Packet Transmit and Receive ILR Interrupt Line Register Access ERREN ERREN and SERREN Bit Toggle IOR I/O Resource Register Access CINIT Chip Initialization
Executed only when speciÞed:
CLOAD Continuous Load
CNCTR Connector
DEC21040 - Ethernet Controller Tests
3 CINIT - Chip Initialization
Command Input
PPC1-Diag>dec21040 cinit
Description
This test checks the DEC21040 chip initialization sequence for proper operation while using interrupts and reading the initialization blocks and rings structures used for Ethernet communications.
Response/Messages
After the command has been issued, the following line is printed:
DEC21040 CINIT: Chip Initialization:...Running --->
If all parts of the test are completed correctly, then the test passes:
DEC21040 CINIT: Chip Initialization:...Running ---> PASSED
If any part of the test fails, then the display appears as follows:
DEC21040 CINIT: Chip Initialization:...Running ---> FAILED DEC21040/CINIT Test Failure Data:
(error message)
Refer to the section DEC21040 Error Messages for a list of the error messages and their meaning.
3
CLOAD - Continuous Load
Command Input
PPC1-Diag>DEC21040 CLOAD
Description
This test verifies that a continuous load can be placed on the controller by transmitting/receiving a sequence of packets totalling at least 1 megabyte of throughput, comparing the input data with the output data.
Response/Messages
After the command has been issued, the following line is printed:
DEC21040 CLOAD: Continuous Load:...Running --->
If all parts of the test are completed correctly, then the test passes:
DEC21040 CLOAD: Continuous Load:...Running ---> PASSED
If any part of the test fails, then the display appears as follows:
DEC21040 CLOAD: Continuous Load:...Running ---> FAILED DEC21040/ClOAD Test Failure Data:
(error message)
Refer to the section DEC21040 Error Messages for a list of the error messages and their meaning.
DEC21040 - Ethernet Controller Tests
This test verifies that the data path through the external (AUI or 10BaseT) connection is functional, by transmitting and receiving packets and comparing the data. This test requires the presence of an external loopback ÒplugÓ for AUI or 10BaseT.
Note It is recommended that the board under test not be connected to a live network while this test is running.
The suggested ÒloopbackÓ setup for AUI is an AUI-to-thinnet transceiver attached to a BNC tee with
terminators on each arm of the tee. For 10BaseT setup, an external shunt needs to be put in the 10BaseT socket (it cannot be connected to a live network).
Response/Messages
After the command has been issued, the following line is printed:
DEC21040 CNCTR: Connector:...Running --->
If all parts of the test are completed correctly, then the test passes:
DEC21040 CNCTR: Connector:...Running ---> PASSED
If any part of the test fails, then the display appears as follows:
DEC21040 CNCTR: Connector:...Running ---> FAILED DEC21040/CNCTR Test Failure Data:
(error message)
Refer to the section DEC21040 Error Messages for a list of the error messages and their meaning.
You can use the CF command to select the port to be tested (whether AUI or 10BaseT). The following example uses the CF command to select port 1 (the 10BaseT port), skipping port 0 (the AUI port).
Example:
PPC1-Diag>CF DEC21040 DEC21040 Configuration Data:
3
ERREN - PERREN/SERREN Bit Toggle
Command Input
PPC1-Diag>DEC21040 ERREN
Description
This test toggles the PERREN and SERREN (Address and Data Parity Error status) bits in the command register found in the PCI header address space to verify that this register functions properly.
Each bit is toggled (written) and then read to verify that they are indeed toggled.
Response/Messages
After the command has been issued, the following line is printed:
DEC21040 ERREN:PERREN and SERREN bit toggle:...Running --->
If all parts of the test are completed correctly, then the test passes:
DEC21040 ERREN:PERREN and SERREN bit toggle:...Running ---> PASSED
If any part of the test fails, then the display appears as follows:
DEC21040 ERREN:PERREN and SERREN bit toggle:...Running ---> FAILED DEC21040/ERREN Test Failure Data:
(error message)
Refer to the section DEC21040 Error Messages for a list of the error messages and their meaning.
DEC21040 - Ethernet Controller Tests
3 ILR - Interrupt Line Register Access
Command Input
PPC1-Diag>DEC21040 ILR
Description
This test sends all possible byte patterns (0x00 - 0xFF) to the Interrupt Line register in the PCI register space. It verifies that the register can be read and written for all possible bit combinations. It checks that the byte read is the same as the byte previously written to verify that the register holds data correctly.
Response/Messages
After the command has been issued, the following line is printed:
DEC21040 ILR:Interrupt Line Register Access:..Running --->
If all parts of the test are completed correctly, then the test passes:
DEC21040 ILR:Interrupt Line Register Access:. Running ---> PASSED
If any part of the test fails, then the display appears as follows:
DEC21040 ILR:Interrupt Line Register Access:..Running ---> FAILED DEC21040/ILR Test Failure Data:
(error message)
Refer to the section DEC21040 Error Messages for a list of the error messages and their meaning.
3
IOR - I/O Resource Register Access
Command Input
PPC1-Diag>dec21040 ior
Description
This test reads all the I/O resource registers (pointed to by the PCI Base Address register) and all the indexed registers read indirectly through the RAP index register, and CSR/BCR data registers. This test verifies that the registers can be accessed and that the data paths to the device are functioning.
Response/Messages
After the command has been issued, the following line is printed:
DEC21040 IOR: I/O Resource Register Access:....Running --->
If all parts of the test are completed correctly, then the test passes:
DEC21040 IOR: I/O Resource Register Access:....Running ---> PASSED
If any part of the test fails, then the display appears as follows:
DEC21040 IOR: I/O Resource Register Access:....Running ---> FAILED DEC21040/IOR Test Failure Data:
(error message)
Refer to the section DEC21040 Error Messages for a list of the error messages and their meaning.
DEC21040 - Ethernet Controller Tests