Furpose
You rrust srecify ene cr mere orerands in eaeh machine instructien staterrent to ~revide the data er the location of the data upon which the rracbine operatien is te be rerferrred. The operand entries consist of ene or ITore fields er subfields de~ending
on the format of the instruction teing ceded. They can s~ecify a register, an address, a length, and irrrr.ediate data.
You can code an operand entry either with syrrbels er ~ith self-defining terms. You can omit length fields or sutfields, which the assembler will compute for you from the otter operand entries.
General Specifications for Coding Operand Entries
The rules for coding operand entries are as felle~s:
• A comma must separate operands.
~Farentheses rrust enclese subfields.
8
A eonna rrust serarate subfields enclosed in parentheses.If a subfield is erritted because it is in implicit in a syrrtclic address, the Earentheses that ~ould
~have enclosed the sutfield rrust te erritted.
LM MVI
MVC
MVC
MVI MVI
•
4,
~/SAVE5
4 (12), C 'F'
'e
, /TO (80), FROM
•
o (80:S), 240(8)
II ~
4 (12), C'F' KEY C 'F'
/
'Implicit Address See 058
If twc sutfields are enclcsed in parentheses and separated ty corrrras,
tbe fcllcwing afflies:
~
- - - - - - - - t---j+----</e---\-,--- 1
-If both sutfields are orritted tecaus€ L 2,48(4,5)
they are irrflici t in a syItbclic
-•
entry, the separating comrra and the farentheses that ~culd have been needed must also re omitted.
If the first subfield is cmitted,
•
the comma that separates it frorr the second sutfield rrust be written as well as the enclosing parentheses.
If tte seccnd subfield is omitted,
•
the comma that separates it frorr the first subfield rrust be omitted, however, the enclosing parentheses rrust te written.
~OTE: Elanks must not appear within the cferand field, exceft as fart
~
of a character self-defining terrr or in tbe sfecificaticn cf a• character literal.
L
L L
MVC MVC
MVC
MVC
MVC
2,FIELD_
--... Implicit
I
Address See D5B I
2,48(4,5)
I
I ndex RegisterI
2,48
(r:s;--
is omitted/ ~ I
LengthI
3 2
(,,1
0) , 4 0 (1 0 ) SpecificationI
I
I
is omittedI
32 (8,10) ,40 (10)
32(16,6) ,48(6)
8\
TO (1;) , ,....F_RO_M _ _ _ ---.
Base Register implicit in symbolic address TO
32 (C'
I'
,5) ,=CL64'AI
B'~ .
Section D: Machine Instructions 81
~5A -- REGISTERS
Purpose and Usage
You can specify a register in an operand for use as an arithmetic accumulator, a base register, an index register, and as a general depository for data to which you wish to refer over and ever.
You must be careful when specifying a register whose contents have been affected by the execution of another machine instruction, the control program, or an IEM-supplied system macro instruction.
For some machine instructions you are limited in which registers you can specify in an operand.
Specifications
~he expressions used to specify registers must have absolute values;
in general, registers 0 through 15 can be specified for machine
instructions. However, the following restrictions on register usage
apply:
1. The floating-point registers (0, 2, 4, or 6) must be specified
~ for floating-point instructions:
• •
•
2. The even numbered registers (0, 2, 4, 6, 8, 10, 12, 14) must be specified for the following groups of instructions:
a. The double-shift instructions b. The fullword multiply and divide instructions
c. The move long and compare logical long instructicns.
3. The floating-point registers
o
and 4 must be specified for the•
instructions that use extended floating-point data:
Registers
3,AREA 4, FLTAREA
4,1 6,2 8,3 12,3
Both register operands must be even-numbered
REGISTER USAGE BY MACHINE
INSTRUCTIONS: Registers that are not explicitly coded in the symbolic assembler language l:epl:esent-at-ien----of machine instructions, but are nevertheless used by the assembled machine instructions, are divided into two categories:
1. The base registers that are implicit in the symbolic addresses specified. These implicit addresses are described in detail in D5B •
•
The registers can be identified
by examining the object cede of the assembled machine instruction
Oor
the USING in~t:ruction(s) that machine instructions in their operations, but do not appear evenL~ the asserrbled object code. They are as follows:
a. For the double shift and fullword multiply and divide instructions, the odd-numbered register whose number is one greater than the even-numbered register specified as the first operand.
b. For the Move Long and Compare Logical Long instructions, the odd-numbered registers whose number is one greater than the even numbered registers specified in the two operands. higher odd-numbered register is used to contain the value to be used for coreparison.
d. For the Translate and Test (TRT) instruction, registers 1 and 2 are also used.
e • For the Load Multi pI e (LM) and Store Multiple (STM)
instructions, the registers that lie between the registers
specified in the first two operands.
REGISTER--USA~ BY SYS'IEM:-
The--control program of the IEM System/370
D5B -- ADDRESSES
Purpose and Definition
You can code a symbol in the name field of a rr.achine instruction statement to represent the address of that instruction. You can then refer to the symbol in the operands of other machine instruction
statements. The object code for the IBM Systero/370 requires that all addresses be assembled in a numeric base-displacement format.
This format allows you to specify
DEFINING SY~BOLIC ADDRESSES: You define symbols to represent either relocatable or absolute addresses.
You can define relocatable addresses in two ways:
o
By using a symbol as the label in the name field of an assembler language statement or• By equa ~ing a symbol to a relocatatle instruction statements. Such address references are also called addresses in this manual. The two ways of coding addresses are:
~ Implicitly: that is, in a form
that the assembler must first convert into an explicit base-displacement form before i t can be assembled
Relocatability of Addresses
Addresses.ill the base displ-acement form are relocatable, because:
• Each relocatable address is the correct address after relocation.
NOTE: Absolute addresses are also assembled in the base-displacement form, but always indicate a fixed location in virtual storage. This
•
means that the contents of the base
· register must always be a fixed absolute address value regardless of relocation.,
Page of GC33-4010-4 Re'iised July 31, 1976 By T:-.JL: GN33-8207
Specifications
~ACHINE OR OBJECT COrE FORMAT: All addresses asserrbled into the object code of the IBM Systemj370 machine instructions have the format given in the figure below.
Format
RS SI SS RX
Coded or Symbolic Representation of Explicit Addresses
D2(B2) DI(BI)
DI (,BI) ,D2 (B2) D2(X2,B2)
S DI (BI}
R 1 and R3 represent registers
12 represents an immediate value L represents a length value
8 bits 4 bits 4 bits Operation
Code
Object Code Representation of Addresses
4 bits
112
bits 4 bitsBase . Displacement Base
Reg- I
Reg-I
ister ' ister
l ______
J ________ ~~
:'OP CODE! R1 : R3
, . . . . - .. - _I _ _ .. _ ' . . _ . . . .
The addresses represented have a value which is the sum of:
O.
A displacereent and8.
The contents of a base register.12
bitsDisplacement
Addresses
Implicit Address
An implicit address is specified
1
---l3Y-Cbd1ng one expres s icn~---nre-expression can be relocatable or absolute. The assembler converts all implicit addresses into their
• tase-displacement form before i t assembles them into object code.
The assembler converts im~licit
addresses into explicit addresses only if a USING instruction has
addressability, thus allowing implicit references. see F1e Explicit Address
An explicit address is specified by coding two absolute expressions as follows: The second (enclosed in parentheses)
• is relocated, the assembled address is relocatatle. If the base register contains a fixed absolute value
that is unaffected by program relocation, the assembled address is atsolute.
NOTES (for implicit and explicit addr ess es) :
1. An explicit base register designation must not accorepany an implicit address.
2. However, in RX instructions an
• index register can be coded with an implicit address as well as with an explici t---a:adress.
3. When two addresses are required,
LA 4,1500 14114IoI0Ij~~1
.---_...1...-1_"" ~
Always used as 11 1
base register for
I I
absolute add. ress Displacement between 0 and
/4095 I
I
IEND
Source Statement Object Code in Hex
D5C -- LENGTHS
Purpose
You can specify the length field in an SS-type instruction.
This allows you to indicate ex~licitly the number of bytes of data at a virtual storaqe location that is to be used ty the instruction. However, you can omit the length specification, because the assembler computes the number of bytes of data to be used from the expression that represents the address of the data.
Specifications
IMPLICIT LENGTH: When a length subfield is omitted from an SS-type machine instruction an implicit length is assembled into the object code of the instruction. The implicit length is either of the following:
1. For an implicit address (see D5B above), i t is the
O
length attribute of the first or only term in the ex~ressionrepresenting the implicit address.
2. For an explicit address (see D5B above), i t is the
• length attribute of the first or only term in the expression that represents the displacement.
For details on the length attribute of symbols and other terms see C4C.
EXPLICIT LENGTH: When a length subfield is specified in
e
an SS-type machine instruction, the explicit length thus defined always overrides the implicit length.NOTES:
•
1. An implicit or ex~licit length is the effective length.
I The length value assembled is always one less than the
•
effective length. If an assembled length value of 0 is desired, an explicit length of 0 or 1 can be specified.
2. In the SS instructicns requiring one length value, the allowable range for explicit lengths is 0 through 256.
In the SS instructions requiring two length values, the allowable range for explicit lengths is 0 through 16.
c
Length Attribute
ID5100l AoooIA1001
•
Section D: Machine Instructions 89
D5D -- IMMEDIATE CATA
Purpose
In addition to addresses, registers, and lengths, sorre machine instruction operands require immediate data. Such data is assembled directly into the object code of the machine instructions. You use immediate data to specify the bit patterns for masks or other absolute values you need.
You should be careful to specify immediate data only where i t is required. Co not confuse it with address references to constants and areas or with any literals you specify as the operands of machine instruction (for a compariscn between constants, literals, and immediate data, see C5).
Specifications
Immediate data must be specified as absolute expressions whose range of values depends on the machine instruction for which the data is required. The immediate data is
o
assembled into its 4-bi t or 8-bit tinary representaticn • according to the figure on the opposite page.Machine Instructions
Examples Object Code in Hex
SRP
A,B/~
~
'"
•
BC 11,AAA 1471Blolxxxxi
,
~~---~- AAA Address
18 •
STCM 3,~BBB IBE131Flxxxxi
CLI