DATA GENEEAL CCRPCBATION

lbe ~cdel 830 was a non-militarized medium scale ccmputer .itb high density core memory, dual c~eraticns, and flexible l/C.

'Ibe f!cdel E30 opera ted with a memcry management and prctecticr urit allowing memory expansicn to 256K tytes, FI:iviledged instructicns, protection for 1/0 devices. and both read end write protection for mait memory. Dual OFeration allcws any two

concurrently, each with rescurces. Fer example, 32

major systems frograms tc run full protected access tc s}stems terminals can time share in

EA~IC, while a tatch stream runs.

!be central processor was organized around four 16 bit accuaulatcrs cf ~hich twc could have teen used as index registers. !be multi-accumulator architecture reduced the number of in~tructions necessary to eXEcute a program. Full memory cycle time was 1000 nancseconds, eXEcuting arithmetic and lcgical instructins in one cycle.

'Ihe ~cdel 830 used 16 bit, single war:!, multifuDcticn instructions. For example, arithmetic and

lcgical instructions, in addition to their eight tasic

fu~ctions, acdified an operand, shifted the result, and/or tested tte result. Altogether a total of 256 variations cculd haVE been performed on each arithmetic and lcgical instructicn. Memory reference instructicDs moved data bet.een «emery and accumulators, and modified program flew.

I/O instructicns transfer data tetween accumulators and perifherals, and central those ~eripherals.

~ajcI subassemblies were packaged on a single printed circuit board. A single etched back panel mace all intertoard ccnnections. The Model 830 contained ~wo central pIccessor beards, and either contained or was wired fer a memory maragement and protection unit. There were seventeen sutassemtly ~lcts. The expansion chassis, which was mcunted below thE ccaFuter, had slots for seven I/O boaLds. The Mcdel 83C .a~ rack mountable. (23]

!te central processor of the Model 121C was organized aIcund four 16 bit accumulators. The comFuter had a full neacry cycle time of 1.2 microseccnds and executed arithmetic arc logical instructions in slightly mere than one cycle, 1.35 microseconds. Major sutassemblies are fackaged cn a single printed circuit board. A single etched tack panel, ~ith an integral power 5uPFly, makes all interboard ccnDections. Plug-in connectors are provided for

cem~cDly ~fECifiEd peripherals. The Model 1210 ccntained

CDe central frccessor board, cne memory board, and sFace for additicnal IEmory £oards and I/O subassemtly boards. The Mcdel 1210 ~cs rack mountable or table top mountable with four sutasseatly slots.

I~ gEneral, the Model 1210 was a scaled down vErsion of the Model 830 resulting in less capacity for expansion.

(22 ]

c.

^{SPERBl O~IVAC} CORPORATION

~he AN/UYK-20(V) manufactured by Sferry Univac was a

"militarized", general purpose 16 bit digital computer. It was physicall} and functionally Kodular in ccnstructiot and eXfandable in nature. The sys~em contained integral tlcwers and power sUffly, mcuntable on a 19 inch rack with Flug in cFtions. ltE entire system would pass through a 2: inch cFening.

Tre central processor was a microprogrammed ccntrcller using two's complement arithmetic, 8 or 16 cr 32 bit operands and 16 bit general purpcse registers. The central fIccessor used either 16 or 32 bit instructicns, had direct addressing to 65K words and indexed via general registers. 1he central processcr contained a power fault

€natling autcmatic restart.

Main storage was expandable from 8K tc 65K wcres ~n

8K increm€[ts. The read/restcre cycle time was 750 nancseconds.

!ee central processor had a MATH ~AC opticn which included floating fcint, sguare root, trigonometric and hYFerbclic, dcuble precision multiply, and dcuble prEcision

add capatilities.

Cccling internal tlc~ers.

~as by circulation of ambient air by

~hreE general purpose fully sUFForted software packages ~er€ available. The .f Ie vel 1" system functions available u~der cperator control from an cn-line kelbcard consisted cf the following major components: core re~ident

Ioutines, litrary subroutines, loader subsystems, utility sutsystems, ^~ystEm tape generators, and a tasic asse~bler.

The system ^c~erated· 'liith a miminum of 16K werds of memcry, a key board, ard a Fapertape reader/punch. The IIlevel 211 system wa~ a «cre comFrehensive support system than level 1.

The majcI cCt~iderations in "level 2" was a eMS-2M cOIIpiler which reguired a minimum of four magnetic tape units for eMS-2M comfilaticns. The third level was a standard real time executive for real time systems. [10,2EJ

Ihe individual specifications cn each syste« are listed in AFEer.dix A.

AtEE

A~AC

. . . . . . . . . . . .

APPENDIX D

GLOSSARY OF TERMS

Automatic Data Precessing Eguipment AFFlied Technology Airtorne Comfuter ATE ••••••• Air Transportable Rack

EEl ••••••• fits Per Inch

CFA ••••••• Ccmputer Family Architecture CMS-2 ••••• Ccmpiler monitoring system-II ECM ••••••• ElectIcnic Countermeasures

EC~D •••••• Extended Cere Memory Unit EMI ••••••• Electrcmagnetic Interference ECE ••••••• Electrcnic Order of Battle EEL ••••••• Electrcnic Parameter List EW •••••••• Electronic Warfare

LA~ES DPU . light Airtcrne Multi-purpose System Data EIccessing Onit

LEt ••••••• light Emitting Device

MTEF •••••• ^~Ean Time Between Failure

M~7B •••••• fean Time To Repair

MAGIS ••••• ~arine Air Ground Intelligence System NIES •••••• tiaval Intelligence Processing System N1tS •••••• !aval Tactical Data System

TEEPES •••• ^~actical Electronic Reconnaissance Processing and Evaluation Segment

1.

Univac Federal Systems Division, lechnical Manual for CP-ECa iinital Data Comr.uter, p:-i='-t]ru J=~o-,-TaEle

';-rctctef~,~o7.

----

---~--Cant~cl tata Corporation, CDC-9~4C ]j§~ ~tof~g§ yni!, f. 1-1 tbru 4-10.

Matcrcla Inc. Government Electrcnics Division, Motorcla's TctalscQQe _D_i_snla^v _Sn_e_c_i_f_i_cati_o_D _I_i_s_t,

~ectIoD~-'.O-~Eru~~7 ^L ~ ~

un~v~c Federal ~ystems Division, In.Eu1LCutput ~~l.Qc~r£

p~~~~§~~ I1f§ j~]l, p. 1-6, October

i~67-.-6. CalifolIia Ccmnuter Products, Dinital flcj!§! ~od~1 ~~l, p. 1-1 thru

Naval Electronics Laboratory Center, Data TransmissioQ and S~itching Slstem and Marine Integrated F~rE-ana-AIr

~U-.Efcr~-~Y1~m-~rocessor RenuIrements;-~-y-R:~:- ~'!ear-,

p:

1~=~~~ ~lprIT-T975:

--~---DeADg€l~

s.

and Jorgensen, P., Mathematics fer Data

~!gf~§§~~~, F. 315-335, McGraw-HiI~-]ocX-~ompany~ 1~7TI7

Naval Electrcnics Syste~s

12. Couoer, J.D. and Knapp, R.W., l§c~~i~~~, Jchn Wiley Sons, 1974.

13. SharFe, i.F., The Economics of ~o!E~te!§, Columbia Oniversity

Pr€ss;-190~7---14.

15.

DepartmEnt cf the Navy Military Specification MIL-E-1E4COG(NAVY)t Electronic_L Inter~cr Communication and Navjcation EOu1Qmen~~-Navar SRIp-ana-Snore.L--neneraI

~E§f~I1S]!IcB; P:-l~5~-~4-necemD€r 1~7~.---

~---16. ROL~ (cIF., Technical ~ata

A!L]1~=jjJl1, August 1974.

----

Model

^l.§Ol.L

17. p. 1-43,

18. p. 46-48, 1

19. Naval Electronics Systems Ccmmand, A~]YK-20J!1

!Y-16

]udS§tgfl ~§tl~~!es, 23 June 1975.

~1. Tactical Infcrmation Processing and Interpretation Prcaram Office, Electronics Systems tivision, Hanscom

AFB~ Contract FJ9628-73-C-0008, MAGIS life Cycle Cost A~~ljsi§ f££ !~e ~arine !lrLGro~]a~nt~111~TIce-~ls!e!;

ny ^I.i.

Kl~ng€nDerg, J.G. ~acnonaIa, ~.t. -a~II€r J]., J.J. Walsh, p.l-1 tnru 3-85, 30 June 1975.

24. General Services Administration 41 CFR 1-1.000, Cede of Federal Renulations on Public Contracts and

frc

ⁿert-l

~gD~g§!~~!;~:-~=lo9, i-JuIy-'~13~--- --- ---~---25. General Services Administraticn Part. 1C1-32,

Gcvernemt-wide Automated Data _M_a_n_an_em_€_D_t _S_e_r_v_2_c_e_s, p.

J~TI3=31~J;-'t-FeDruary-197o:- ~

26. Sperry Univac Defense Systems, !!L£l!=l~lYL ~Yff~t

~Q!!.!~fs·

27.

28.

29.

30.

.3 1 •

33.

Naval Research Laboratory, ARMYLNAVY Comnuter Famil~

Architecture Selection com~T~tee~ -~~orts cf--2~

~€plEmter-lg7:,-1b-ITC~oE€r i~7S;-'2-December 197: and 19 ~arcc 1976.

Marine Corps Development and Educatio~ Center, Results of Intell~gence Anallsis Center Life Cvcle cost-~~ual-;

1"9 SEftEiirer i"974:--- --- --- - - -~--- ----HOLM Cer~.t Summa~ of ~ualification Test Reocrt Medel

1Li~, ~. 2-~,-nctoner-1971~--- ---- -

---Naval Air Develcpment Center Anal~sis of the CMS-2 PronLamming LaBnuane, prepared

6y

Ray~nEon -ComFaDy~--i

nec~iE€I-1S71:-~--~-34.

F~eet Ccmtat Direction Systems Suppcrt Activity San

~§~4~' ~]S=1Q gr2g£am~e~~§ ~~ference ~~~~~1, 15 CctcbBr

Department of the Navy, NTDS Advanced ~~~a ~~nag§~€n!,

Naval Snip Engineering

C€nter,-1~7~7--DatafIC Research Corp., Data~ro 7C The EDP ~~~~f~s

~i~l!, F. 70t-010-90a

tnru-7UU-U10-9Uw,-,~7~:-Madnick, S.E. and Donovan, ^J.J.~ Oneratinn SvsteIs, p.

'Iimareck, E. M., "Computer Selecticn Methcdclcgy",

~2!fu1j~s ~~f1~1§, v.5, p. 199-217, December 1973.

Naval iarfare Research center

4

^{Marine EW Aircr~ft}

jD~11s1~, by K.R. Ausich, p. 1-1 , 2E-~uIy

~75:---Naval Wa~fare Research Center, MEthods AirtcrDE ECM Effectiveness---~or­

In!~I£lf~ioB~-DY

K.R7-AusIcn,-.~75.---45. ITEK( A1AC AEElied Technologl !~l~]f~] ~CMfO!EQ,

ApplIEd

lEcnnology~-'~75:---46. Coofers and Lybrand, certified Public Acccuntants,

l~t§f~~J ~!af! ~tu£11 San Francisco, Ca.

1 •

De~artmeDt cf Computer Science Naval Ec~tgraduat€ School

Mcnt€rey, California 93940

Professcr N.F. Scheidewind, Code 55S5 (advisor) Department of Cperat~ons Research/Administrative

Sc~eDces/Ccmputer Sc~ence

Naval fcstgraduate School Monterey, California 93940

CDR. C.P. Gibfried, Code 55GF/52GF Department of Com~uter Science Naval fc~tgraduate School

Dans le document Monterey, California (Page 90-100)