(Continued)
20
Input or Output Cycles. Figure 7 shows the timing for an I/O read or I/O write operation.
During I/O operations, the CPU automatically
inserts a smgle Walt state (Tw). This extra Walt state allows sufficient time for an I/O port to decode the address from the port address lines.
CLOCK
WAIT __
+-__
~__ -r __________
~~~~110 { READ OIiERATION
{ WR
W"I~~
OPERATION Do-D7
---1:=======~::==~~~===j
DATA OUTNOTE Tw* = One Walt cycle automatIcally Inserted by CPU
Figure 7. Input or Output Cycles
Interrupt Request/Acknowledge Cycle. The CPU samples the mterrupt signal wIth the ris-mg edge of the last clock cycle at the end of any instruction (Figure 8). When an interrupt is accepted, a speCIal Ml cycle is generated.
During this Ml cycle, IORQ becomes active (instead of MREQ) to indicate that the inter-rupting device can place an a-bit vector on the data bus. The CPU automatically adds two Wait states to this cycle.
T, T,
CLOCK
AO-A15 ____________
+_-fl~---~~_4---_+~~--_4+__4+_~~--WAIT ____________
-r ________________________
~~--$_-JDO-D7========j~~---E!~=~~=~~~~~== -r=
NOTE: 1) TL = Last state of preVIOUs Instruction 2) Two Walt cycles automatIcally Inserted by CPU(*)
Figure 8. Interrupt Request/Acknowledge Cycle
2005-884, 885
CPU Timing
(Co~tinued)
2005-0218. 886
Non-Maskable Interrupt Request Cycle.
NMI is sampled at the same time as the mask-able interrupt input INT but has higher prIOrity and cannot be disabled under software control.
The subsequent timing is similar to that of a
CLOCK
normal instruction fetch except that data put on the bus by the memory is ignored. The CPU Instead executes a restart (RST) operation and jumps to the NMI service routine located at address 0066H (Figure 9).
AO-AUI _ _ _ _ _ _ _ _ _ _ _+J''l---+----..,;.:....---+J~'---+_-_+----+'~
'" Although NMI IS an asynchronous mput, to ~antee Its bemg recogmzed on the followmg machme cycle, NMI's fallIng ,edge
must occur no later than the rlsmg edge of the clock cycle preceding TLAST.
Figure 9. Non-Maskable Interrupt Request Operation Bus Request/Acknowledge Cycle. The CPU
samples BUSREQ with the rising edge of the last clock period of any machine cycle (Figure 10). If BUSREQ is active, the CPU sets its address, data, and MREQ, IORQ, RD, and WR
T,
CLOCK
lines to a hIgh-impedance state with the rising edge of the next clock pulse. At that time, any external deVIce can take control of these lines, usually to transfer data between memory and I/O deVIces.
T, T, T,
AO-Au
===========t=~---I.I----~~----+-(
®--iinT
---+---NOTE. TL = Last state of any M cycle. TX = An arbItrary clock cycle used by requesting deVice.
Figure 10. Z-BUS Request! Acknowledge Cycle
21
CPU Timing (Continued)
22
Halt Acknowledge Cycle. When the CPU receives a Halt instruction, it executes NOP states until either an INT or NMI input is
received. When in the Halt state, the HALT output is active and remains so until an inter-rupt is received (Figure 11).
M1 "I_ M1 ~ I" M1
CLOCK~T'
T, T, T, T. T, T,• H
H A L T = =
Rec.lved ~_. _ _ _ _ _ _ _ _ _ _ _ _
iiMi
U-NOTE: INT will also force a Halt eXIt. *See note, Figure 9.
Figure 11. Halt Acknowledge Cycle
Reset Cycle. RESET must be active for at least three clock cycles for the CPU to properly accept it. As long as RESET remains active, the address and data buses float, and the control outputs are inactive. Once RESET goes
CLOCK
inactive, three internal T cycles are consumed before the CPU resumes normal processing operation. RESET clears the PC register, so the first opcode fetch will be to location 0000 (Figure 12).
_ M .
-T, T,
AO-A11 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
~-1~~(~----~~~---_t~l_---@J-'-_____
~,...~~
FLOAT______
~---III ____________________________
---J!
;J&R~
.u!l---2T2TZTZTZT2T7T---~·~'l---\-~::::=====
HALT
Figure 12. Reset Cycle
2005·887, 888
AC Characteristics
Z8D CPU Z8DA CPU Z8DB CPU Z8DH cPut
Number Symbol Parameter Min Max Min Max Min Max Min Max
TcC Clock Cycle TIme 400' 250' 165' 125'
2 TwCh Clock Pulse WIdth (HIgh) 180' 110' 65' 55'
3 TwCl Clock Pulse WIdth (Low) 180 2000 110 2000 65 2000 55 2000
4 TfC Clock Fall TIme 30 30 20 10
5-TrC Clock RIse TIme 30 30 2 0 - 1 0
-6 TdCr(A) Clock I to Address Vahd Delay 145 110 90 80
7 TdA(MREQf) Address Vahd to MREQ 125' 65' 35' 20'
I Delay
8 TdCf(MREQf) Clock I to MREQ I Delay 100 85 70 60
9 TdCr(MREQr) Clock I to MREQ 1 Delay 100 85 70 60
10 - TwMREQh - - MREQ Pulse WIdth (HIgh) - - - 1 7 0 ' 110' 65'
45'-11 TwMREQI MREQ Pulse WIdth (Low) 360- 220' 135' 100'
12 TdCf(MREQr) Clock I to MREQ I Delay 100 85 70 60
13 TdCf(RDf) Clock I to RD I Delay 130 95 80 70
14 TdCr(RDr) Clock 1 to RD 1 Delay 100 85 70 60
15 - TsD(Cr) - - - Data Setup TIme to Clock 1 - - -50 35 30
30-16 ThD(RDr) Data Hold TIme to RD 1 0 0 0 0
17 TsWAIT(Cf) WAIT Setup TIme to Clock I 70 70 60 50
18 ThWAlT(Cf) WAIT Hold TIme after Clock I 0 0 0 0
19 TdCr(Mlf) Clock 1 to MI I Delay 130 100 80 70
20 - TdCr(Mlr) - - Clock 1 to Ml 1 Delay 130 100 8 0 - 7 0
-21 TdCr(RFSHf) Clock 1 to RFSH I Delay 180 130 110 95
22 TdCr(RFSHr) Clock I to RFSH I Delay 150 120 100 85
23 TdCf(RDr) Clock I to RD 1 Delay 110 85 70 60
24 TdCr(RDf) Clock I to RD I Delay 100 85 70 60
25 - TsD(Cf) - - - Data Setup to Clock I dunng - - 60 50 40
30-M2 , M3 , M4 or Ms Cycles
26 TdA(IORQf) Address Stable pnor to IORQ 320' 180' 110' 75'
27 TdCr(lORQf) Clock 1 to IORQ I Delay 90 75 65 55
28 TdCf(lORQr) Clock I to IORQ I Delay 110 85 70 60
29 TdD(WRf) Data Stable pnor to WR I 190- 80' 25-
5-30 - TdCf(WRf) - - Clock I to WR I Delay 90 80 7 0 - - 6 0
-31 TwWR WR Pulse WIdth 360' 220' 135'
100-32 TdCf(WRr) Clock I to WR I Delay 100 80 70 60
33 TdD(WRf) Data Stable pnor to WR I 20' -10- -55-
55-34 TdCr(WRf) Clock I to WR I Delay 80 65 60 55
35 - TdWRr(D) - - Data Stable from WR 1 120- 60- 30-
15--36 TdCf(HALT) Clock I to HALT 1 or I 300 300 260 225
37 TwNMI NMI Pulse WIdth 80 80 70
60-38 TsB USREQ( Cr) BUSREQ Setup TIme to Clock I 80 50 50 40
* For clock periods other than the mlnlmUms shown In the table, calculate parameters uSing the expressions In the table on the followmg page
r Umts In nanoseconds (ns) All bmmgs are prehmmary and subject to change
23
AC Characteristics (Contmued) Coil leu late parameters usmg the followmg expreSSlons Calculated values above assumed Ire = TIC = 20 os
r Umts m nanoseconds (os) All bmmgs are prehmmary and subject to change
Footnotes to AC Characteristics
110
Absolute
under Bias ... Specified operating range Voltages on all inputs and
outputs with respect to grol,lnd . -0.3 V to + 7 V Power Dissipation ... 1.5 W
The characteristics below apply for the following standard test conditions, unless otherwise noted. All voltages are referenced to GND (0 V). Positive current flows into the referenced pin. Available operating temperature ranges are:
* See Ordermg InformatIon sechon for package temperature range and product number.
Symbol Parameter
VILe Clock Input Low Voltage VIHe Clock Input High Voltage VIL Input Low Voltage VIH Input High Voltage VOL Output Low Voltage VOH Output High Voltage Icc Power Supply Current
Z80 Z80A
zaOB
ILl Input Leakage Current
Iw 3-State Output Leakage Current in Float For mdJtary grade parts, ICC IS 200 rnA
2 TYPIcal rate for Z80A IS 90 rnA.
Symbol Parameter CCLOeK Clock CapaCItance C IN Input Capacitance C OUT Output Capacitance TA ~ 2soe, f ~ I MHz.
Stresses greater than those hsted under Absolute MaxI' mum Ratmgs may cause permanent damage to the device.
ThIS IS a stress rating only; operatIon of the device at any condItIon above those IndICated in the operatIonal sectIons of these speclfIcatIons IS not Imphed. Exposure to absolute maXlmum rahng condItions for extended perIods may affect devIce rehablhty.
All ac parameters assume a load capacitance of 100 pF. Add 10 ns delay for each 50 pF
Ordering Product Pac:kage/ Product Package/
Information Number Temp Speed Description Number Temp Speed Description ZS400 CE 2.5 MHz 280 CPU (40-pin) 28400A CMB 4.0 MHz ZSOA CPU (40-pin) 28400 CM 2.5 MHz Same as above 28400A CS 4_0 MHz Same as above 28400 CMB 2.5 MHz Same as above 28400A DE 4.0 MHz Same as above 28400 CS 2.5 MHz Same as above 28400A DS 4.0 MHz Same as above 28400 DE 2.5 MHz Same as above 28400A PE 4.0 MHz Same as above 28400 DS 2.5 MHz Same as above 28400A PS 4.0 MHz Same as above 28400 PE 2.5 MHz Same as above 28400B CS 6.0 MHz ZSOB CPU (40-pin) 28400 PS 2.5 MHz Same as above 28400B DS 6.0 MHz Same as above 28400A CE 4.0 MHz 280A CPU (40-pin) 28400B PS 6.0 MHz Same as above 28400A CM 4.0 MHz Same as above 28400H PS S.O MHz 280H CPU (40-pin) 'NOTES: C = Ceramic. D = Cerdip. P = Plastic; E = -40'C to +85'C, M = -55'C to + l25'C, MB = -55'C to + l25'C wlth
MIL·STD-883 Class B processmg, S = O'C to + 70'C.
26 00-2001'()3
Zilog
Features
General Description
2032-0125, 0126
• Transfers, searches and search/transfers in Byte-at-a-Time, Burst or Continuous modes.
Cycle length and edge timing can be pro-grammed to match the speed of any port.
• Dual port addresses (source and destination) generated for to-I/O, memory-to-memory, or I/O-to-I/O operations.
Addresses may be fixed or automatically incremented! decremented.
• Next-operation loading without disturbing current operations via buffered starting-The 2-80 DMA (Direct Memory Access) is a powerful and versatile device for controlling and processing transfers of data. Its basic function of managing CPU-independent transfers between two ports is augmented by an array of features that optimize transfer speed and control with little or no external logic in systems using an 8- or 16-bit data bus
Memory Access Controller Product
Specification
September 1983
address registers. An entire previous sequence can be repeated automatically.
• Extensive programmability of functions.
CPU can read complete channel status.
• Standard 2-80 Family bus-request and prioritized interrupt-request daisy chains implemented without external logic.
Sophisticated, internally modifiable inter-rupt vectoring.
• Direct interfacing to system buses without external logic.
Transfers can be done between any two ports (source and destination), including memory-to-I/O, memory-to-memory, and I/O-to-I/O. Dual port addresses are automatically generated for each transaction and may be either fixed or incrementing/decrementing. In addition, bit-maskable byte searches can be performed either concurrently with transfers or as an operation in itself .
Figure 2. Pin Assignments
27