routine and (2) to fetch a core load. It may be used for either or both of these functions on any single entry.
[f called to fetch and transfer control to a core load, phase 2 first fetches and processes the core image header and then the disk I/O subroutine required by the core load to be fetched if it is not currently present in the Resident Monitor. The last thing it does is to fetch and transfer control to the core load itself.
Special Techniques. Upon entry, phase 2 requires the disk call subroutine placed at $HASH +8 through
$HASH+19 by phase 1. Using this disk call sub-routine, phase 2 is able to overlay itself when fetch-ing a core load. Included in this subroutine, at
$HASH+13 through $HASH+19, is the coding that moves the transfer vector from its position at the end of the core load (as it exists on disk) to the end of COMMON in core storage. Once the transfer vector has been moved, control passes to the core load being fetched.
CORE LAYOUT
Figure 4 shows the layout of the contents of core storage following an entry to the Skeleton Supervisor at $EXIT when DISKZ is present in the Resident Monitor 0 In panel 1, phase 1 of the Core Image Loader has been fetched by the Skeleton Supervisor.
In panel 2, the Monitor Control Record Analyzer has been fetched by phase 1.
r'igure 5 shows the layout of the contents of core storage following an entry to the Skeleton Supervisor at $EXIT when DISKZ is not present in the Resident MonitoL In panel 1, phase 1 of the Core linage Loader has been fetched by the Skeleton Supervisor.
In panel 2, phase 2 of the Core Image Loader has been fetched by phase 10 In panel 3, DISKZ has been fetched by phase 2. In panel 4, the Monitor Control Record Analyzer has been fetched by phase 1.
Figure 6 shows the layout of the contents of core storage following an entry to the Skeleton Supervisor
COMMA, Skeleton Supervisor DISKZ
Core Image Loader, Phase 1
COMMA, Skeleton Supervisor DISKZ
Figure 4. Core Layout on Supervisor Entry at $EXIT (DISKZ in Core)
at $DUMPo In panel 1, locations $CIBA+l through 4095 have been saved on the CIB and phas'8 1 of the Core Image Loader has been fetched by the Skeleton Supervisor. In panel 2, the System Core Dump program has been fetched by phase 1 as the result of a non-negative parameter following the branch to
$DUMP. In panel 3, the Auxiliary Supervisor has been fetched by phase 1 as the result of a negative parameter following the branch to $DUMP.
CD CD CD 0
COMMA, COMMA, COMMA, COMMA,
Skeleton SkeletQn Skeleton Skeleton
Supervisor Supervisor Supervisor Supervisor
DISK1 DISK1 DISKZ DISKZ
or or
DISKN DISKN
Core Image Loader, Phase 1
Figure 5. Core Layout on Supervisor Entry at $EXIT (DISKZ Not in Core)
Figure 7 shows the layout of the contents of core storage following an entry to the Skeleton Supervisor at $LINK when the program being linked to is in disk system format (DSF). In this case DISK1 or DISKN is currently present in the Resident Monitor. In panel 1, phase 1 of the Core Image Loader has been fetched by the Skeleton Supervisor, Low COMMON has been saved by phase 1, and the LET/FLET search buffer has been allocated. In panel 2, COMMON defined by the previous core load below location 4096 (if any) has been saved on the CIB by phase 1. In panel 3, phase 2 of the Core Image
CD
COMMA, Skeleton Supervisor
Any Disk I/o
Subroutine Core Image Loader, Phase 1
That Portion
of Core Load
Above 4096, Not Saved On
CIB
CD
COMMA, Skeleton Supervisor
Any Disk I/o
Subroutine
That Portion
of Core Load
Above 4096, Not Saved On
CIB
0)
COMMA, Skeleton Supervisor
Any Disk I/o
Subroutine
Figure 6. Core Layout on Supervisor Entry at $DUMP
Loader has been fetched by phase 1; DISKZ has been fetched by phase 2. If DISKZ is currently present in the Resident Monitor, phase 2 is not called as shown in panel 3. In panel 4, phase 0/1 of the Core Load Builder has been fetched by phase 1 of the Core 1m age Loader.
Figure 8 shows the layout of the contents of core storage following an entry to the Skeleton Supervisor at $LINK when the program being linked to is in disk core image format (DCI). In this case DISKZ is currently present in the Resident Monitor. In panel 1, phase 1 of the Core Image Loader has been fetched by the Skeleton Supervisor, Low COMMON
Section 7. Core Image Loader 29
~)
COMMA, Skeleton Supervisor
DISK 1 or DISKN Core Image
Loader, Phase 1 LET/FLET
Buffer Low COMMON
G)
COMMA, Skeleton Supervisor
DISK 1 or DISKN Core Image
Loader, Phase 1 LET/FLET
Buffer
COMMON Above
4096, Not Saved
@
8)COMMA, COMMA,
Skeleton Skeleton Supervisor Supervisor
DISKZ DISKZ
Core Load Builder,
Phase 0/1
Core Image Loader, Phase 2
Figure 7. Core Layout on Supervisor at $LINK (Link in Disk System Format)
has been saved by phase 1, and the LET/FLET search buffer has been allocatedo In panel 2, phase 2 of the Core Tmage Loader has been fetched by phase 1; the core image he ader buffer has been allocated by phase 20 In panel 3, the disk I/O sub-routine required by the program being linked to has been fetched into the Resident Monitor. In panel 4, the program being linked to has been fetched by phase 2. In panel 5, COMMON defined by the previous core load below location 4096, previously saved on the CIB by phase 1 of the Core Image Loader, as well as the program being linked to, has been fetched by phase 20 In panel 6, the portion of the program being linked to that is contained in the CIB (the portion below location 4096, placed in the CIB by the Core Load Builder) has been fetehed by phase 2.
DEBUGGING/ANALYSIS AIDS
To facilitate the finding of errors in and associated with the Core Image Loader, NOP instructions have been placed at critical locations in the Core Image
Loader; they are: CMOOO+l, CMI18-5, CM180, LDOOO+l, GETCL, and LDI00+8. These NOPs can be replaced by WAIT instructions so that core dumps can be taken at various stages during Core Image Loader execution. An analysis of the core dump(s) may provide enough information to locate the problem.
Bear in mind that the Core Image Loader is naturally relocatableo Thus, all modifications made to it must be executable irrespective of core location.
CD CD CD 0 CD CD
COMMA, COMMA, COMMA, COMMA, COMMA, COMMA,
Skeleton Skeleton Skeleton Skeleton Skeleton Skeleton
Supervisor Supervisor Supervisor Supervisor Supervisor Supervisor
DISKZ DISK1 Reikired Required Required Reikired
or Dis I/o Disk I/o Disk I/o Dis I/o
Core Image DISKN Subroutine SubrQlJtine Subroutine Subroutine
Loader,
Phase 1 Core Image Core Image
Loader, Loader,
LET/FLET Phase 2 Phase 2
Buffer Link
CI Header Core That
Buffer Load Portion
Low of
COMMON Core Load
Loaded From
CIB Link
COMMON Core
Load Below
4096, Restored
COMMON That
Above Portion
4095, of
Not Core Load
Saved Above
But 4095,
Not Placed
Overlaid In
Core By Core Load
Builder
Figure 8. Core Layout on Supervisor Entry at $LINK (Link in Core Image Format)
Section 7. Core Image Loader 31
FLOWCHARTS Phase 1 (IN): CLB01 Phase 2 (MC): CLB02
The Core Load Builder builds a specified mainline program into an executable core load. The main-line program, with its required subroutines (LOCALs and SOCALs included), is converted from disk system format (DSF) to a format suitable for execu-tion. During the conversion, the Core Load Builder also builds the core image header record and the transfer vector. The resulting core load is suitable for immediate execution or for storing on the disk in disk core image format (DCI) for future execution.
GENERAL COMMENTS
Each phase of the Core Load Builder has been broken up into a series of relatively small, self-contained subroutines. After initialization (phase 1) control remains in the Master Control subroutine, which is a part of phase 2. (The labels in this sub-routine all start with "MC".) In other words, the basic control logic is found in the Master Control subroutine.
The labels assigned to constants and work areas within subroutines are in the range 900-999. When-ever noted, even-numbered labels are on even boundaries, and odd -numbered labels are on odd boundaries. Constants and work areas in RCOM (phase 0) are mnemonic and are arranged in four groups, each ordered alphabetically. Double-word cells are in one group, indexed cells are in a second;
constants are in a third; and switches and work areas are in a fourth. The labels of switches are of the form "LSWx", where "x" is a number. The labels of constants are of the form "Kx", where "x" is either the number, in decimal, defined in the con-stant or the four hexadecimal digits defined in the constant.
Patch areas are usually found at the end of a phase.
Each one is defined by a BSS followed by a DC.