Control Registers for the R4000 CPU and Fol- Fol-lowersFol-lowers

The R4000 (the first CPU implementing the 64-bit MIPS III ISA) was a brave attempt to regularize some features of CPU implementations that were show-ing signs of gettshow-ing out of control and an attempt to provide a regular struc-ture for some irresistible feastruc-tures.

The most obvious change is that the caches now come under the control of a new instruction (really a set of instructions) calledcacheadditional features

60 3.4. Control Registers for the R4000 CPU and Followers

include an on-CPU timer, some debug facilities, and mechanisms for handling recoverable bit errors in the extensive cache. Also there’s a Config register that allows parameterization of some key features (cache size, cache line size, etc.) by communicating those parameters to the software that needs to know it.

We’ll introduce the registers that are just for cache management in Chap-ter 4 where we’re dealing with caches in general and the MMU/TLB registers in Chapter6.

3.4.1 Count/Compare Registers: The R4000 Timer

These registers provide a simple general-purpose interval timer that runs continuously and that can be programmed to interrupt. In most CPUs, it’s a reset-time configuration option whether the timer is wired to an interrupt.

The timer is always the interrupt input found atCause(IP7)(usually making the hardware input Int5* redundant).

Count is a 32-bit counter that counts up continually, at exactly half the CPU’s pipeline clock rate. When it reaches the maximum 32-bit value it overflows quietly back to zero. You can read Count to find the current time.

You can also writeCount at any time — but it’s normal practice not to do so.

Compareis a 32-bit read/write register. WhenCountincrements to a value equal to Compare, the interrupt is raised. The interrupt remains asserted until cleared by a subsequent write to Compare.

To produce a periodic interrupt, the interrupt handler should always in-crement Compareby a fixed amount (not an increment to Count, because the period would then get slightly increased by interrupt latency). The software needs to check for the possibility that a late interrupt response might lead it to setCompare to a value that Counthas already passed; typically, it rereads Count after writingCompare.

3.4.2 Config Register: R4x00 Configuration

CPU configuration is firmly CPU dependent, but all members of the R4x00 family have the Config register and share many of its fields. Figure 3.4 shows the set of flags provided by the original R4000 CPU.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

EC EP SB SS SW EW SC SM IC DC IB DB CU KO

CM BE EM EB

Figure 3.4: Fields in R4000’sConfigregister The fields in Figure 3.4 are as follows:

CM Set 1 for master/checker mode — applicable to fault-tolerant systems only. Set at reset time and read only.

EC This 3-bit field encodes the clock divider: the ratio between the internal pipeline clock and the clock used to run the system interface. In some CPUs, the system interface clock is the same as the input dock, and this acts as a multiplier for the internal clock; in older CPUs, the pipeline al-ways runs at twice the input clock rate, and this acts as a programmable divider for the system interface clock.

For the R4000, when the field holds the number n, the ratio is (n+ 2).

But the introduction of such clock ratios as 1.5 and 2.5 in later CPUs has forced a change of encoding. Refer to the individual CPU manual.

This field is (so far) set at reset time and read-only.

EP This 4-bit field encodes the transmit data pattern. The R4000 CPU and many of its successors have a system interface that has no external handshake signal on the multiple data of a cache line write-back cyde.

The CPU is capable of sending the data at one bus-width quantity per clock cycle. Because this is sometimes too fast For the interface to cope with, the rate and rhythm with which data is sent can be programmed here.

The following table shows the data pattern as a pattern of “D”; meaning a clock cycle where a word of data is sent, or “x”where the system interface rests for a clock:

Short patterns are repeated as necessary, so a write back of an 8-word (4-doubleword) cache line programmed with

Config(EP) == 5 would be “DDxxxxDD”. (Or would it be correctly writ-ten “DDxxxxDDxxxx”, implying a three-cycle quiet period on the bus?) Our experience is that many CPUs do not implement dead time at the end of a write but that some do. Ask your CPU supplier if this is impor-tant to you.

Most CPUs support only a subset of these values. Some use different encodings. The EP field is sometimes set at reset time and read-only and sometimes programmable here.

EP field Data pattern EP field Data pattern

0 D 8 Dxxx

1 DDx 9 DDxxxxxx

2 DDxx 10 Dxxxx

3 Dx 11 DDxxxxxxx

4 DDxxx 12 Dxxxxx

5 DDxxxx 13 DDxxxxxxxx

6 Dxx 14 Dxxxxxx

7 DDxxxxx 15 DDxxxxxxxxx

62 3.4. Control Registers for the R4000 CPU and Followers SB Off-chip secondary cache block size (or line size). This field is usually

hardware configured and read-only here. R4000 encodings are SB Value Block size

(32-bit words)

0 4

1 8

2 16

3 32

SS On the R4000 CPU, the off-chip secondary cache can either be operated as split (separate cache locations used for instructions and data, regard-less of their addresses) or unified (all treated the same according to their address). It is set 1 for split, 0 for unified.

SW On the R4000 (and maybe some others), it is set 1 if the secondary cache is 128 bits wide like the original R4000SC, 0 for 64 bits wide.

EW System interface width: 0 for 64 bit, 1 for 32 bit.

SC In R4000 and R5000 CPUs and their immediate descendants, this field is writable and acts as a software-controlled enable for the secondary cache; it is very useful for diagnostic purposes. It is set 1 if there is an on-chip controlled secondary cache, 0 otherwise.

Some later uniprocessor CPUs with provision for secondary caches re-port the secondary cache size in another field, recycling some bitfields that are used for multiprocessor purposes in R4000. However, typi-cally those size fields are just blindly passing on information received at power-on configuration time and have no hardware impact.

SM Multiprocessor cache coherenry protocol configuration.

BE CPU endianness (see Section 11.6): 1 for big-endian, 0 for little-endian.

On the NEC Vr4300 (at least) this field is software writable, but on most MIPS CPUs it’s part of the hardware configuration.

EM Data checking mode: 1 for ECC checking, 0 for per-byte parity.

EB Must be 0. There was once going to be a hardware interface option to do all cache refills/write backs in sequential order, rather than in sub-block order; this option has never been implemented.

IC/DC Size of primary I- and D-cache: A binary value n codes for a cache size of 2¹²⁺ⁿ bytes.

IB/DB Line (block) size of primary I- and D-cache: 0 for 4×32-bit words, 1 for 8×32-bit words.

CU Another multiprocessor cache coherency protocol configuration bit.

K0 This is a writable field that allows you to configure cache behavior for accesses in kseg0. The codes here are just the same as those that can be entered into the MMU tables to control caching on a page-by-page basis and appear to you as the EntryLo(C) field. Outside of cache-coherent multiprocessors, the only interesting standard values are 3 ==

cached and 2 == uncached.

Post-R4000 CPUs not offering multiprocessor cache facilities have used other values to configure different cache behaviors such as write through and write allocate — see Section 3.4for what those mean.

3.4.3 Load-Linked Address (LLAddr) Register

This register holds the physical address of the last-run load-linked operation, which is kept to monitor accesses that may cause a future store conditional to fail; see Section 5.8.4. Software access to LLAddr is for diagnostic use only.

3.4.4 Debugger Watchpoint (WatchLo/