Complexity Comparison

2.7.4.1 Expected Algorithm Complexity

Figure 2.12 presents the expected algorithmic complexity of the different phases of the concerned algorithms. Since the number of bits to be allocated in a particular phase varies from case to case for a particular algorithm, a precise comparison of complexity can only be made by actual execution of algorithms on hardware for a given channel scenario and target bit-rate, as performed below. Figure 2.12 also depicts the well-known high complexity of the greedy bit-filling approach as it requires N operations to allocate a single bit, where N indicates the total number of subcarriers. For the algorithm of

38 Chapter 2 : Bit-Loading Algorithm for Multicarrier Systems Figure 2.11 Reduction in Total Energy by means of Bit-Loading for different values of N ( Total No. of subcarriers ) and M ( M-ary modulation scheme per subcarrier when no bit-loading )

Figure 2.12Expected Algorithmic Complexity for Different Algorithms

Papandreou [15], although the initial and intermediate phases do not require extensive computations, the final phase depends on the factor B^{lef t}(the remaining bits that will be allocated using the greedy procedure), which when large can lead to high complexity because each bit allocation in this phase will require O(N) order of operations. Even for the cases where B^{lef t} is not large but the total number of subcarriers is large, the final phase of Papandreou algorithm renders large complexity because all the subcarriers have to be compared before allocation of a single bit.

In our proposed 3dB-subgroup allocation algorithm, we find that the initial phase

2.7 Simulation and Results 39 requires classification of sub-carriers with respect to 3-dB difference from the least atten-uated subcarrier where this classification can be efficiently implemented in a number of operations which is linear with respect to N. Final allocation requires further classifica-tion in different intervals whose complexity is also linear with respect to the number of subcarriersN. Finally theB^{lef t} number of bits are greedily allocated to the last interval, which requires only comparing the subcarriers belonging to the last interval and hence an eventual reduction in complexity.

2.7.4.2 Exact Number of Execution Cycles on a Processor

In order to have a precise complexity comparison, along with performing the theoretical complexity analysis, we also compared the concerned algorithms in terms of actual num-ber of execution cycles, when executed over a processor. Theoretical complexity analysis and a comparison of simulation times on any simulation tool, can only provide an approx-imate complexity comparison. Most simulation environments, like Matlab, are based on interperative languages and hence are very much dependent on the intermediate compiler.

Therefore, it is preferable to use some other method/tool to evaluate the exact number of cycles taken by an algorirthm.

In this regard, Simplescalar [61] is a popular tool, that enables extracting the param-eters (No. of execution cycles, energy consumed etc.) concerned with the execution of a given program, for a wide variety of processors. Therefore, we employed the Simplescalar tool, to extract the exact number of execution cycles taken by different bit-loading al-gorithms over a MIPS [80] processor architecture processor.MIPS (originally an acronym for Microprocessor without Interlocked Pipeline Stages) is a RISC (Reduced Instruction Set Computer) microprocessor architecture and is primarily used in embedded processors.

The default parameters of the Simplescalar tool, with which the algorithms were run, are shown in figure 2.13.

2.7.4.3 SimpleScalar Tool For Execution-Based Algorithm Complexity Anal-ysis

Simplescalar is an execution driven cycle accurate instruction set simulator (ISS) of a superscalar microprocessor [61]. A complete development chain (compiler, debugger, profiler) comes with the tool which allows the quick porting of any ANSI C application to Simplescalar. The Simplescalar toolset is composed of a gcc compiler ported for the

40 Chapter 2 : Bit-Loading Algorithm for Multicarrier Systems Figure 2.13 The Default values of the Superscalar Processor Architecture used by Sim-pleScalar

Simplescalar microprocessor which generates simplescalar binary files. The simplescalar microprocessor models an out-of-order superscalar architecture based on a RUU (Regis-ter Update Unit) . The RUU exploits a reorder buffer to automatically rename regis(Regis-ters and hold the results of pending instructions. However, completed instructions are retired in program order to the register file. The microarchitecture supports speculative exe-cution. The memory system uses a load/store queue and a rich set of cache memories with tunable sizes is also available. The detailed description of the Simple-Scalar tool alongwith its Superscalar MIPS architecture will be given in chapter 6, where we will adapt different processor parameters as a mean to further reduce the running-time of the bit-loading algorithm. In this context we keep the processor parameters constant for all the three compared algorithms so as to perform an exact execution-cycles based complexity comparison of the concerned algorithms.

2.7.4.4 Comparison of Number of Execution-Cycles

The simplescalar architecture parameters were kept same for all of the simulations. Asad1 indicates our earlier proposed method [21] wheresorting was used in the final allocation, whereas Asad2 represents our improvement in the algorithm where sorting is replaced with the interval-classification based final allocation, as presented in [22] as well. Figure 2.15 shows the number of execution cycles taken by different algorithms for the case where the number of subcarriers (N) is increased but the number of bits/subcarrier for the non-adaptive case is kept constant. The horizontal axis shows various simulation

2.8 Conclusion 41