IP/
PROFESS
;.
---- #7
PRINT REQUEST
PORT
I ·;..._ _ _.,
CARRI&,
432 PROCESS
.,,,,. .,,,,.
PRINT REPLY PORT
- -
-PRINT OBJECT
IP
Figure F-2 IP Performs Blocking Receive
--EJ
•RECEIVE"
function
F-11
iAPX 432 Interface Processor Architecture Reference Manual
IP DISPATCHING
PORT IP AP
(i---
414/ ,
- ...
CARRIER
,,..,
IP ~/
IP ~~/
•
PROCESSOR PROCESS~~IV OBJECT
~s/'
~'?/
1
/ / / / /(
I
PRINT I PRINT
REQUEST I REPLY
PORT
I PORT I
--
ICARRIER I
_.,
...
~ If' ~ I0 I
l
432
PROCESS
_..
-.-PRINT OBJECT
Figure F-3 GDP Executes SEND and Unblccks RECEIVE
F-12
DISPATCHING IP PORT
...
-SELECTED STATE SELECTED INDEX
IP PROCESSOR
INTERP~ CDMJN!CATICN AND DISPATCHING EXAMPLE
INTERRUPT ,--.._'
,,
....,
--~---''~/_.., ---~'--~--i
IP AP
PROCESS IP
'-
OBJECT IJ
PRINT REQUEST
PORT
,..--:nnTr-n l</'\l\l\11.:l\
STATE INDEX
)
432
PROCESS
..
PRINT REPLY PORT
PRINT OBJECT
•
Figure F-4 IP Responds to IPC
F-13
F-14
iAPX 432 Interface Processor Architecture Reference Manual
PRINT REQUEST
PORT
IP PROCESS
CARRIE
432 PROCESS
PRINT REPLY PORT
PRINT OBJECT
IP WINDOW
"ALTER MAP AND SELECT DATA SEGMENT" function
Figure F-5 WindCM Manipulation
PRI?>.'fT REQUEST PORT
INTERPIU:ESS CGMJNICATICN AND DISPATCHING EXAMPLE
.-
...
432 PROCESS
PRINT REPLY PORT
,~
PRINT OBJECT
IP
•sEND"
£unction
Figure F-6 Print Reply
AP
F-15
APPENDIX G
I
J:MPLEMEtilI'ATIOO NJrES
December, 1981 PORI' OPERATICN
The queue values ~laced in carriers are assumed by the micrcx..---ode to be in the ·correct ranqe (less than 2**14 and greater than or equal to -2**14). Incorrect deadline calculation will result from out-of-range values.
WINOOW OPERATIONS
If a fault occurs when executing an alter map operator in l~ical
mode, the windo.'1 should be invalidated befor.e retry is attempted, since, depending on the type of fault, the I/O lock for the obiect that the windCM was to have pointed to mav have already been set.
The base_disp pseudo-refinement mechanism is used when settinq up all rand.an windows; this includes winday 0 in random mode and windoo 1 in interconnect node. Therefore, a base 1isP of zero should be specified when initializing a window for interconnect access. (Note:
this pseudo-refinement only \-JOrks in loqical node.)
When an invalidate windCMs !PC or a resume Physical reference nx:rle
!PC is executed, or a fatal error occurs, all windCMs are irrmediately invalidated. If window 0 is open in block transfer.
node, then t.he invalidation mav terminate t.his window in the middle
-..C .L.1.-.!. - _._ _____ ..c __ _ ___ ,!,_, __ , __ .: __ L L - .: -.C---L.: _,_, -·---.1-1T.. ..; ... .a-i..-.,...,
U.L L.!1-L>::I l..LC:Ul:::>.Ll:::!L, J::JU:::>:::>.LU.l._y ..LUt:::l.Ll~ 1-l!C J.11.LVL!LICU .. J.\J!l \....ULL"'=ll"-·'-}' .LU \...U.;::;
buffer. · Also, no information is written into the winoCM status area on the number of blocks already transferred.
To avoid fatal errors, the processor data segment has to be large enough to accorrmoc:1ate the control window.
Forced termination is only valid for window 0 in buffer node.
The mapping faci Uty areas in the control windON disolay the actual block count (not block count minus one); this is also true for the
recrl and write counts.
The reserved field of the window 0 mapping facility area is actuallv written with the block count. 'Ihis has been done to alloo deterministic testing of the chip.
When force terminating window 0 (block rrode) , the updated entrv state in the mapping facility area of tl-ie control windcM will only slnw a chanqe in the transfer state fieln, the oriqinal values for.
transfer direction, validity, arrl rrcde will remain intact.
Change 2 C":rl
iAPX 432 Interface Processor. Architecture Reference Manual
The windCMed bit is checked and set several rnicrocycles after the data segment being windowed has been qualified. Consequently, when invalidating objects (clearing the storage allocated bit), software should wait at least 50 rnicrocycles before checking the windCMed bit of an invalidated data segment.
DISPATCH
When the dispatch operator executes and finds a orocess at the disoatch port, the current·· process is suspended before process selection (wake-up) is executed. At t.his time, any faults that occur will be processor level faults, since no process is currently bound.
Sirce a faulted process is not executable, it is l;X)Ssible to get into a situation where all processes are faulted arrl no functions can be executed via the control windav on the IP.
For Release 2.1, which adds a fault vector bit, at least one process
shoul~ have the fault vector bit set in the the orocess status.
FAULT HANDLTI\G
C.ontext and Process level faults which occur when a Process is not bound to the processor are treated as processor level faults.
GENERAL
The IP INSERI' SJDRI' ORDINAL ooerator takes slightlv different inout data fran the GDP INSERI' SHOR!' ORDINAL ooerator; please refer to Al:;.pendix B of this document.
The first reserved slot in the IP processor object (bvte disolac~ment 28) has been changed to pso:r_obj_ad and should contain an AD to the processor object itself.
The nnst significant 10 hits in the operator ID double-bvte in the fault information area are undefinen and -can take arbitrarv values. The least significant 6 bits contain the ID code itself.
-It is advisable that IP process objects be frozen, since when a selection of an unfrozen process is attempted, a processor level fault occurs arrl the M! rrust ship the process off explicitly to the fault port.
The context faulted bit in the process context status is onlv cleared when the microcode context fault handling routine exits nor..mally. If a process fault ocqurs, e.g. address develooment, then tl-\e process is
sent to the fault port with both context and process faultecl°bits set.
Thev sh:>uld, therefore, be cleared by the process fault handler.
G-2 Change 2
IMPLEMENI'ATIOO IDIBS
When qualifying the control wintJc:M :refinement of the processor rl.ata segment, neither the tvPe of the refinement oo:r the tvoe of the base oh]ect is tested. ···
If a fault occurs during processor qualification, it is considered a physical m.:>de fault ·and the processor returns to ohvsical mode. (The
processor is set to l<XJical node at the verv en~ of processor qualification.) HCMever, the processor object may have been locked and the control windav rnav have already been chanqed.
The REI'RIEVE TYPE DEFINITICN OPERATOR returns an exact imaqe of the AD which is 1n the tvpe descriptor. Any riqhts which are oiacea into that AD will aloo be in the AD that is returnerl when the ooerator is executed.
Chanqe 2 G-3
iAPX 432 INTERFACE PROCESSOR ARCHITECTURE REFERENCE MANUAL 171863-003