The links of the transputer used on the 8003 are capable of running at 20 Mbits/s, at which speed they will not tolerate skew introduced by buffering.
Links 2 and 3 of each transputer which are connected within the 8003 have a simple series termination on the LinkOut signal. The termination resistor of 47 ohms, combined with the output impedence of the LinkOut circuit, gives a termination impedence marginally below 100 ohms.
Links 0 and 1, which are brought to the edge connector, also have 47 ohm resistors on the link outputs.
The link inputs also need pull down resistors in case a link is not connected. On the transputers used on the
B003, the link inputs are more sensitive to electrostatic discharge (ESD) than the link outputs, and so the link inputs which connect to the edge connector are protected by schottky diodes; with the diodes the transputer can withstand 'zap' tests of up to 2 kV without damage.
Error
The error output produced by the transputer is active high, which is suitable when there is one transputer on a board but causes extra wiring and logic if there are many transputers on a board. To simplify the wiring, a notErrorWiredOR signal is generated by a resistor and transistor.
Decoupling
The power supply decoupling for the RAM and for the TTL is so close to the transputer that it provides excellent decoupling for the transputer. In addition to the power supply decoupling a further capacitor is needed between CapPlus and CapMinus to decouple an internal power supply used by the phase locked loop/clock multiplier. This capaCitor was originally a 10 Jl.F tantalum capacitor, but has been changed to 1 Jl.F ceramic for future production.
Printed circuit layout
The printed circuit is a straightforward 4 layer board with power and ground planes for the inner layers, and all signal traces on the outer layers. The design rules are an easily manufacturable 0.010" trace, with 0.008"
between traces. Component pads are 0.070", with 1 mm holes; vias are 0.050" pads with 0.6 mm holes.
Only one trace is allowed between pads.
The two outer layers are shown in figure 4.3.
(a) Component side
•••••••••••••••••••• ••• ••••••••••••• ..
-•
Figure 4.3 PCB layout: (a) Component side (b) Solder side
(b) Solder side
PGAs have been somewhat notorious for the difficulty they present to PCB layout. At first sight this layout appeared difficult, but careful component placement and orientation resulted in surprisingly simple layout, and there is still transparency for a number of additional connections.
Aspects of the placement which helped were:
• moving the link and control connections so they do not interfere with the memory connections;
• placing ICs lengthwise to the transputer. This allows maximum transparency, without pads getting in the way;
• moving the 373 to beyond the address multiplexors, which also had the effect of putting Byte 1 of the RAMs beyond Byte O.
Overall signal flow is shown in figure 4.4:
Link
MemAD bu.
~~ ~--~--~~
Multiplexed
addre ••
Byte1
By teO
Byte2
Byte3
Figure 4.4 Signal flow on IMS B003 PCB
Ltnk1 LlnkO
Analyse Reset Analyse Reset
TRANSPUTER 0 Ltnk.2I-t-.... HLlnk3 TRANSPUTER 1 Ciockln Llnk3notErro Clockln LlnkfotError
AnalyseLlnk2 Reset Analyse Llnk3 Reset TRANSPUTER 3 Llnk31-+-+--HLlnk2 TRANSPUTER 2 Clockln not Error Clockln not Error
LlnkO Llnk1
12 DownNotRaset Ink1
VCC
... +-_____
. . . J . . . -LlnkOSpe.d... +-___
...J..._ Llnk123Spaad ... ---~--SpaclalSpaad Error LED6 UpNolError
Figure 4.5 Logic shared by the four transputers on IMS B003
4.1.2 Logic used by all the transputers
The logic shared by all the transputers is shown in figure 4.5.
Reset etc
The evaluation boards share a common system control architecture. The aim of the system control functions is that it should be possible to control an arbitrarily large system built with the boards. The control implies the ability to reset the system, to note that an error has occurred in the system, and to analyse the error. Signals are provided for this purpose in the Up and Down sockets on the edge connector.
Up and Down sockets of evaluation boards are connected in a daisy chain as shown. The board at the top of the chain is controlled by a Subsystem socket on another evalulation board. The Subsystem socket has the same signals as the Up and Down sockets, but the Subsystem signals can be controlled by software running on the board with the Subsystem socket.
The Reset and Analyse signals flow in the direction of the arrows, the Error signal flows in the reverse direction from Down to Up, and indicates that an error has occurred on this board or on a board further down from this board.
All the 8003's transputers are reset on power ON. A single Error LED (yellow) lights if an error has occurred on this board.
Coding switch
The coding switch sets the Link speed signals for all the transputers. Separate controls are provided for Links
o
and Links 123, which are independently set to 10 Mbits/s or 20 Mbits/sec.Clock
The board uses a Single 5 MHz clock OSCillator, which is shared by all the transputers.
5 Using transputers from EPROM 5.1 Introduction
The INMOS Transputer has a unique ability to start from cold without any EPROM or similar non-volatile storage. It is able to load its first program from its serial links. This allows large networks of transputers to be constructed without the need for an EPROM on each, or its associated glue logic.
Where networks of transputers are being used for compute intensive tasks, many users have developed systems that are hosted by an I/O processor that sends the first program to the transputer. This allows the myriad of transputer based accelerator boards on the market to use cheap high volume keyboard, screen and disc in the form of a PC or a workstation.
Few systems of this type require an EPROM. However there are two other areas where EPROMs are needed;
the embedded system where there is no I/O processor or disc, and the workstation that is transputer based, i.e. has no other processor.
5.2 Requirements
The EPROM is required to boot the processor to which it is attached, and any other processors attached to that one by the links .... thus only one set of EPROMs for the entire network.
For the 'other' processors, no problem, as they are simply booting from link, as they were when attached to a development system. For the first processor, however, there are three possible requirements.
i) Transputers have a few kilobytes (2K on T212,T414, 4K on T425,T800 ... ) of internal RAM that is extremely fast (50ns,40ns). Thus it can be beneficial to use this rather than slow external EPROM for execution. The normal run from EPROM case would use this fast RAM as its dataspace.
ii) Transputer memory interfaces support RAM down to 1 OOns cycle time, (T801-25 80ns), which is faster than EPROM. EPROMs are widely available only down to 150ns access time, which means at least 200ns cycle time on a conventional bus. Thus, even if the program does not fit in the extremely fast internal memory, it can be beneficial to load it into external RAM where 1 OOns cycle time can be achieved.
iii) Especially on 16 bit machines, it may be desirable to run the code from EPROM, either to save providing RAM or to save space in the address map, but some critical piece or pieces of code may need to execute from internal RAM to achieve the necessary performance. When it is a single piece of code, this must be downloaded from EPROM to RAM at start-up. When it is multiple pieces of code, a paging system may need to be implemented.
Another implementation possibility is to use EPROMs that are not in the transputer address space at all, but are controlled by a counter and some logic to drive a link adapter. At reset, the contents of the EPROM are sent down the link to the transputer or transputer network, which itself is set to boot from link. The target system then behaves exactly as if it were loaded from the development system. One may still need to use method three above if it were critical to execute a part of the code from internal RAM, when the dataspace required was more than the size of that RAM.
5.3 Methodology ... D700D TDS based
The INMOS Transputer Development System (TDS) (IMS D700D) provides support for the first two require-ments outlined above, and these are described briefly below. The purpose of this note, however, is to demonstrate the two variants of requirement (iii).
5.3.1 Running from EPROM
To create an EPROM from the TDS, one simply takes a CODE SC fold and places it in a previously empty fold bundle. An additional fold that specifies the memory interface timing requirements may also be included for T414,T800,T425 processors which have an on chip DRAM controller. This fold is created by another
development system utility. One then gets the EPROM HEX tool from the toolset fold, puts the cursor on
opti.ona~ memory i.nterface data output created by EPROM HEX program
} } }
This creates an additional member of the fold bundle, which is the EPROM HEX file, which simply contains the start address, the processor type, and the code in ascii hex.
Finally one runs the HEXTOPROGRAMMER utility on the hex fold, to drive an EPROM programmer, or an equivalent program to create a disc image for later use by a programmer.
The code sent out actually has been extended slightly to include a preamble whose task it is to initialise those parts of the transputer not initialised by reset. Only the absolute minimum is reset in hardware, so that source of such a loader in directory \tds2\tools\eprom, in a fold marked 'multi-board EPROM loader', or the user can provide their own.
... F (confi.gurati.on) opti.onal memory ti.mi.ng } } }
supports the
endprocess
should the user program complete.5.3.3 Running from EPROM, with critical code in RAM (statically)
When it is necessary to run certain time critical sections of code from internal RAM, leaving the rest of the program running from EPROM, the task becomes far more complex.
Using the INMOS
occam
compilers, there is a predefined procedurekernel.. run
that allows code previ-ously loaded into a data array to be executed. There are also other various predefines to allow the parameters to be loaded for that code.Thus the call of
signal.. process (x,y,z)
where the formal parameter associated with
x
is a VAL:INT,
with Y is []BYTE,
withz
is [10]BYTE,
becomes:VAL