TYPE TYPICAL f MAX
74ALS164 60 MHz
ORDERING INFORMATION
TYPICAL SUPPLY CURRENT (TOTAL)
3.5 mA
COMMERCIAL RANGE PACKAGES
Vee
=
5V±10%;TA=
O°Cto +70°C14-Pin Plastic DIP 74ALS164N
14-Pin Plastic SO 74ALS164D
INPUT AND OUTPUT LOADING AND FAN-OUT TABLE
74ALS(U.L.) LOADVALUE
PINS DESCRIPTION HIGH/LOW HIGH/LOW
Dsa' Dsb Data inputs 1.0/1.0 201JAl0. 1 mA
CP Clock Pulse input (active rising edge) 1.0/1.0 201JAl0. 1 rnA MR Master Reset input (active-Low) 1.0/1.0 20fJA/0. 1 rnA
°0-07 Outputs 20/80 O.4rnA/SrnA
Signetics ALS Products Preliminary Specification
Shift Register 74ALS164
LOGIC DIAGRAM
MR----~~--~_;---4--+_--~_+--~--~--~_r--~--r_--~~--~
Vee -Pin 14 GND_ Pln7
FUNCTION TABLE
INPUTS OUTPUTS
OPERATING MODE MR CP D ••
0 ...
00 01 •••• °7L X X X L L L Reset (clear)
H
t
I I LCIa
qaH
t
I h LCIa
q6 ShiftH
t
h I LCIa
~H
t
h h HCIa
~H • High voltage level
h = HIgh voltage level one set-up tIme prior to the Low-te-Hlgh clock transition L Low voltage level
I
=
Low voltage level one set-up bme prior to the Low-to-High clock transitionqn = Lower case letters indIcate the state of the referenced input (or output) on setup time prior to the Low-to-High clock transibon
X Don1care
t _
Low-to-Hlgh clock transItionAPPLICATION
NOTES:
CLEAR CLOCK
DATA ENABLE
cp MR
D ..
Dab
The 'ALSI64 can be cascaded to form synchronous shift regl"e .. of any length.
Here. two devices are corri:lined to form a 16-bft shift register.
August 16, 1988
H
5-83
10
D ..
Dab
11
as
12
Signetics ALS Products Preliminary Specification
Shift Register 74ALS164
ABSOLUTE MAXIMUM RATINGS (Operation beyond the limits set forth in this table may impair the useful life of the device.
Unless otherwise noted these limits are over the operating free-air temperature range.)
SYMBOL PARAMETER RATING UNIT
Vce Supply voltage -0.5 to +7.0 V
VIN Input voltage -0.5 to +7.0 V
liN Input current -30 to +5 mA
VOUT Voltage applied to output in High output state -0.5 to +Vee V
lOUT Current applied to output in Low output state 16 mA
TA Operating free-air temperature range
o
to +70 ·CTSTG Storage temperature -65 to +150 ·C
RECOMMENDED OPERATING CONDITIONS
UMITS
SYMBOL PARAMETER UNIT
Min Nom Max
Vee Supply voltage 4.5 5.0 5.5 V
VIH High-level input voltage 2.0 V
VIL LOW-level input voltage 0.8 V
11K Input clamp current -18 mA
IOH High-level output current -0.4 mA
IOL Low-level output current 8 mA
TA Operating free-air temperature range 0 70 ·C
DC ELECTRICAL CHARACTERISTICS (Over recommended operating free-air temperature range unless otherwise noted.) TEST CONDITIONS 1
UMITS
SYMBOL PARAMETER
Typ2 UNIT
Min Max
Vee±10%, VIL = MAX, VIH = MIN, IOH = MAX Vee-2 V VOH High-level output voltage
Vee = MIN, VIL =
MAX I
IOL =4mA 0.25 0.4 VVOL LOW-level output voltage
VIH = MIN
I
IOL =8mA 0.35 0.5 VVIK Input clamp voltage Vee = MIN, II = 11K -1.5 V
II Input current at maximum
Vee = MAX, VI = 7.0V 100
!1A
input voltage
IIH High-level input current Vee = MAX, VI = 2.7V 20
!1A
IlL Low-level input current Vee = MAX, VI = 0.4V -0.1 mA
I 3
0 Output current Vee = MAX, Vo = 2.25V -30 -112 mA
lee Supply current (total) Vee = MAX 10 mA
NOTES:
1. For condmons shown as MIN or MAX, use the appropriate value specllied under recommended operating conditions for the applicable type.
2. All typical values are at Vee = 5V, TA
=
25'<:.3. The output conditions have been chosen to produce a current that closely approximates one half 01 the true short-cirUit output current,los'
August 16, 1988 5-84
Signetics AlS Products
Shift Register
AC ELECTRICAL CHARACTERISTICS
SYMBOL PARAMETER TEST CONDITION
fMAX Maximum Clock frequency Waveform 1
tpLH tpHL
Propagation delay
CP to On Waveform 1
tpHL Propagation delay MR to On Waveform 2
AC SETUP REQUIREMENTS
SYMBOL PARAMETER TEST CONDITION
ts(H) Set-up time Waveform 3 Waveform 1. Propagation Delay, Clock Input To Output,
Clock Pulse Width, and Maximum Clock Frequency
On
Waveform 2. Master Reset Pulse Width, Master Reset to Output Delay and Master Reset to Clock Recovery Time
Waveform 3. Data Setup And Hold Times NOTE: For all waveforms. V M - 1.3V.
The shaded areas indicate when the input is permitted to change for predictable output performance.
August 16, 1988 5-85
Signetics ALS Products
Shift Register
TEST CIRCUIT AND WAVEFORMS
Vee
Test Circuit for Totem-Pole Outputs DEFINITIONS
RL = Load resistor; see AC CHARACTERISTICS for value.
CL = Load capacitance includes jig and probe capacitance;
see AC CHARACTERISTICS for value.
RT = Termination resistance should be equal to ZOUT of pulse generators.
August 16, 1988
FAMILY
74ALS
5-86
Preliminary Specification
74ALS164
INPUT PULSE REQUIREMENTS Ampl~ude Rep. Rate tw tTLH tTHL
3.SV 1MHz 500ns 2.0ns 2.0ns
Signetics
ALS Products
FEATURES
• Six edge-triggered D-type flip-flops
• Buffered common Clock
• Buffered, asynchronous Master Reset
DESCRIPTION
The 74ALS174 has six edge-triggered D-type flip-flops with individual D inputs and Q outputs. The common buffered Clock
TYPICAL SUPPLY CURRENT (TOTAL)
and reset (clear) all flip-flops simultane-
INPUT AND OUTPUT LOADING AND FAN-OUT TABLE
ously.The register is fully edge-triggered. The state of each D input, one setup time before the Low-to-High clock transition is trans-ferred to the corresponding flip-flop's Q output.
All Q outputs will be forced Low independ-ent of Clockor Data inputs by a Low voltage level on the MR input. The device is useful for applications where true outputs only are required, and the Clock and Master Reset are common to all storage elements.
PIN CONFIGURATION
MR Vee
74ALS(U.L.) LOADVALUE
PINS DESCRIPTION HIGH/LOW HIGH/LOW
Do - Ds Data inputs 1.0/1.0 20flA/0.1mA
CP Clock Pulse input (active rising edge) 1.0/1.0 20A/0.1mA
MR
Master Reset input(active-Low) 1.0/1.0 20flA/0.1mA00-05 Outputs 20/80 0.4mAl8mA
NOTE:
One (1.0) ALS Unit Load IS defined as: 20JlA in the High state and 0.1 rnA In the Low state.
LOGIC SYMBOL LOGIC SYMBOL(IEEEIIEC)
3 4 6 11 13 14