logic diagram (positive logic)
typical clear, shift, and clear sequences
CL"R--U
I~
I
SERIAL { A INPUTS
B ----i-, - - - I
I
~--..--..---..+---..----OUTPUTS CLK
I I I
---,
IQA __ ~I _ _ _ _ _ _ _ _ _ _ _ --I
---,
QB ___ ~I _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ~
~--..---~---
~---~---,
QC ___ ~I _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ~
~~---~---,
QO ~I ________________________ ~
QE ·---~l
_________________________
....J~~---L.Sl'---_____ ___
I
---,
IQF ___ ~I _____________________________ - - - I
I
---,
QG ___ ~I _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ -....J
---, n'
IQH __ ~, ________________________________________ ~ ~ ___________ _
I
CLEAR CLEAR
maximum ratings, recommended operating conditions, and electrical characteristics See Table IV, page 2-10.
3-128
TEXAS ~
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265
TYPES SN54HC164, SN74HC164 8-BIT PARALLEL-OUT SERIAL SHIFT REGISTERS
timing requirements over recommended operating free-air temperature range (unless otherwise noted) TA = 25°C SN54HC164 SN74HC164
UNIT
VCC MIN MAX MIN MAX MIN MAX
2V 0 6 0 4.2 0 5
fclock Clock frequency 4.5 V 0 31 0 21 0 25 MHz
6V 0 36 0 25 0 28
2V 100 150 125
ClR low 4.5 V 20 30 25
6V 17 25 21
tw Pulse duration
100 ns
2V 80 120
ClK high or low 4.5 V 16 24 20
6V 14 20 18
2V 100 150 125
Data 4.5 V 20 30 25
Setup time 6V 27 25 21
tsu before ClKt 2V 100 150 125 ns
ClR inactive 4.5 V 20 30 25
6V 27 25 21
2V 5 5 5
th Hold time. data after ClK t 4.6 V 5 5 5 ns
6V 5 5 5
switching characteristics over recommended operating free-air temperature range (unless otherwise noted), CL - 50 pF (see Note 1)
PARAMETER FROM TO TA = 25°C SN54HC164 SN74HC164
UNIT (INPUT) (OUTPUT) VCC
MIN TYP MAX MIN MAX MIN MAX
2V 6 10 4.2 5
fmax 4.5 V 31 54 21 25 MHz
6V 36 62 25 28
2V 140 205 295 255
tpHl ClR Any Q 4.5 V 28 41 59 51 ns
6V 24 35 51 46
2V 115 175 265 220
tpd ClK Any Q 4.5 V 23 35 53 44 ns
6V 20 30 45 38
2V 38 75 110 95
tt 4.5 V 8 15 22 19 ns
6V 6 13 19 16
Power dissipation capacitance No load. TA = 25°C 135 pF typ NOTE 1: For load circuit and voltage waveforms. see page 1-14.
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TEXAS •
INSTRUMENTS
3-129POST OFFICE BOX 225012 • OALLAS. TEXAS 75265
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3-130
HIGH·SPEED CMOS LOGIC
• Complementary Outputs,
• Direct Overriding Load (Data) Inputs
• Gated Clock Inputs
• Parallel·to-Serial Data Conversion
• Package Options Include Both Plastic and Ceramic Chip Carriers in Addition to Plastic and Ceramic DIPs
• Dependable Texas Instruments Quality and Reliability
description
The 'HC165 is an 8-bit serial shift register that, when clocked, shifts the data toward serial output QH. Parallel-in access to each stage is provided by eight individual direct data inputs that are enabled by a low level at the SH/lD input. The 'HC165 also features a clock inhibit function and a complementary serial output QH.
Clocking is accomplished by a low-to-high transition of the ClK input while SH/lD is held high and ClK INH is held low. The functions of the ClK and ClK INH (clock inhibit) inputs are independently of the levels of ClK, ClK INH, or SER inputs.
The SN54HC165 is characterized for operation over the full military temperature range of -55 DC'to 125 DC. The SN74HC165 is characterized for operation -from - 40 DC to 85DC.
FUNCTION TABLE INPUTS
Shift - content of each internal register shifts toward serial output QH. Data at serial input is shifted into first register.
TYPES SN54HC165. SN74HC165 PARALLEL·LOAD 8·BIT SHIFT REGISTERS
02684. DECEMBER 1982-REVISED MARCH 1984 SN54HC165 •.• J PACKAGE
NC-No internal connection logic symbol
Copyright ©1982 by Texas Instruments Incorporated
II en
INSTRUMENTS
3-131POST OFFICE BOX 225012 • DALLAS. TEXAS 75265
TYPES SN54HC165, SN74HC165 PARALLEL·LOAD 8·BIT SHIFT REGISTERS
logic diagram (positive logic)
_ _ Pin numbers shown are for J and N packages.
_ _ typical shift, load, and inhibit sequences
::J:
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C m
!S
(")m
rJ)CLK
CLKINH
SER L
S H / L D - U
I I
A----flIHl~
____
~________________________________ ___
DATA
B I L I C
--f:Hl
D I L . -I
E~~----~---F I L
G~~----~--- I
IH---lfHl~ ____
.~I---~---__ ~---
QH H H
CH
-~---~I---~ L L
j4-INHIBIT -. ~~II4
.. ---
SERIAL SHIFT - - - -••LOAD
TEXAS -I/}
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265
TYPES SN54HC165, SN74HC165 PARALLEL·LOAD 8·BIT SHIFT REGISTERS
timing requirements over recommended operating free-air temperature range (unless otherwise noted)
VCC TA = 25°C SN54HC165 SN74HC165
UNIT
MIN MAX MIN MAX MIN MAX
2V 0 6 0 4.2 0 5
fclock Clock frequency 4.5 V 0 31 0 21 0 25 MHz
6V 0 36 0 25 0 29
2V 80 120 100
SH/iJ5 low 4.5 V 16 24 20 ns
Pulse duration 6V 14 20 17
tw 2V 80 120 100
ClK high or low 4.5 V 16 24 20 ns
6V 14 20 17
2V 80 120 100
SH/iJ5 high before ClK t 4.5 V 16 24 20 ns
6V 14 20 17
2V 40 60 50
SER before ClK t 4.5 V 8 12 10 ns
6V 7 10 9
tsu Setup time
ClK INH low 2V 100 150 125
before ClKt 4.5 V 20 30 25 ns
6V 17 25 21
ClK INH high 2V 40 60 50
before ClK~ 4.5 V 8 12 10 ns
6V 7 10 9
2V 100 150 125
Data before SH/iJ5 t 4.5 V 20 30 25 ns
6V 17 26 21
2V 5 5 5
SER data after ClK t 4.5 V 5 5 5 ns
Hold time 6V 5 5 5
th 2V 5 5 5
PAR data after SH/LD t 4.5 V 5 5 5 ns
6V 5 5 5
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TEXAS ~
INSTRUMENTS
3-133POST OFFICE BOX 225012 • DALLAS, TEXAS 75265
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TYPES SN54HC165, SN74HC165 PARALLEL·LOAD 8·BIT SHIFT REGISTERS
switching characteristics over recommended operating free-air temperature range (unless otherwise noted), CL
=
50 pF (see Note 1)PARAMETER FROM TO TA = 25°C SN54HC165 SN74HC165
(INPUT) (OUTPUT) vCC
MIN TYP MAX MIN MAX MIN MAX UNIT
2V 6 13 4.2 5
fmax
-
4.5 V 31 50 21 25 MHz6V 36 62 25 29
2V 80 150 225 190
tpd SH/ID QH or GH 4.5 V 20 30 45 38 ns
6V 16 26 38 32
2V 75 150 225 190
tpd ClK QH or GH 4.5 V 15 30 45 38 ns
6V 13 26 38 32
2V 75 150 225 190
tpd H QH or GH 4.5 V 15 30 45 ., 38 ns
6V 13 26 38 32
2V 38 75 110 95
tt Any 4.5 V 8 15 22 19 ns
6V 6 3 19 16
Power dissipation capacitance No load. TA - 25°C 75 pF typ NOTE 1: For load circuit and voltage waveforms. see page 1-14.
3-134
TEXAS ~
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265
HIGH·SPEED
• Dependable Texas Instruments Quality and Reliability
description
The 'HC166 parallel-in or serial-in, serial-out registers feature gated clock inputs and an overriding clear input. The parallel-in or serial-in modes are established by the shift/load input.
When high, this input enables the serial data input and couples the eight flip-flops for serial shifting with each clock pulse. When low, the parallel (broadside) data inputs are enabled and synchronous loading occurs on the next clock pulse. During parallel loading, serial data flow is inhibited. Clocking is accomplished on the low-to-high-Ievel edge of the clock pulse through a two-input positive NOR gate permitting one input to be used as a clock-enable or clock-inhibit function. Holding either of the clock inputs high inhibits clocking; holding either low enables the other clock input. This, of course, allows the system clock to be free-running and the register can be stopped on command with the other clock input. The clock-inhibit input should be changed to the high level only when the clock input is high. A direct clear input overrides all other inputs, including the clock, and resets all flip-flops to zero.
The SN54HC166 is characterized for operation over the full· military temperature range of -55°C to 125°C. The SN74HC166 is characterized for operation from - 40°C to 85°C.
FUNCTION TABLE
INPUTS INTERNAL
CLOCK
SHIFT/ PARALLEL OUTPUTS
CLEAR CLOCK SERIAL
TYPES SN54HC166. SN74HC166 PARALLEL·LOAD H·BIT SHIFT REGISTERS
02684, DECEMBER 1982-REVISED MARCH 1984 SN54HC166 ... J PACKAGE
NC-No internal connection
logic symbol
Copyright ©1982 by Texas Instruments Incorporated
II
INSTRUMENTS
3-135POST OFFICE BOX 225012 • DALLAS, TEXAS 75265