change the format in the 12C-bus specification. Using 10 bits for addressing exploits the reserved combination 1111 XXX for the first 7 bits of the first byte following a START (S) or repeated START (Sr) condition as explained in Section 8.1. The 10-bit addressing does not affect the existing 7-bit addressing. Devices with 7-bit and 10-bit addresses can be connected to the same 12C-bus, and both 7-bit and 10-bit addressing can be used in a standard-mode system (up to 100 kbitls) or a fast-mode system (up to 400 kbitls) system.
Although there are eight possible combinations of the reserved address bits 1111 XXX, only the four combinations 11110XX are used for 10-bit addressing. The remaining four combinations 11111 XX are reserved for future 12C-bus enhancements.
Signetics 8OC51-Based 8-Bit Microcontrollers
12C-bus specification (including fast-mode)
12.1 Definition of bits in the first two bytes
The 10-bit slave address is formed from the first two bytes following a START condition (S) or a repeated START condition (Sr).
The first 7 bits of the first byte are the combination 11110XX of which the last two bits (XX) are the two most-significant bits (MSBs) of the 1 D-bit address; the eighth bit of the first byte is the RiWbit that determines the direction of the message. A 'zero' in the least significant position of the first byte means that the master will write information to a selected slave. A 'one' in this position means that the master will read information from the slave.
If RlW is 'zero', then the second byte contains the remaining 8 bits (XXXX~XX) of the 10-bit address. If RlW is 'one', then the next byte contains data transmitted from slave to master.
12.2 Formats with 10-bit addresses
Various combinations of read/write formats are possible within a transfer that includes 10-bit addressing. Possible data transfer formats are:
- Master-transmitter transmits to slave-receiver with a 10-bit slave address. The transfer direction is not changed (Fig.27). When a 10-bit address follows a START condition, each slave compares the first 7 bits of the first byte of the slave address (11110XX) with its own address and tests if the eighth bit (RlW direction bit) is O. It is possible that more than one device will find a match and generate an acknowledge (Al). All slaves that found a match will compare the 8 bits of the second byte of the slave address (XXXXXXXX) with their January 1992
Fig.27 A master-transmitter addresses a slave-receiver with a 10-bit address
Fig.28 A master-receiver addresses a slave-transmitter with a 1 a-bit address
t t t to X X 0
~~ =~~ .IDAT'~ ]D'T'~
fJM:f) ... "
Fig.29 Combined format. A master addresses a slave with a 1 a-bit address, then transmits data to this slave and reads data from this slave own addresses, but only one
slave will find a match and generate an acknowledge (A2).
The matching slave will remain addressed by the master until it receives a STOP condition (P)
or
a repeated START condition (Sr) followed by a different slave address.148
- Master-receiver reads slave-transmitter with a 10-bit siave address. The transfer direction is changed after the second RlW bit (Fig.28). Up to and including acknowledge bit A2, the procedure is the same as that described above for a master-transmitter
Signetics 8OCS1-Based B-Bit Microcontrollers
12C-bus specification (including fast-mode)
1 1 1 lOX X 0
~tt~ ~\'r~E~ - !fk;'! =~ - [;:%1-' ]~~.~j
(MI»I
Fig.30 Combined format. A master transmits data to two slaves, both with la-bit addresses
Fig.31 Combined format. A master transmits data to two slaves, one with a 7-bit address, and one with a 10-bit address
addressing a slave-receiver.
After the repeated START condition (Sr), a matching slave remembers that it was addressed before. This slave then checks if the first 7 bits of the first byte of the slave address following Sr are the same as before after the generates acknowledge A3.
The slave-transmitter remains addressed until it receives a STOP condition (P) or until it receives another repeated START condition (Sr) followed by a different slave address. 11110XX slave address (for 7-bit devices) does not matCh) - Combined format. A master
transmits data to a slave and then reads data from the same slave (Fig.29). The same master occupies the bus all the time. The transfer direction is...£hanged after the second R/W bit
- Combined format. A master transmits data to one slave and then transmits data to another slave (Fig.30). The
149
master occupies the bus all the time
- Combined format. 10-bit and 7-bit addressing combined in one serial transfer (Fig.3l).
After each START condition (S), or each repeated START condition (Sr), a la-bit or 7-bit slave address can be transmitted. Figure 30 shows how a master-transmits data to a slave with a 7 -bit address and then transmits data to a slave with a 10-bit address.
The same master occupies the bus all the time. decrement of previously accessed memory locations etc. are taken by
\he designer of \he device.
3) Each byte is followed by an acknowledgement bit as indicated by \he A or
A
blocks in the The 10-bit addressing procedure for the 12C-bus is such that the first two bytes after the START condition (S) usually determine which slave will be selected by the master. The exception is the 'general call' address 00000000 (H'OO'). Slave devices with 10-bit addressing will react to a 'general call' in the same way as slave devices with 7 -bit addressing (see Section B.l.l).Hardware masters can transmit their 10-bit address after a
Signetics 80C51-Based 8-Bit Microcontrollers
12C-bus specification (including fast-mode)
'general call'. In this case, the 'general call' address byte is followed by two successive bytes containing the 10-bit address of the master-transmitter. The format is as shown in Fig. 15 where the first DATA byte contains the eight least-significant bits of the master address.
The START byte 00000001 (H'Ol') can precede the 10-bit addressing in the same way as for 7-bit addressing (see Section 8.1.2).
14.0 APPLICATION INFORMATION FOR FAST-MODE 1
2C-BUS DEVICES
14.1 Output stage with slope control
The electrical specifications for the II0s of 12C-bus devices and the characteristics of the bus lines connected to them are given in
14.2 Switched pull-up circuit The supply voltage (V DO) and the capacitance than this, a switched pull-up circuit as shown in Fig.34 additional control signals. During
the rising/falling edges, the bilateral switch in the HCT 4066 switches pull-up resistor Rp2 on/off at bus levels between 0.8 V and minimize crosstalk and undershoot of the bus line signals. The maximum value of Rs is determined by the maximum permitted voltage drop across this resistor when the bus line is
12C-bus specification (including fast-mode)
January 1992
Fig.32 S/ope-controlled output stage in CMOS technology
r-;::=====~£.;--VDD
Fig.33 S/ope-controlled output stage in bipolar technology
nE
Sv±,O% voo
~~ _ _ _ ~ _ _ ~~ ___ ~~_SO~~~L Rp'
Cb 400pF
max.
FAST - MODE 12C BUS DEVICES Fig.34 Switched pull-up circuit
maxlirum valueRp
7.5
(kn) 6.0
'.5
3.0
1.5
o
\\
\\
'\ vRs·o
~ I-""",.RS ~I:,..
@VOO·5V
-=::::: F=
1=o 100
I
200 300 400 bus capadlance (pF)Fig.35 Maximum value of Rp as a function of bus capacitance for meeting the tR max. requirement for a fast-mode 12C-bus
These wiring pattems also result in identical capacitive loads for the SDA and SCL lines. The Vss and Voo lines can be omitted if a PCB with a Vss and/or Voo layer is used.
If the bus lines are twisted-pairs, each bus line must be twisted with a Vss retum.
Altematively, the SCL line can be twisted with a Vss retum, and the SDA line twisted with a Voo retum. In the latter case, capacitors must be used to decouple the Voo line to the Vss line at both ends of the twisted pairs.
If the bus lines are shielded (shield connected to V ss)' interference will be minimized. The shielded cable must have low capacitive coupling between the SDA and SCL lines to minimize crosstalk.
14.4 Maximum and minimum values of resistors Rp and Rs The maximum and minimum values for resistors Rp and Rs connected to a fast-mode 12C-bus can be determined from Fig.23, 24 and 26 in Section 9.1. Because a fast-mode
1
2C-bus has faster rise times (tR) the maximum value of Rp as a function of bus capacitance is less than that shown in Fig.25 The replacement graph for Fig.25 showing the maximum value of Rp as a function of bus capacitance (Cb) for a fast mode 12C-bus is given in Fig.35.Signetics 80C51-Based 8-Bit Microcontrollers
12C-bus specification (including fast-mode)
15.0 ELECTRICAL SPECIFICATIONS AND TIMING FOR 110 STAGES AND BUS LINES
The 1/0 levels, 1/0 current, spike suppression, output slope control and pin capacitance for 12C-bus standard-mode 12C-bus devices.
The minimum HIGH and LOW mode devices. Standard-mode and fast-mode 12C-bus devices
Table 3 Characteristics of the SDA and SCL VO stages for 12C-bus devices standard-mode devices
Parameter Symbol
Min. Max.
LOW level input voltage: VIL
fixed input levels -0.5 1.5
V Do-related input levels -0.5 0.3Voo
HIGH level input voltage: VIH
fixed input levels 3.0 .1)
V oo-related input levels O·7VOO .1)
Hysteresis of Schmitt trigger inputs: Vhys
fixed input levels nla nla
V Do-related input levels nla nla
Pulse width of spikes which must be tS? nla nla
suppressed by the input filter LOW level output voltage (open drain or open collector): voltage between 0.4 V and 0.9Voo max.
Capacitance for each 1/0 pin Ci
-
10 applying the clock synchronization procedure described in Section 6 quoted in Table 4 (300 ns) is longer than the specified maximumIoF
for the output stages (250 ns).This allows series protection resistors (R.)to be connected between the SDAlSCL pins and the SDAlSCL bus lines as shown in Fig.34 without exceeding the maximum specified ~.
3) 1/0 pins of fast-mode devices must not obstruct the SDA and SCL lines if Voo is switched off.
12C-bus specification (including fast-mode)
Table 4 Characteristics of the SDA and SCL bus lines for 12C-bus devices
Standard-mode Fast-mode
Parameter Symbol 12C-bus 12C-bus Unit
Min. Max. Min. Max.
SCL clock frequency fSCL 0 100 0 400 kHz
Bus free time between a STOP and START condition 1aUF 4.7
-
1.3-
IlsHold time (repeated) START condition. After this period, 4iD;STA 4_0 0.6 Ils the first clock pulse is generated
LOW period of the SCL clock ~ow 4.7 1.3
-
IlsHIGH period of the SCL clock 4iIGH 4.0
-
0.6-
IlSSet-up time for a repeated START condition lsU;STA 4.7
-
0.6 IlSData hold time: 4iD;DAT
for CBUS compatible masters (see NOTE, Section B.l.3) 5.0
- - -
Ilsfor 12C-bus devices 0') 0') 0.92) IlS
Data set-up time tSU;DAT 250 1003)
-
nsRise time of both SDA and SCL signals ~
-
1000 20+ 300 ns0.ICb4) Fall time of both SDA and SCL signals
'" -
300 0.IC20+ b4) 300 nsSet-up time for STOP condition Isu;STO 4.0
-
0.6 IlSCapacitive load for each bus line Cb
-
400 400 pFAll values referred to V1H min. and V1L max. levels (see Table 3).
') A device must internally provide a hold time of at least 300 ns for the SDA signal (referred to the V1H min of the SCL signal) in order to bridge the undefined region of the falling edge of SCL.
2)The maximum 4iD;DAT has only to be met if the device does not stretch the LOW period (~ow) of the SCL signal.
3) A fast-mode 12C-bus device can be used in a standard-mode 12C-bus system, but the requirement tSU;DAT ;,250 ns must then be met. This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must ou1put the next data bit to the SDA line ~ max. + tSU;DAT ~ 1000 + 250 ~ 1250 ns (according to the standard-mode 12C-bus specification) before the SCL line is released.
4) Cb ~ total capacitance of one bus line in pF.
Fig.36 Definition of timing on the ,2C-bus
Signetics 8OCS1-Based 8-BII Mlcroconlrollers