Though Intel's EPLDs include many of the typical latch and register types, some logic designs require reg-ister or latch configurations not directly supported in the current EPLDs. In many cases these register and latch configurations can be generated using the logic array and combinational feedback. A "latch" is defined as a level-triggered, flow-through type such as the 74373, and a "register" is defined as an edge-triggered flip-flop such as the 7474.
This application brief will detail the construction of a D-type latch, an RS latch and a D flip-flop using com-binational logic and feedback. Also discussed is the construction of an RS flip-flop, a JK flip-flop and a T flip-flop using registered logic and feedback.
The RS latch is the simplest latch configuration. The equations for it are as follows: QB = !(Q
+
S), Q =!(QB
+
R) where Q is the output of one NOR gate, and QB is the output of the other (Note: as a conventionin this Ap brief, the "!" operator is used to signify in-version). The schematic of the RS latch is shown in Figure.la.
Since cross coupled logic is not supported in EPLDs, we must convert the equation to a single term with feedback.
aD, OF = COCF (a, VCC) Q = S
+
!R * OF;where QF is the feedback from Q output.
This circuit can be implemented in an EPLD macro-cell. Where combinational feedback is not supported, 1/0 feedback will suffice. The schematic of this imple-mentation is shown in Figure lb.
With the RS latch, the inputs are normally low. A logi-cal one on S sets Q to I, and a one on R resets Q to a O.
Logical ones on both inputs simultaneously cause the output to remain at a high level since S takes prece-dence over R in this implementation.
~
R 0
OB
5
NOR2
292031-1 (a)
Vce
INP
5
----.
INP COCF'
R
•
00292031-2
(b)
Figure 1. RS Latch Implementation In a) Discrete Gates and b) EPLD Logic
2-153
infef
AB-16Another latch is the 74373 type, or D latch. This latch works by either enabling input data to appear at the output, or by holding the output to the last input data state. Its equation is this: QB = !(!(!D*E)*Q), Q =
!(!(D*E)*QB). Again, Q is the output of one NAND gate, and QB is the output of the other. Figure 2a shows this version of the design.
Again, we must convert to an EPLD-type equation and schematic:
0-1-+--1
E-~--I NAN02
(a)
01- 0 - - - - 1 . E:-D'"-'
(b)
QD, QF = COCF (Q,VCC) Q = D • E
+
!E • QF;QF is the feedback from the COCF. In this circuit, when E is high, data flows through transparently.
When E is brought low, data is latched. When using input feedback, care must be taken when tri-stating the output as data will no longer be latched. The EPLD implementation is given in Figure 2b.
Q
292031.,.3
----.
COCFII ' T ' ~~~'-QO
292031-4
Figure 2. Implementation of a D Type Latch Using a) Discrete Gates and b) EPLD Logic
2-154
AB-16
This latch can be cascaded with a second latch to pro-duce an edge triggered, master/slave D flip-flop, using combinational logic. The flip-flop is a solution to using asynchronous clocking, preset and clear functions when they aren't supported. Also, if an I/O conflict exists within a macrocell group when using registered logic, this design will fit since it uses combinational logic.
Figure 3. shows the schematic for this design.
This design does consume two macro cells, but in many cases, that isn't a problem.
o-D---I
INPINP CLOCK
-C>--+--I
The boolean equation of the D flip-flop is this:
QD,QF = COCF (Q,VCC) YF = NOCF (Y)
Y = D • !CLOCK
+
YF • CLOCK;Q = YF • CLOCK + QF • !CLOCK;
Q is the flip-flop output and Y is the first latch output.
Data is latched in to the second latch on the low-going edge of clock, and is clocked out to Q on the high-going edge of clock.
YF
.
----. cocn
>-C>r'-oo
OF
292031-5 Figure 3. Combinational Logic implementation of a
o
Flip-Flop2-155
intJ AB·16
Preset and clear can be added into the equations as well:
QD,QF = COCF (Q,vcC) YF = NOCF (Y)
Y = D' !CLOCK
+
YF • CLOcK;Q = YF • CLOCK • I (CLEAR TERM)
+
(PRESET TERM)
+
QF • !CLOCK • ! (CLEAR TERM);
When the PRESET TERM is logically true,
Q
is asyn-chronously set to 1.INP
D
-0_---1.
CLOCK--{:>---~--_r. INP
INP
CLEAR TERM -C>-of ~>O""'-~I--IA INP
. PRESET TERM
--C>---....J
When the CLEAR TERM is logically true, Q is
asyn-chronously cleared to O. .
The PRESET TERM takes priority over the' CLEAR TERM.
This schematic is shown in Figure 4.
Due to the nature of the design, input delays plus array . delays plus feedback delays must be added and used to determine a maximum operating frequency. In this ex-ample, tIN
+
tAD+
tCF+
tAD = 113 ns for a-6S SC121, leaving a maximum frequency of 8.8 MHz.
vr .
----" cocr.
'~~~ ~~~'--QD
292031-6 Figure 4. 0 Flip-Flop with Added Preset and Clear Terms
2-156
intJ AB-16
Other useful workarounds involve D registers and logic in constructing RS, JK and T flip-flops, for use in EPLDs not supporting these configurations. The RS flip-flop is simply the RS latch discussed earlier cou-pled to registered feedback.
OD,OF = RORF (O,CLOCK,GND,GND,VCC) 0= S
+
OF· !R;Normally, Sand R will remain low. When S is brought high, QD will become 1 on the next clock trigger edge.
When R is brought high, QD will become 0 on the next clock trigger edge. The schematic is given in Figure 5.
INP
The JK flip-flop is another useful and easily implement-ed register:
OD,OF = RORF (O,CLOCK,GND,GND,VCC)
o
= J • !OF+
!K • OFWhen J = K = 1, QD toggles to opposite state on next clock trigger. When J = K = 0, QD remains the same.
When J does not equal K, QD 'will follow J on next clock trigger. The schematic is shown in Figure 6.
CLOCK--£:)---, GNO Vee
INP
s--~~---~
----.
INP R--lD-f
RORF'
>-C>r'--OO
292031-7
Figure 5. EPLD Implementation of an RS Flip-Flop
INP
CLOCK--£:)---, INP
----.
RORF'>-C>r'-oo
INP K--lD--I
292031-8
Figure 6. EPLD Implementation of a JK Flip-Flop
2-157
AB-16
The T flip~flop is also easily constructed:
OD,OF = RORF (O,CLOCK,GND,GND,VCC) Q = T • ! OF
+
! T • OF;When T is high, QD will toggle to opposite state on next trigger. When T is low, QD will remain the same.
Figure 7 shows the T flip-flop design schematic.
Each of these designs uses a minimum number of p-terms; adding p-terms is possible to the limit of the macrocell being used. It is possible to substitute an en-tire logical expression for each input listed (except
INP
CLOCK-C>----__.
INP
T-ID--\
register clock), as long as the minimized logic equations resulting do not exceed the macrocells p-term count ..
For example, consider using the J-K register. Setting J
=
A • B • C+
D and setting K=
E • !F • !G+
H
+
I then the minimized p-term count will expand from two p-terms to five p-terms, which would still be okay within a macrocell with more than five p-terms.Using logic gates and combinational or registered feed-back, one can easily implement many types of latches and registers. Regardless of the EPLD type, there exists the resources to implement any of the discussed circuit-ry.
GND Vce
----.
RORF'·>-C>r'-QD
292031-9
Figure 7. Implementation of a T Flip-Flop
2-158