Application Hints (Continued)

U)

C

Application Hints

(Continued)

BALANCED LINE DRIVER

II

INPUT VOLTAGE

TLlF/5801-14

Balanced RS-422 Fall-Safe

5Vo---~--~

INPUT VOLTAGE w CI

<

o ~

>

....

~ ....

=

o o

TLlF/5801-15

Truth Table

(For Balanced Fail-Safe)

Input Strobe A-OUT B-OUT C-OUT

0 1 0 1 0

1 1 1 0 1

X 1 0 0 X

0 0 1 1 0

1 0 1 1 0

X 0 1 1 0

1-162

D-OUT 0 0 1 0 0 0

TL/F/5801-13

CI w

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~ o

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....

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TL/F/5801-16

~

^NatiOnal

Semiconductor Corporation

DS78LS120/DS88LS120 Dual Differential Line Receiver (Noise Filtering and Fail-Safe)

General Description

The OS78LS120 and OS88LS120 are high performance, dual differential, TTL compatible line receivers for both bal-anced and unbalbal-anced digital data transmission. The inputs are compatible with EIA, Federal and MIL standards.

Input specifications meet or exceed those of the popular OS7820/0S8820 line receiver.

Features

The line receiver will discriminate a ± 200 mV input signal over a common-mode range of ± 10V and a ± 300 mV sig-nal over a range of ± 15V.

• Meets EIA standards RS232-C, RS422 and RS423, Federal Standards 1020, 1030 and MIL-188-114

• Input voltage range of

±

15V (differential or common-mode)

Circuit features include hysteresis and response control for applications where controlled rise and fall times and/or high frequency noise rejection are desirable. Threshold offset control is provided for fail-safe detection, should the input be open or short. Each receiver includes an optional 1800 terminating resistor and the output gate contains a logic strobe for time discrimination. The OS78LS120 is specified over a - 55°C to + 125°C temperature range and the OS88LS120 from O°C to +70·C.

• Separate strobe input for each receiver

• 5k typical input impedance

• Optional 1800 termination resistor

• 50 mV input hysteresis

• 200 mV input threshold

• Separate fail-safe mode

Connection Diagram

Dual-In-Llne Package

FAIL·SAFE TERMI· RESPONSE

Vee OFFSET -INPUT NATION +INPUT STROBE TIME OUTPUT

16 15 14 13 11

FAIL·SAFE -INPUT TERMI· +INPUT STROBE RESPONSE OUTPUT GNO

OFFSET NATION TIME

Top View

Order Number DS78LS120J, DS88LS120J or DS88LS120N See NS Package Number J16A or N16A

1-163

TLlF17499-1

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Absolute Maximum Ratings

(Note 1)

Operating Conditions

Specifications for Military I Aerospace products are not Min Max Units

contained In this datasheet. Refer to the associated Supply Voltage (Vce> 4.5 5.5 V reliability electrical test specifications document. Temperature (T A)

Supply Voltage 7V DS7BLS120 -55 +125 ·C

Input Voltage ±25V DSBBLS120 0 +70 ·C

Strobe Voltage 7V Common-Mode Voltage (VCM) -15 +15 V

Output Sink Current 50 rnA

Storage Temperature Range - 65·C to + 150·C Maximum Power Dissipation· at 25·C

Cavity Package 1433 mV

Molded Package 1362 mW

Lead Temperature (Soldering, 4 sec) 260·C 'Derate cavity package 9.6 mWrC above 2SoC; derate molded package 10.9 mW

rc

above 2SOC.

Electrical Characteristics

(Notes 2 and 3)

Symbol Parameter Conditions Min Typ Max Units

VTH Differential Threshold Voltage lOUT = -400 IJ-A, VOUT ~ 2.5V -7V ~ VCM ~ 7V 0.06 0.2 V -15 ~ VCM ~15V 0.06 0.3 V VTL Differential Threshold Voltage lOUT = 4 rnA, VOUT ~ 0.5V -7V ~ VCM ~7V -O.OB -0.2 V -15V ~ VCM ~ 15V -O.OB -0.3 V VTH Differential Threshold Voltage lOUT = -400 IJ-A, VOUT:<! 2.5V -7V ~ VCM ~ 7V 0.47 0.7 V VTL with Fail-Safe Offset

=

5V

lOUT = 4 rnA, VOUT ~ 0.5 -7V ~ VCM ~ 7V -0.2 -0.42 V

RIN Input Resistance -15V ~ VCM ~ 15V, OV ~ VCC ~ 7V 4 5 kn

RT Line Termination Resistance TA

=

25·C 100 1BO 300 n

Ro Offset Control Resistance TA = 25·C 42 56 70 kn

IINO Data Input Current (Unterminated) VCM

=

10V 2 3.1 rnA

VCM

=

OV OV ~ VCC ~ 7V 0 -0.5 rnA

VCM

=

-10V -2 -3.1 rnA

VTHB Input Balance lOUT

=

-400 IJ-A, VOUT :<! 2.5V, -7V ~ VCM7V

0.1 0.4 V

(Note 5) Rs

=

500n

lOUT

=

4 rnA, VOUT ~ 0.5V, -7V ~ VCM ~ 7V

-0.1 -0.4 V Rs = 500n

VOH Logical "1" Output Voltage lOUT = -400 IJ-A, VOIFF

=

W, VCC

=

4.5V 2.5 3 V VOL Logical "0" Output Voltage lOUT = 4 rnA, VOIFF

=

^{-W, VCC =} 4.5V 0.35 0.5 V

Icc Power Supply Current VCC

=

5.5V VCM

=

15V 10 16 rnA

VOIFF = -0.5V, (Both Receivers) VCM

=

-15V 10 16 rnA IIN(1) Logical "1" Strobe Input Current VSTROBE = 5.5V, VOIFF = 3V 1 100 IJ-A liN (0) Logical "0" Strobe Input Current VSTROBE

=

OV, VOIFF = -3 -290 -400 IJ-A VIH Logical "1" Strobe Input Voltage VOL ~ 0.5, lOUT

=

4mA 2.0 1.12 V VIL Logical "0" Strobe Input Voltage VOH ~ 2.5V, lOUT, = -400 IJ-A 1.12 O.B V los Output Short-Circuit Current VOUT = OV, VCC = 5.5V, VSTROBE = OV, (Note 4) -30 -100 -170 rnA

Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. Except for "Operating Temperature Range"

they are not meant to imply that the devices should be operated at these limits. The table of "Electrical Characteristics" provides conditions for actual device operation.

Note 2: Unless otherwise specified minImax limits apply across the - Ssoc to + 12SOC temperaturo range for the DS78LS120 and across the O"C to + 70°C for the DS88LS120. All typical values are for TA = 2SoC, ^VCC = SV and ^VCM = OV.

Note 3: All currents Into device pins shown as positive, out of device pins as negative, all voltages referenced to ground unless otherwise noted. All values shown as max or min on absolute value basis.

Note 4: Only one output at a time should be shorted.

Note 5: Refer to EIA·RS422 for exact conditions.

1-164

Switching Characteristics

^Vee = 5V, TA = 25°C

Parameter Conditions Min

Differential Input to "0" Output Differential Input to "1" Output

Response Pin Open, CL = 15 pF, RL = 2 kO Strobe Input to "0" Output

Strobe Input to "1" Output

AC Test Circuit and Switching Time Waveforms

Differential and Strobe Input Signal

OUTPUT

INPUT OPEN

':' TL/F17499-3

"Includes probe and test fixture capacitance

Z.5V - - - , - - - . . OIFF

INPUT

-Z.5V _ _ _ J

OUTPUT

Ir = If ~ 10 ns IpdO(O) Ipd1(O) Ipd1(S)

PRR = 1 MHz

Note: Optimum switching response is obtained by minimizing stray capacitance on Response Control pin (no external connection).

Application Hints

Balanced Data Transmission

Typ 38 38 16 12

OUTPUT

1·165

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co

r-Max Units

en _...

60 ns ^N ₀ ...

60 ns C

25 ns

en

co co

25 _ns

r-en ...

N 0

TLlF17499-4

TLlF17499-5

o

C'I

Application Hints

(Continued)

Unbalanced Data Transmission

114 OSI488 OR 1140S1691A/0S3691

J

^VOL

VIL VT VIH

INPUT VOLTAGE TL/F/7499-7

The OS78LS120/0S88LS120 may be used as a level trans-lator to interface between ± 12V MOS, ECL, TTL and CMOS. To configure, bias either input to a voltage equal to

%

the voltage of the input signal, and the other input to the driving gate.

LINE DRIVERS

Line drivers which will interface with the OS78LS1201 OS88LS120 are listed below.

Balanced Drivers OS26LS31 OS7830, OS8830 OS7831, OS8831 OS7832, OS8832 OS1691A,OS3691 OS1692,OS3692 OS3487

Unbalanced Drivers OS1488

OS75150

Quad RS-422 Line Driver Dual CMOS Dual TTL Dual TRI-STATE TTL Dual TRI-STATE TTL Quad RS-423/0ual RS-422 TTL Quad RS-423/0ual TRI-STATE RS-422TTL Quad TRI-STATE RS-422 Quad RS-232 Dual RS-232 RESPONSE CONTROL AND HYSTERESIS

In unbalanced (RS-232/RS-423) applications it is recom-mended that the rise time and fall time of tile line driver be controlled to reduce cross-talk. Elimination of switching noise is accomplished in the OS78LS120/0S88LS120 by the 50 mV of hysteresis incorporated in the output gate.

This eliminates the oscillations which may appear in a line receiver due to the input signal slowly varying about the threshold level for extended periods of time.

High frequency noise which is superimposed on the input Logic Level Translator

OUTPUT

affecting the termination impedance of the transmission line. Noise pulse width rejection vs the value of the re-sponse control capacitor is shown in Figures 1 and 2. This combination of filters followed by hysteresis will optimize performance in a worse case noise environment.

INPUT

RESPONSE CONTROL CAPACITOR (pF)

FIGURE 1. Noise Pulse Width vs Response Control Capacitor

TL/F17499-9

POSITIVE INPUT

NOISE PULSE 0

---I

L --0.5V

TLlF17499-10 FIGURE 2

Application Hints

(Continued)

Dans le document A Corporate Dedication to Quality and Reliability (Page 181-186)