Advanced Micro
APPENDIX D-TRANSACTION REQUEST/OPERATION TIMING
ClK
Transaction Request
ClK
Transaction Request
- - - - « ~ _ _ _ _ ~'~ _ _ _ _ _ _ _ _ _ _ -J,
~>----~<
~>---I
---4~~c---~---I I
1
Data Accepted on this Edge a. Normal Operation, Data Accepted
--~<~--~)>--- --~<~--~)>--- --~<~--~)>--- --~<~--~)>--- --~<~--~)>--- «
»--- »--- »--- »--- »--- «
) >
-\'---'/
b. Halt On Error Mode, Unmasked Exception Present
091148-017C Note: Signals A31-Ao and 031-00 are the Am29000 address and data buses, respectively.
1·182
Figure 01. Timing for the Write Operand R, Write Operand 8, Write Operands R, 8, and Write Instruction Transaction Requests
Am29027
ClK Transaction
< ~
Request
I
A3'-Ao
< )
I
03,-00
< ~
COA OROY OERR
1
Data Accepted on this Edge a.CDA Low
ClK
Transaction
< )
Request I
A3'-Ao
< ~
03,-00
< ~
ICOA
\ ~
OROY OERR
t
Data Accepted on this Edge b. CDA High Initially
Note: Signals A3'-Ao and 03,-00 are the Am29000 address and data buses, respectively.
09114-018C
Figure 02. Timing for the Write Mode, Write Status, and Write Register File Precisions Transaction Requests
1-183
29K Family CMOS Devices
ClK
Transaction Request
ClK
Transaction Request
----~<~--~)~---I
-~(
~>---I
~(
p>---Registers Advanced on this Edge 8.CDA Low
- - - « ) >
-~---~I
- - - «
~>---I
-~( ) >
-I
\'---f-~ ... ~ ... ~
b. CDA High Initially
Registers Advanced
t
on this Edge
09114-019C Note: Signals A31-Ao and D31-Do are the Am29000 address and data buses, respectively.
Figure 03. Timing for the Advance Temp. Registers Transaction Request
1·184
ClK
Transaction Request
ClK
Transaction Request
Am29027
\:-_____ ~X
RD MSBs)>---'\'I..~
lSBsX
MSBs)>---''\ /
---~~~c---a. Read Result MSBs Request Issued in Cycle after
Read Result LSBs Request
~ ____________ ...J) <
Read Result MSBs)>-'---~'
..~
lSBsX
MSBs )<
MSBs)>---~'\ / \ j'
---~,~c---b. Read Result MSBs Request Issued Two or More Cycles after Read Result LSBs Request
09114-020C
Figure 04. Timing for the Read Result LSBs Transaction Request, No Unmasked Exceptions
1-185
29K Family CMOS Devices
1-186
elK
Transaction
Request
~----~)~---~~~ X · ) >
-' \ /
"\ /
09114-021C
Figure 05. Timing for Read Result LSBs Transaction Request, Unmasked Exception Present
ClK
Transaction Request
ClK
Transaction Request
It-
1 or More-I
Cycles
I L
-C~'c---: 1 ) >
-~,~ )~---
' \ /
---~,~,---a. No Unmasked Exceptions Present
It-
1 or More-I
Cycles
I L
-c: ) >
-~~~
)~---' \ / ' \ /
b. Unmasked Exceptions Present
09114-022C
Am29027
Figure 06. Timing for Read Result MSBs~ Read Flags, and Read Status Transaction Requests
1-187
29K Family CMOS Devices
ClK
Transaction Request
ClK
Transaction Request
I-
1 or More-I
Cycles
I L
-C~ave
StateX
Save State)>--- )>--- )>--- )>--- ' \ ' ..
~
lSBsX
MSBs)>---~\ /
a. Second Save State Request Issued In Cycle Following First Request
r---J) <
Save State)>---~'
..~
lSBsX
MSBs )<
MS8s)>---~\ / \ /
----~~~(---b. Second Save State Request Issued Two or More Cycles after First Request
09114-023C
Figure D7. Timing forthe Save State Transaction Request, 64-Bit Resources (Registers R, R-Temp, S, S-Temp; Register File Locations RF7-RFo: Mode Register)
1-188
• ClK
Transaction Request
I-
1 or More-I
Cycles
~
-C:~:
----»).---~,~ )~---
' \ /
Am29027
09114-024C
Figure 08. Timing for the Save State Transaction Request, 32-8it Resources (Instruction Register, Register I-Temp, Status Register, Precision Register)
~ Operation in Progress
II
6 Cycles
ClK
Transaction Request
--<3G)----(
RM)
A31-Ao/
--GX3 S
031-00
OREQTo
~
COA
OROY
V
DEAR
Notes: WRS = Write Operands R, S WI = Write Instruction RM = Read MSBs A. B = Operands A, B INST = Addition Instruction RES = Result
Signals A31-Ao and 031-00 are the Am29000 address and data buses, respectively.
09114-025C
Figure 09. Typical Timing for Single-Precision Operation in Flow-Through Mode-Perform the Operation A PLUS 8, Readthe Result; Mode Register Field PLTC=6
1-189
29K Family CMOS Devices
ClK
b Operation in Progress J
r
... - - - - 6 Cycles - - -...
Transaction
Request
~
___________ R_l ____________~
DREOTo
__ ~f\~ ___________________ _
Notes: WR
=
Write Operand R WI = Write Instruction RM "" Read MSBs B=
Operand BlSB
=
Result LSBsWS = Write Operand S Rl
=
Read lSBsA = Operand A INST = Addition Instruction MSB
=
Result MSBsSignals A31-Ao and 031-00 are the Am29000 address and data buses, respectively.
09114-026C
Figure 010. Typical Timing for the Double-Precision Operation In Flow-Through Mode-Perform the Operation A PLUS B, Read the Result; Mode Register Field PlTC=6
ClK
Transaction Request
-<3G)---(
RM)
A03131-AoI -00
~ ~
OREOTo
~
COA
OROY
V
OERR
V
Notes: WRS
=
Write Operands R, S WI=
Write InstructionRM = Read MSBs A, B
=
Operands A, B 09114-027CINST
=
Addition Instruction RES=
ResultSignals A31-Ao and 031-00 are the Am29000 address and data buses, respectively.
Figure 011. Typical Timing for Single-Precision Operation in Flow-Through Mode, with Unmasked Exception Present-Perform the Operation A PLUS B, Read the Result; Mode Register Field Pl TC=6 1-190
Am29027 Operation in Progress J
~It--- 6 Cycles ---~,
ClK Transaction Request
_ _ _ _ _ _ _ _ _ R_l _ _ _ _ _ _ _
·)~---OREOTo COA OROY
__ ~f\~ __________ _
\\---1/
---~--~\
/
Notes: WR = Write Operand R WI = Write Instruction A = Operand A INST = Addition Instruction MSB = Result MSBs
WS = Write Operand S Rl = Read lSBs B = Operand B lSB = Result lSBs
Signals A3'-Ao and 03,-00 are the Am29000 address and data buses, respectively.
09114-028C
Figure D12. Typical Timing for Double-Precision Operation in Flow-Through Mode, with Unmasked Exception Present-Perform the Operation A PLUS B, Read the Result; Mode Register Field PLTC=6
ClK Transaction
Request
~
_ _ _ _ _ _ _ _ R_M _ _ _ _ _ _~)~---
~---~~r---OREOTo
~---v V
Notes: WRS = Write Operands R, S RM = Read MSBs
WI = Write Instruction A. B = Operands A, B RES = Result
09114-029C INST
=
Addition InstructionSignals A3,-Ao and 03,-00 are the Am29000 address and data buses, respectively.
Figure D13. Typical Timing for Single-Precision Operation in Flow-Through Mode, with DRDY Advanced-Perform the Operation A PLUS B, Read the Result; Mode Register Field PLTC=6
1-191
29K Family CMOS Devices
... ~ _ _ _ _ Operation in Progres;:;..s ---tl~
6 Cycles
CLK
Transaction
Request
~
___________ R_L __________~~
OREOTo _ _ _ _ _ _ _ _ _ _ _ _ _ _
-J~~
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _Notes: WR = Write Operand R WS = Write Operand S
RL = Read LSBs 09114-030C
WI = Write Instruction RM = Read MSBs B = Operand B LSB = Result LSBs
A = Operand A INST.. Addition Instruction MSB = Result MSBs
Signals A31-Ao and 031-00 are the Am29000 address and data buses, respectively.
Figure 014. Typical Timing for Double-Precision Operation In Flow-Through Mode, with ORO Advanced-Perform the Operation A PLUS B, Read the Result; Mode Register Field PLTC=6
CLK
Transaction
Request
~~
_ _ _ _ _ _ R_M _ _ _ _ _ _ _-J)r---
~~---~~r---OREOTo
~~---Notes: WRS = Write Operands R, S RM = Read MSBs INST
=
Addition InstructionWI = Write Instruction A, B
=
Operands A, B RES = Resultv V
Signals A31-Ao and 031-00 are the Am29000 address and data buses, respectively.
09114-031C
Figure 015. Typical Timing for Single-Precision Operation In Flow-Through Mode, with DROY Advanced and Unmasked Exception Present-Perform the Operation A PLUS B, Read the Result;
Mode Register Field PL TC
=
61-192
ClK Transaction Request
Am29027 Operation In Progress d
lit-I - - - - 6 Cycles - - -... ,
_ _ _ _ _ _ _ R_l ________
~)~---OREOTo COA OROY
__ ~f\~ ______________________ _
\'----J/
---~\
/
Notes: WR = Write Operand R WI = Write Instruction A = Operand A INST = Addition Instruction MSB = Result MSBs
WS = Write Operand S Rl = Read lSBs B = Operand B lSB = Result lSBs
Signals A31-Ao and 031-00 are the Am29000 address and data buses, respectively.
09114-037C
Figure D16. Typical Timing for Double-Precision Operation in Flow-Through Mode, with DRDV Advanced and Unmasked Exception Present-Perform the Operation A PLUS B, Read the Result;
elK
Transaction Request
OREOTo
OERR
Notes: WRS = Write Operands R. S WR = Write Operand R A. B = Operands A, B C = Operand C RES = Result
Mode Register Field PL TC
=
6Operation 2 - - -... - - 6 Cycles ---;
lJlnIL
WI = Write Instruction RM = Read MSBs 11
=
Addition Instruction 12 = Multiplication Instruction09114-032C
Signals A31-Ao and 031-00 are the Am29000 address and data buses, respectively.
Figure D17. Typical Timing for Overlapped Single-Precision Operations In Flow-Through Mode; Perform the Compound Operation (A PLUS B) x C by Performing Operations: (1) RFo ~ A PLUS B, (2) RFo x C
Mode Register Field PL TC
=
61-193