Analog Multiplex Register

The analog multiplex register (AMUX) controls the general

interconnection and operation. The control bits in the AMUX are shown inFigure 8-2.

HOLD, DHOLD

These read/write bits control the source connection to the negative input of voltage comparator 2 shown inFigure 8-3. This allows the voltage on the internal temperature sensing diode, the channel selection bus, or the 1:2 divided channel selection bus to charge the internal sample capacitor and to also be presented to comparator 2.

The decoding of these sources is given inTable 8-1.

During the hold case when both the HOLD and DHOLD bits are clear, the VOFF bit in the analog status register (ASR) can offset the V_SS reference on the sample capacitor by approximately 100 mV. This offset source is bypassed whenever the sample capacitor is being charged with either the HOLD or DHOLD bit set. The VOFF bit must be enabled by the analog options mask option.

During a reset the HOLD bit is set and the DHOLD bit is cleared, which connects the internal sample capacitor to the channel selection bus. And since a reset also clears the MUX1:MUX4 bits, the channel selection bus will be connected to V_SS and the internal sample capacitor will be discharged to V_SS following the reset.

NOTE: When sampling a voltage for later conversion, the HOLD and DHOLD bits should be cleared before making any changes in the MUX channel selection. If the MUX channel and the HOLD/DHOLD are changed on the same write cycle to the AMUX register, the sampled voltage may be

$0003 Bit 7 6 5 4 3 2 1 Bit 0

Read:

HOLD DHOLD INV VREF MUX4 MUX3 MUX2 MUX1

Write:

Reset: 1 0 0 0 0 0 0 0

Figure 8-2. Analog Multiplex Register (AMUX)

Figure 8-3. Comparator 2 Input Circuit

Table 8-1. Comparator 2 Input Sources

Case HOLD

Source To Negative Input of Comparator 2

No Sample capacitor connected to comparator 2 negative input; very low leakage current.

1 0

1 1 Yes

Sample capacitor connected to comparator 2 negative input; bottom of capacitor offset from V_SSby approximately 100 mV, very low leakage current.

Divided

Input 0 1 X X No

Signal on channel selection bus is divided by 2 and connected to sample capacitor and comparator 2 negative input Direct

Input 1 0 X X No

Signal on channel selection bus is connected directly to sample capacitor and comparator 2 negative input.

Internal Temperature

Diode

1 1 X X No

Internal temperature sensing diode connected directly to sample capacitor and comparator 2 negative input.

INV

This is a read/write bit that controls the relative polarity of the inherent input offset voltage of the voltage comparators. This bit allows voltage comparisons to be made with both polarities and then averaged together by taking the sum of the two readings and then dividing by 2 (logical shift right).

The polarity of the input offset is reversed by interchanging the internal voltage comparator inputs while also inverting the comparator output. This interchange does not alter the action of the voltage comparator output with respect to its port pins. That is, the output will only go high if the voltage on the positive input (PB2 pin for

comparator 1 and PB0 pin for comparator 2) is above the voltage on the respective negative input (PB3 pin for comparator 1 and PB1 pin for comparator 2). This is shown schematically inFigure 8-4. This bit is cleared by a reset of the device.

1 = Voltage comparators internally inverted 0 = Voltage comparators not internally inverted

Figure 8-4. INV Bit Action

NOTE: The effect of changing the state of the INV bit is to only change the polarity of the input offset voltage. It does not change the output phase of the CPF1 or CPF2 flags with respect to the external port pins.

V–

V+

INV = 0

+COMP V_IO

–

RISE WHEN V+ > V–

INV = 1

V+

V–

+COMP V_IO

–

RISE WHEN V+ > V–

NOTE: Either comparator may generate an output flag when the inputs are exchanged due to a change in the state of the INV bit. It is therefore recommended that the INV bit not be changed while waiting for a comparator flag. Further, any changes to the state of the INV bit should be followed by writing a logical one to both the CPFR1 and CPFR2 bits to clear any extraneous CPF1 or CPF2 flags that may have occurred.

VREF

This read/write bit connects the channel select bus to V_DDfor making a reference voltage measurement. It cannot be selected if any of the other input sources to the channel select bus are selected as shown inTable 8-2. This bit is cleared by a reset of the device.

1 = Channel select bus is connected to V_DDif all MUX1:MUX4 are cleared.

0 = Channel select bus cannot be connected to V_DD. MUX1:MUX4

These are read/write bits that connect the analog subsystem pins to the channel select bus and voltage comparator 2 for purposes of making a voltage measurement. They can be selected individually or combined with any of the other input sources to the channel select bus as shown inTable 8-2.

NOTE: The V_AOFF voltage source shown in Figure 8-1 depicts a small offset voltage generated by the total chip current passing through the package bond wires and lead frame that are attached to the single V_SSpin. This offset raises the internal V_SSreference (AV_SS) in the analog subsystem with respect to the external V_SS pin. Turning on the V_SS MUX to the channel select bus connects it to this internal AV_SS reference line.

When making A/D conversions, this AV_SS offset gets placed on the external ramping capacitor since the discharge device on the PB0/AN0 pin discharges the external capacitor to the internal AV_SS line. Under these circumstances, the positive input (+) to comparator 2 will always be higher than the negative input (–) until the negative input reaches the AV_SS offset voltage plus any offset in comparator 2.

Therefore, input voltages cannot be resolved if they are less than the sum of the AV_SS offset and the comparator offset because they will

Table 8-2. Channel Select Bus Combinations

Analog Multiplex Register Channel Select Bus Connected to:

VREF MUX4 MUX3 MUX2 MUX1 V_DD PB4/AN4/

TCMP

PB3/AN3/

TCAP PB2/AN2 PB1/AN1 V_SS

0 0 0 0 0 - - - - - - - - - - - - - - - ON

X 0 0 0 1 - - - - - - - - - - - - ON

-X 0 0 1 0 - - - - - - - - - ON - - -

-X 0 0 1 1 - - - - - - - - - ON ON

-X 0 1 0 0 - - - - - - ON - - - - - -

-X 0 1 0 1 - - - - - - ON - - - ON

-X 0 1 1 0 - - - - - - ON ON - - -

-X 0 1 1 1 - - - - - - ON ON ON

-X 1 0 0 0 - - - ON - - - - - - - - -

-X 1 0 0 1 - - - ON - - - - - - ON

-X 1 0 1 0 - - - ON - - - ON - - -

-X 1 0 1 1 - - - ON - - - ON ON

-X 1 1 0 0 - - - ON ON - - - - - -

-X 1 1 0 1 - - - ON ON - - - ON

-X 1 1 1 0 - - - ON ON ON - - -

-X 1 1 1 1 - - - ON ON ON ON

-1 0 0 0 0 ON - - - - - - - - - - - -

-X = Don’t Care

- - - = High Impedance