ADDRESSES OF ETHERNET FUNCTIONS

All Ethernet functions may be accessed as long words at the addresses given in Table 12-5. Except for the Port command,each function may also be accessed as a byte at the byte address that corresponds to the least significant byte of the long word, that is, long word address plus 3.

Revision A (Preliminary) I June 1991

TABLE 12·5

Ethernet pertphera

a

Address Function Notes

02EO,OOOO'6 Write: 82596CA Port command This address MUST be accessed as a long word.

Writing to this address generates the PORT signal to the 82596CA. The data for the write is the 32-bit value to be latched by the 82596CA. See Table 12-3.

Read: Not used.

02EO,OO04'6 Write: 82596CA Channel Attention Writing to this address generates the CA signal to the command 82596CA. The data for the write is of no consequence.

Read: Not used.

02EO,OO08,6 Write: Not used.

Read: Not used.

02EO,OOOC'6 Write: Ethernet section interrupt Writing to this address clears an active Ethernet clear. section interrupt. Data for the write is of no

consequence. Clearing the interrupt turns off the interrupt signal but does not clear either of the causes of the interrupt.

Read: Not used.

02EO,0010'6 Write: 82596CA interrupt Writing a 1 to the least significant bit of this address enable/d isable enables the interrupt signal from the 82596CA. Writing

a 0 to the least significant bit disables the interrupt.

Reading from this address returns the state of the enable bit as the least significant bit. The other bits are undefined.

Read: 82596CA interrupt enable/disable

02EO,0014'6 Write: Abort interrupt enable/disable Writing a 1 to the least significant bit of this address enables the 82596CA abort interrupt. Writing a 0 to the least significant bit disables the interrupt. Reading from this address returns the state of the enable bit as the least significant bit. The other bits are undefined.

Read: Abort interrupt enable/disable 02EO,0018'6' Write: Not used.

Read: 82596CA interrupt status Reading from this address returns the state of the 82596CA interrupt signal as the least significant bit. A 1 bit indicates the interrupt is asserted; 0 indicates not asserted. The other bits are undefined.

02EO,001 C'6 Write: Clear abort interrupt. Writing to this address clears the 82596CA abort condition. The data for the write is of no consequence.

Read: Abort interrupt status Reading from this address returns the state of the 82596CA abort interrupt signal as the least significant bit. A 1 bit indicates the interrupt is asserted; 0 indicates not asserted. The other bits are undefined.

02EO,0020_'6 - Not used.

02EO,OO37,6 Continues

Revision A (Preliminary) I June 1991

TABLE 12-5 - Continued Ethernet addresses

Address Function Notes

02EO,OO38'6 Write: Hardware trigger point #1

Read: Not used. Writing to these addresses produces a low-going pulse at one of two test points. The data are of no consequence. These addresses and test points are intended to aid debugging.

02EO,OO3C'6 Write: Hardware trigger point #2 Read: Not used

12.8.1 Interrupts

The Ethernet interrupt causes a level 1 interrupt autovector to the CPU (vector 25).

The Ethernet interrupt combines interrupt conditions from two sources:

1. The interrupt signal from 82596cA controller itself.

2 The ABORT condition. The ABORT condition is generated by logic external to the 82596CA (see section 12.9.1). It is set when the 82596CA receives an exception acknowledge as the response to a bus cycle.

To cause an interrupt, an interrupt condition must be enabled.

Each of the two interrupt conditions has its own enable.

Once the Ethernet interrupt is asserted, it stays asserted until the processor writes to the interrupt clear address. Likewise, each interrupt condition stays asserted until explicitly cleared or disabled by the processor.

The ABORT condition is cleared by writing to the ABORT clear address. The 82596CA interrupt is cleared by setting the appropri-ate acknowledge bits in the command word of the 82596CA's sys-tem control block (SCB), setting the next control commands in the command word of the SCB, and issuing a Channel Attention to the 82596cA.

The sequence of events for dealing with an Ethernet interrupt due to an ABORT condition are:

Revision A (Preliminary) / June 1991

1. Enable the interrupt.

2. Assume that some time later the ABORT condition becomes asserted. Once asserted, it will stay asserted until explicitly cleared.

3. The enabled ABORT condition causes the Ethernet interrupt to be asserted.

It will stay asserted until explicitly cleared.

4. The interrupt causes the HK68N3D to execute the Ethernet interrupt service routine. The interrupt service routine of the processor clears the Ethernet interrupt.

5. The interrupt service routine reads the interrupt status bits to determine whether the interrupt is an ABORT condition or 82596cA interrupt signal. (This and the previous step may be interchanged.)

6. The interrupt service routine clears the ABORT condition. At this point, both the interrupt signal and the ABORT condition have been cleared.

If the second interrupt condition is enabled and occurs before the first is cleared, it will cause the interrupt signal to be asserted only after the first condition is cleared; that is, not after the Ethernet interrupt is cleared, but after the interrupting condition (ABORT or 82596cA interrupt) is cleared. Thus, the interrupt signal may be cleared early in an interrupt service routine knowing that it cannot be reasserted until later in the routine when the interrupting condition is cleared.

If the interrupt service routine checks the interrupt status bits and both are set, it is not possible to determine which of the two occurred first and thus which one to clear. In this case, the inter-rupt service routine should handle both cases and clear both conditions.

If an interrupt condition is true when it is enabled, an interrupt will occur immediately.

Disabling an interrupt source is equivalent to clearing it to the extent that it allows the other interrupt condition to generate an interrupt.

Revision A (Preliminary) I June 1991