ADDRESS JUMP

ADDRESS

(P + l---.L, R)

NO

BRING NEXT

INSTRUCTION

(W-+U)

TRANSFER

t - - - - -____

^a.

SENSE CODE

YES

(U o -

^U8~E

^BUS)

FORM EFFECTIVE ADDRESS (FIG. 3-8)

R+L & R

BRING INSTRUCTION

(W-+U)

P0131812A

The ni ne bi ts represented by XYY are placed on the party I ine

I/O

bus and represent the condi ti on to be tested.

X defines a specific line within device YY. The associated peripheral controller replies with a true or false signal.

If a true signa 1 is received by the DATA

620/i,

a jump is made to the jump address. If a false signal is received, the next instruction in sequence is executed.

Indexing: No

Indirect Addressing: Yes Regi sters A I tered: P 4.3.3 Data Transfer In

Two types of data transfer in instructions are provided: input to operational registers, and input directly to memory. The first type of input instruction is a single-word, non-addressing instruction; the second type is a double-word addressing instruction.

~

Clear and Input to A Register Timing: 2 cycles

17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 0

10 2

5ZZ

r-T-

L_..l. _ ... _ _ _ _ _ _

!

-'--_ _ _ ^~ _ _ _ _ _ _ _ _ _ ___I

lIS-bit I

option

The A register is cleared and a data word from the selected device, ZZ, is transferred to the A register.

Indexing: No

Indirect Addressi ng: No Reg is ters A I tered: A

4-7

4-8

~

Clear and Input to B Register Timing: 2 cycles 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 0

10 2 6ZZ

r-r-!

L_..L _ ... _ _ _ _ _ ---' _ _ _ _ '"'--_ _ _ _ _ _ _ _ ...

lIB-bit I

option

The B register is cleared and a data word from the selected device, ZZ, is transferred to the B register.

Indexing: No

Indirect Addressing: No Registers Altered: B

Input to A Register Timing: 2 cycles 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 0

,-T- !

^{10 2 lZZ}

L_-L _ ... _ _ _ _ _ ---' _ _ _ _ '"'--_ _ _ _ _ _ _ _ - "

lIB-bit I

option

A data word from the selected device, ZZ, is inclusively-OR led with the contents of the A register.

Indexing: No

I ndirect Addressing: No Reg isters A I tered: A

I nput to B Register Timing: 2 cycles 17 16 15 14 13 12 11

10 9 8

7 6 5

4 3 2 0

,- T -

L _.1. _ .L.. _ _ _ _ _

!

¹⁰ ---'-_ _ _ _ _ ² 1....-_ _ _ _ _ _ _ _ ^2ZZ ...

lIB-bit I

option

A data word from the selected device, ZZ, is inclusively-ORled with the contents of the B register.

n n+1

Indexing: No

Indirect Addressing: No Reg i sters A I tered: B

~

Input to Memory Timing: 3 cycles

17 16 15 14 13 12 11 10

9 8

7 6 5 4 3 2 1 0

r-r- I I

I I 10 2 OZZ

~-+-

I

I

I 1

Da ta Address

tyL_

18-b..!.!..

option

A data word from the selected device, ZZ, is placed in the cleared effective memory address. Figure

4-3

shows the execution of this instruction.

Indexing: No

Indirect Addressing: No Reg is ters A I tered: Memory

4.3.4

Data Transfer

Ou

t

Two types of output data transfer instructions are provided:

output from operationa I registers and output from memory.

The first type of instruction is a single-word, non-addressing instruction; the second type is a double-word, adqressing i nstructi on.

Output from A Register Timing: 2 cycles 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 0

,-,- !

^{10 3 1ZZ}

L_ J..._ ... _ _ _ _ _ _ _ _ 1....-_ _ _ - ' - -_ _ _ _ _ _ _ _ ----.1

IIS-bitl

option

The contents of the A register are transferred to the selected device, ZZ.

Indexing:, No

Indirect Addressing: No Reg i s ters A I tered: None

4-9

~ I

o

... ...

-... ...

BRING

INSTRUCTION

r:N~U)

BRING OPERAND ADDRESS

(W~R)

ADDRESS NEXT

INSTRUCTION (P +

l~L,P)

P0131813A

ADDRESS TRANSFER

.... OPERAND ... ^DEVICE

... _ADDRESS ... CODE

(P

+

1

~L,P) (U - U-E

o ^{5 BUS)}

FORM

EFFECTIVE INPUT

.... ... _DATA

.... _ADDRESS --..

(FIG. 3-8) (E BUS

~W)

BRING

.

... NEXT

.... INSTRUCTION

(VV~U)

n n+l

4.4 OPTIONAL AUTOMATIC CONTROL FUNCTIONS (di rect-memory-access-a nd-i nterrupt I ogi c opti on)

Output from B Register Timing: 2 cycles 17 16 15 14 13 12 11 10

9 8

7

6 5 4

3 2 0

10

3 2ZZ

r-T- :

_{L _} J.. _ ... _ _ _ _ _ _ --'-_ _ _ ---IL...-_ _ _ _ _ _ _ _ -.I

lIB-bit I

option

The contents of the B registers are transferred to the selected device, ZZ.

Indexing: No

Indirect Addressing: No Registers Altered: None

I

^¢ME

I

Ou tpu t from Memory Timing: 3 cycles 17 16 15 14 13 12 11 10

9 8

7 6

543

2 1 0

r-T- I I

I ^I 10 3

OZZ

r-+

I I

I ^I Da ta Address

~L_

18-bi!..

option

The contents of the effective memory location are transferred to the selected device, ZZ.

Indexing: No

Indirect Addressing: No Reg i s ters A I tered: None

Two types of computer timing sequences are provided to automatically transfer control and information signals be1ween peripheral devices and the DATA 620/i:

a. An interrupt timing sequence is initiated when the DATA 620/i recognizes an external interrupt signal.

This sequence forces the computer to execute an instruction at the memory location specified by interrupt logic through the E bus.

4-11

b. A trap timing sequence is initiated when an external device signals that it must transfer a word to or from memory. The externa I devi ce must supply the memory address of the word through the E bus. Th is sequence delays the internal program sequence for the time

required to execute the,I/O transfer (2.7 microseconds).

The devi.ces that demand either of those automatic sequences must first have priorities to resolve two or more simultaneous demands for service. The priorities of devices demanding service are determined every 0.9 microseconds, and are clocked by the interrupt clock. Refer to the interface

reference manua I (VDM-300l) for a more detai led description.

Priority assignment for devices on the I/O cable is optional and is a part of the system definition. Priorities may be fixed for any given configuration by properly connecting pri ori ty lines in the I/O ca ble. Priori ti es can be a I tered if the definition changes.

4.4.1 Interlace Data Transfers

I nterlace optional data transfers may be performed concurrently with internal program operation. This type of operation uses

the computer trap-timing sequence to delay the program for 2.7 microseconds whi Ie a word is transferred between memory and a peripheral device. The transfer is controlled by the external device_r which must transmit the memory address of the data word, and must synchronize the operation using the signals transmitted on the I/O control lines. The maximum interlace transfer rate is 202_r 000 words per second.

The general trap-sequence flow is shown in figure 4-4. The maximum computer delay in acknowledging a trap request is 5.4 microseconds. However_r the time delay experienced by a specific controller in receiving acknowledgment to a trap request may be extended by the time required for the computer to service higher-priority requests.

Special peripheral controllers designed for system applications (such as A/D and D/ A converters) may uti I ize the trap

facilities of the computer to implement automatic I/O operations (refer to the interface reference manual for detailed design information). A buffer interlace controller (BIC) is also available for use with all standard DATA 620/i peripheral equipment. Special system devices may be inter-faced for interlace operations under control of the BIC.

Dans le document DATA 620/i (Page 99-106)