add me addme - PowerPC 405GP . Embedded Processor User's Manual

Add to Minus One Extended

234

21 22 31

The sum of the contents of register RA, XER[CA], and -1 is placed into register RT.

XER[CA] is set to a value determined by the unsigned magnitude of the result of the add operation.

Registers Altered

This instruction is part of the PowerPC User Instruction Set Architecture.

Preliminary Instruction Set 24-13

addze

Add to Zero Extended addze

The sum of the contents of register RA and XER[CA] is placed into register RT.

202

XER[CA] is set to a value determined by the unsigned magnitude of the result of the add operation.

Registers Altered

This instruction is part of the PowerPC User Instruction Set Architecture.

24-14 PPC405GP User's Manual Preliminary

and

RA,RS,RS

and.

RA,RS,RS

RS

0 6 11

(RA) (- (RS) 1\ (RB)

Rc=O Rc=1

RB

28 21

and

AND

IRcl

The contents of register RS are ANDed with the contents of register RS; the result is placed into register RA.

Registers Altered

• RA

• CR[CROkT, GT, EO,

so

if Rc contains 1

Architecture Note

This instruction is part of the PowerPC User Instruction Set Architecture.

Preliminary Instruction Set 24·15

andc

AND with Complement

andc

andc.

o

RA,RS,RB RA,RS,RB

RS 6

(RA) (- (RS) /\ -,(RB)

RA 11

Rc=O Rc=1

RB 16

21 2 31

The contents of register RS are ANOed with the ones complement of the contents of register RB; the result is placed into register RA.

Registers Altered

• RA

• CR[CROlLT, GT, EO, so if Rc contains 1

Architecture Note

This instruction is part of the PowerPC User Instruction Set Architecture.

24-16 PPC405GP User's Manual Preliminary

andi.

AND Immediate andl. RA, RS,

1M

28 RS RA 1M

o

6 11 16 31

(RA) ~ (RS) /\ (160

II

1M)

The

1M

field is extended to 32 bits by concatenating 16 O-bits on its left. The contents of register RS is ANDed with the extended

1M

field; the result is placed into register RA.

Registers Altered

• RA

• CR[CRO]LT, GT, EO, so Programming Note

The andi. instruction can test whether any of the 16 least-significant bits in a GPR are 1-bits.

andi. is one of three instructions that implicitly update CR[CRO] without having an Rc field. The other instructions are addic. and andis ..

Architecture Note

This instruction is part of the PowerPC User Instruction Set Architecture.

Preliminary Instruction Set 24-17

andis.

AND Immediate Shifted

andis.

RA, RS, 1M

29 RS RA 1M

o

6 11 16 31

(RA) ~ (RS) A (1M

II

¹⁶0)

The 1M field is extended to 32 bits by concatenating 16 O-bits on its right. The contents of register RS are ANDed with the extended 1M field; the result is placed into register RA.

Registers Altered

• RA

• CR[CRO]LT, GT, EO, so

Programming Note

The

andis.

instruction can test whether any of the 16 most-significant bits in a GPR are 1-bits.

andis.

is one of three instructions that implicitly update CR[CRO] without having an Rc field. The other instructions are

addic.

and

andi ..

Architecture Note

This instruction is part of the PowerPC User Instruction Set Architecture.

24-18 PPC405GP User's Manual Preliminary

The next instruction address (NIA) is the effective address of the branch. The NIA is formed by adding a displacement to a base address. The displacement is obtained by concatenating two O-bits to the right of the LI field and sign-extending the result to 32 bits. .

If the AA field contains 0, the base address is the address of the branch instruction, which is also the current instruction address (CIA). If the AA field contains 1, the base address is

o.

Program flow is transferred to the NIA.

If the LK field contains 1, then (CIA

+

4) is placed into the LR.

Registers Altered

• LR if LK contains 1

Architecture Note

This instruction is part of the PowerPC User Instruction SetArchitecture.

Preliminary Instruction Set 24-19

be

The BI field specifies a bit in the CR to be used as the condition of thebranch.

30 31

If the AA field contains 0, the base address is the address of the branch instruction, which is also the current instruction address (CIA). If the AA field contains 1, the base address is 0.

The BO field controls options that determine when program flow is transferred to the NIA. The BO field also controls branch prediction, a performance-improvement feature. See "Branch Prediction" on page 3-36 for a complete discussion.

If the LK field contains 1, then (CIA

+

4) is placed into the LR.

Registers Altered

• CTR if B02 contains

°

• LR if LK contains 1

24-20 PPC405GP User's Manual Preliminary

be

Branch Conditional Architecture Note

This instruction is part of the PowerPC User Instruction Set Architecture.

Table 24-7. Extended Mnemonics for bc, bca, bcl, bcla

Other Registers

Mnemonic Operands Function Altered

bdnz target Decrement CTR; branch if CTR -:;:.

o.

Extended mnemonic for be 16,O,target

bdnza Extended mnemonic for

bea 16,O,target

bdnzl Extended mnemonic for (LR) (- CIA + 4.

bel 16,O,target

bdnzla Extended mnemonic for (LR) (- CIA + 4.

bela 16,O,target

bdnzf cr_bit, target Decrement CTR.

Branch if CTR -:;:. 0 AND CRcr_bit

= o.

Extended mnemonic for be O,er_bit,target

bdnzfa Extended mnemonic for

bea O,er_bit,target

bdnzfl Extended mnemonic for (LR) (- CIA + 4.

beIO,er_bit,target

bdnzfla Extended mnemonic for (LR) (- CIA + 4.

bela O,er_bit,target

bdnzt ccbit, target Decrement CTR.

Branch if CTR -:;:. 0 AND CRccbit

=

^1.

Extended mnemonic for be 8,er_bit,target

bdnzta Extended mnemonic for

bea 8,er_bit,target

bdza Extended mnemonic for

bea 18,O,target

bdzl Extended mnemonic for (LR) (- CIA + 4.

bel 18,O,target

bdzla Extended mnemonic for (LR) (- CIA + 4.

bela 18,O,target

Preliminary Instruction Set 24-21

be

Branch Conditional

Table 24-7. Extended Mnemonics for bc, bca, bcl, bcla (continued)

Other Registers

Mnemonic Operands Function Altered

bdzf cr_bit, target Decrement CTR

Branch if CTR

=

0 AND CRccbit

= o.

Extended mnemonic for be 2,er_bit,target

bdzfa Extended mnemonic for

bea 2,er_bit,target

bdzfl Extended mnemonic for (LR) (- CIA + 4.

beI2,er_bit,target

bdzfla Extended mnemonic for (LR) (- CIA + 4.

bela 2,er_bit,target bdzt cr_bit, target Decrement CTA.

Branch if CTR

=

0 AND CRccbit

=

Extended mnemonic for be 10,er_blt,target

bdzta Extended mnemonic for

bea 10,er_bit,target

target Use CRO if ccfieid is omitted.

Extended mnemonic for be 12,4*er_field+2,target

beqa Extended mnemonic for

bea 12,4*er _field+2, target

beql Extended mnemonic for (LR) (- CIA + 4.

bfa Extended mnemonic for

bea 4,ecbit,target

bfl Extended mnemonic for LR

beI4,er_bit,target

bfla Extended mnemonic for LR

bela 4,er_bit,target

24-22 PPC405GP User's Manual Preliminary

be

Branch Conditional

Table 24-7. Extended Mnemonics for bc, bca, bcl, bcla (continued)

Other Registers

Mnemonic Operands Function Altered

bge [cr_field,] Branch if greater than or equal.

target Use CRO if cr_field is omitted.

Extended mnemonic for be 4,4*ecfield+O,target

bgea Extended mnemonic for

bea 4,4*er_fleld+O,target

bgel Extended mnemonic for LR

beI4,4*er_field+O,target

bgela Extended mnemonic for LR

bela 4,4*er_field+O,target bgt [cr_field,] Branch if greater than.

target Use CRO if ccfieid is omitted.

Extended mnemonic for be 12,4*er _field+ 1 ,target

bgta Extended mnemonic for

bea 12,4*er_field+ 1 ,target

bgtl Extended mnemonic for LR

bel 12,4*er_field+1 ,target

bgtla Extended mnemonic for LR

bela 12,4*er _field+ 1, target ble [ccfield,] Branch if less than or equal.

target Use CRO if ccfieid is omitted.

Extended mnemonic for be 4,4*er _field+ 1, target

blea Extended mnemonic for

bea 4,4*er_field+1 ,target

blel Extended mnemonic for LR

beI4,4*er_field+1,target

blela Extended mnemonic for LR

bela 4,4*er_field+1,target

bit [ccfield,] Branch if less than

target Use CRO if ccfieid is omitted.

Extended mnemonic for be 12,4*er_field+O,target

blta Extended mnemonic for

bea 12,4*er_field+O,target

bltl Extended mnemonic for (LR) t--CIA + 4.

bel 12,4*er _field+O,target

bltla Extended mnemonic for (LR) t--CIA + 4.

bela 12,4*er _field+O, target

Preliminary Instruction Set 24-23

be

Branch Conditional

Table 24-7. Extended Mnemonics for bc, bca, bcl, bcla (continued)

Other Registers

Mnemonic Operands Function Altered

bne [ccfield,] Branch if not equal.

target Use CRO if ccfieid is omitted.

Extended mnemonic for be 4,4*er _fleld+2,target

bnea Extended mnemonic for

bea 4,4*er _fleld+2, target

bnel Extended mnemonic for (LR) ~ CIA + 4.

beI4,4*er_fleld+2,target

bnela Extended mnemonic for (LR) ~ CIA + 4.

bela 4,4*er _fleld+2,target bng [cr_field,] Branch if not greater than.

target Use CRO if cr_field is omitted.

Extended mnemonic for be 4,4*er_fleld+1,target

bnga Extended mnemonic for

bea 4,4*er _fleld+ 1 ,target

bngl Extended mnemonic for (LR) ~ CIA + 4.

bel 4,4*er_fleld+1 ,target

bngla Extended mnemonic for (LR) ~ CIA + 4.

bela 4,4*er_fleld+1 ,target

bnl [ccfield,] Branch if not less than; use CRO if cr_field is omitted.

target Extended mnemonic for

be 4,4*er_field+O,target

bnla Extended mnemonic for

bea 4,4*er_fleld+O,target

bnll Extended mnemonic for (LR) ~ CIA + 4.

beI4,4*er_fleld+O,target

bnlla Extended mnemonic for (LR) ~ CIA + 4.

bela 4,4*er_field+O,target

bns [ccfield,] Branch if not summary overflow.

target Use CRO if ccfieid is omitted.

Extended mnemonic for be 4,4*er_field+3,target

bnsa Extended mnemonic for

bea 4,4*ecfleld+3,target

bnsl Extended mnemonic for (LR) ~ CIA + 4.

bel 4,4*er _fleld+3, target

bnsla Extended mnemonic for (LR) ~ CIA + 4.

bela 4,4*er _fleld+3,target

24-24 PPC405GP User's Manual Preliminary

be

Branch Conditional

Table 24·7. Extended Mnemonics for bc, bca, bcl, bcla (continued)

Other Registers

Mnemonic Operands Function Altered

bnu [ccfield,) Branch if not unordered.

target Use CRO if ccfieid is omitted.

Extended mnemonic for be 4,4*er_field+3,target

bnua Extended mnemonic for

bea 4,4*er_fleld+3,target

bnul Extended mnemonic for (LR) ~ CIA + 4.

beI4,4*er_field+3,target

bnula Extended mnemonic for (LR) ~ CIA + 4.

bela 4,4*er _fleld+3,target bso [cr_field,) Branch if summary overflow.

target Use CRO if ccfieid is omitted.

Extended mnemonic for be 12,4*er_field+3,target

bsoa Extended mnemonic for

bea 12,4*er _field+3, target

bsol Extended mnemonic for (LR) ~ CIA + 4.

bta Extended mnemonic for

bea 12,er_bit,target

btl Extended mnemonic for (LR) ~ CIA + 4.

bel 12,er_bit,target

btla Extended mnemonic for (LR) ~ CIA + 4.

bela 12,er_bit,target

bun [ccfield), Branch if unordered.

target Use CRO if cr_field is omitted.

Extended mnemonic for be 12,4*er_fleld+3,target

buna Extended mnemonic for

bea 12,4*er_fleld+3,target

bunl Extended mnemonic for (LR) ~ CIA + 4.

bel 12,4*er_fleld+3,target

bunla Extended mnemonic for (LR) ~ CIA + 4.

bela 12,4*er_fleld+3,target

Preliminary Instruction Set 24·25

bcctr

Branch Conditional to Count Register

bcctr

The next instruction address (NIA) is the target address of the branch. The NIA is formed by concatenating the 30 most significant bits of the CTR with two O-bits on the right.

If the lK field contains 1, then (CIA

+

4) is placed into the LR. branch condition is true, the branch is taken; the NIA is the contents of the CTR after it is decremented.

Architecture Note

This instruction is part of the PowerPC User Instruction Set Architecture.

24-26 PPC405GP User's Manual Preliminary

bcctr

Branch Conditional to Count Register

Table 24-8. Extended Mnemonics for bcctr, bcctrl

Other Registers

Mnemonic Operands Function Altered

bctr Branch unconditionally to address in CTA.

Extended mnemonic for bcctr 20,0

bctrl Extended mnemonic for (LR) ~ CIA + 4.

bcctrl20,0

beqctr [ccfield] Branch, if equal, to address in CTR Use CRO if ccfieid is omitted.

Extended mnemonic for

Use CRO if ccfieid is omitted.

Extended mnemonic for bcctr 4,4*cr_field+0

bgectrl Extended mnemonic for (LR) ~ CIA + 4.

bcctrI4,4*cr_field+0

bgtctr [ccfield] Branch, if greater than, to address in CTR.

Use CRO if ccfieid is omitted.

Extended mnemonic for bcctr 12,4*ccfield+ 1

bgtctrl Extended mnemonic for (LR) ~ CIA + 4.

bcctrI12,4*cr_field+1

blectr [cr_field] Branch, if less than or equal, to address in CTA.

Use CRO if cr_field is omitted.

Extended mnemonic for bcctr 4,4*cr _field+ 1

blectrl Extended mnemonic for (LR) ~ CIA + 4.

bcctrI4,4*cr_field+1

bltctr [ccfield] Branch, if less than, to address in CTA.

Use CRO if ccfieid is omitted.

Extended mnemonic for bcctr 12,4*ccfield+0

bltctrl Extended mnemonic for (LR) ~ CIA + 4.

bcctrI12,4*cr_field+0

Preliminary Instruction Set 24-27

bcctr

Branch Conditional to Count Register

Table 24-8. Extended Mnemonics for bcctr, bcctrl (continued)

Other Registers

Mnemonic Operands Function Altered

bnectr [cr_field] Branch, if not equal, to address in CTA.

Use CRO if ccfieid is omitted.

Extended mnemonic for bcctr 4,4*ccfield+2

bnectrl Extended mnemonic for (LR) ~ CIA + 4.

bcctrl 4,4*cr _field+2

bngctr [ccfield] Branch, if not greater than, to address in CTA.

Use CRO if ccfieid is omitted.

Extended mnemonic for bcctr 4,4*ccfield+ 1

bngctrl Extended mnemonic for (LR) ~ CIA + 4.

bcctrI4,4*cr_field+1

bnlctr [ccfield] Branch, if not less than, to address in CTR.

Use CRO if ccfieid is omitted.

Extended mnemonic for bcctr 4,4*cr_field+O

bnlctrl Extended mnemonic for (LR) ~ CIA + 4.

bcctrI4,4*cr_field+O

bnsctr [ccfield] Branch, if not summary overflow, to address in CTA.

Use CRO if cr_field is omitted.

Extended mnemonic for bcctr 4,4*cr _field+3

bnsctrl Extended mnemonic for (LR) ~ CIA + 4.

bcctrI4,4*cr_field+3

bnuctr [ccfield] Branch, if not unordered, to address in CTR; use CRO if cr_field is omitted.

Extended mnemonic for bcctr 4,4*cr _field+3

bnuctrl Extended mnemonic for (LR) ~ CIA + 4.

bcctrI4,4*cr_field+3

bsoctr [ccfield] Branch, if summary overflow, to address in CTR.

Use CRO if cr_field is omitted.

24-28 PPC405GP User's Manual Preliminary

bcctr

Branch Conditional to Count Register Table 24-8. Extended Mnemonics for bcctr, bcctrl (continued)

Other Registers

Mnemonic Operands Function Altered

bunctr [cr_field] Branch if unordered to address in CTR.

Use CRO if ccfieid is omitted.

Extended mnemonic for bcctr 12,4*ccfield+3

bunctrl Extended mnemonic for (LR) f--CIA + 4.

bcctrI12,4*cr_field+3

Preliminary Instruction Set 24-29

bclr

Branch Conditional to Link Register

bclr

The BI field specifies a bit in the CR to be used as the condition of the branch.

The next instruction address (NIA) is the target address of the branch. The NIA is formed by concatenating the 30 most Significant bits of the LR with two O-bits on the right.

The BO field cbntrols options that determine when program flow is transferred to the NIA. The BO field also controls branch prediction, a performance-improvement feature. See "Branch Prediction" on page 3-36 for a complete discussion.

If the LK field contains 1, then (CIA

+

4) is placed into the LR.

This instruction is part of the PowerPC User Instruction Set Architecture.

Table 24-9. Extended Mnemonics for bclr, bclrl

Mnemonic Operands Function

blr Branch unconditionally to address in LA.

Extended mnemonic for bclr 20,0

blrl Extended mnemonic for

bclrl20,0

24-30 PPC405GP User's Manual Preliminary

Other Registers Altered

(LR) ~ CIA + 4.

bclr

Branch Conditional to Link Register

Table 24-9. Extended Mnemonics for bclr, bclrl (continued)

Other Registers

Mnemonic Operands Function Altered

bdnzlr Decrement CTR.

Branch if CTR :F-0 to address in LR.

Extended mnemonic for bclr 16,0

bdnzlrl Extended mnemonic for (LR) (- CIA + 4.

bclrl16,0

bdnzflr cr_bit Decrement CTA.

Branch if CTR :F-0 AND CRccbit

=

0 to address in LA.

Extended mnemonic for bclr O,cr_bit

bdnzflrl Extended mnemonic for (LR) (- CIA + 4.

bclrl O,cr _bit

bdnztlr ccbit Decrement CTR.

Branch if CTR :F-0 AND CRcr_bit

=

1 to address in LR.

Extended mnemonic for bclr B,cr_bit

bdnztlrl Extended mnemonic for (LR) (- CIA + 4.

bclrl B,cr _bit

bdzlr Decrement CTR.

Branch if CTR

=

0 to address in LA.

Extended mnemonic for bclr 18,0

bdzlrl Extended mnemonic for (LR) (- CIA + 4.

bclrl18,0

bdzflr ccbit Decrement CTA.

Branch if CTR

=

0 AND CRcr_bit

=

0 to address in LR.

Extended mnemonic for bclr 2,ccbit

bdzflrl Extended mnemonic for (LR) (- CIA + 4.

bclrI2,cr_bit

bdztlr cr_bit Decrement CTA.

Branch if CTR

=

0 AND CRccbit

=

1 to address in LR.

Extended mnemonic for bclr 10,cr_bit

bdztlrl Extended mnemonic for (LR) (- CIA + 4.

bclrI10,cr....:.bit

beqlr [cr_field] Branch if equal to address in LA.

Use CRO if ccfieid is omitted.

Extended mnemonic for bclr 12,4*ccfield+2

beqlrl Extended mnemonic for (LR) (- CIA + 4.

bclrI12,4*ccfield+2

Preliminary Instruction Set 24-31

bclr

Branch Conditional to Link Register

Table 24-9. Extended Mnemonics for bclr, bclrl (continued)

Other Registers

Mnemonic Operands Function Altered

bflr ccbit Branch if CRcr_bit

=

0 to address in LR.

Extended mnemonic for bclr 4,cr_blt

bflrl Extended mnemonic for (LR) ~ CIA + 4.

bc!rl 4,ccblt

bgelr [cr_field] Branch, if greater than or equal, to address in LR.

Use CRO if ccfield is omitted.

Extended mnemonic for bclr 4,4*ccfield+O

bgelrl Extended mnemonic for (LR) ~ CIA + 4.

bclrI4,4*cr_field+O

bgtlr [ccfield] Branch, if greater than, to address in LR.

Use CRO if ccfield is omitted.

Extended mnemonic for

Use CRO if cr_field is omitted.

Extended mnemonic for bclr 12,4*cr_field+O

bltlrl Extended mnemonic for (LR) ~ CIA + 4.

bclrI12,4*cr_field+O

bnelr [ccfield] Branch, if not equal, to address in LR.

Use CRO if ccfieid is omitted.

Extended mnemonic for bclr 4,4*cr_field+2

bnelrl Extended mnemonic for (LR) ~ CIA + 4.

bclrl 4,4*ccfield+2

bnglr [ccfield] Branch, if not greater than, to address in LR.

Use CRO if cr_field is omitted.

Extended mnemonic for bclr 4,4*cr_field+1

bnglrl Extended mnemonic for (LR) ~ CIA + 4.

bclrl 4,4*ccfield+1

24-32 PPC405GP User's Manual Preliminary

bclr

Branch Conditional to Link Register

Table 24-9. Extended Mnemonics for bclr, bclrl (continued)

Other Registers

Mnemonic Operands Function Altered

bnllr [ccfield] Branch, if not less than, to address in LA.

Use CRO if cr_field is omitted.

Extended mnemonic for bclr 4,4*cr_fleld+O

bnllrl Extended mnemonic for (LR) ~ CIA + 4.

bclrI4,4*cr_fleld+O

bnslr [ccfield] Branch if not summary overflow to address in LA.

Use CRO if ccfieid is omitted.

Extended mnemonic for bclr 4,4*cr_fleld+3

bnslrl Extended mnemonic for (LR) ~ CIA + 4.

bclrl 4,4*cr_field+3

bnulr [cr_field] Branch if not unordered to address in LA.

Use CRO if ccfieid is omitted.

Extended mnemonic for bclr 4,4*cr_field+3

bnulrl Extended mnemonic for (LR) ~ CIA + 4.

bclrI4,4*cr_fleld+3

bsolr [ccfield] Branch if summary overflow to address in LA.

Use CRO if ccfieid is omitted.

Extended mnemonic for

bunlr [ccfield] Branch if unordered to address in LA.

Use CRO if ccfieid is omitted.

Extended mnemonic for bclr 12,4*cr _fleld+3

bunlrl Extended mnemonic for (LR) ~ CIA + 4.

bclrl 12,4*cr _fleld+3

Preliminary Instruction Set 24-33

cmp

Compare

cmp SF, 0, RA, RS

o

31 BF

CO:3 ~ 40

if (RA) < (RS) then

Co

~ 1 if (RA) > (RS) then c1 ~ 1 if (RA)

=

(RS) then c2 ~ 1 c3 ~ XER[SO]

n~SF

CR[CRn] ~ cO:3

RA RB

o

9 11 16 21

The contents of register RA are compared with the contents of register RS using a 32-bit signed compare.

The CR field specified by the SF field is updated to reflect the results of the compare and the value of XER[SO] is placed into the same CR field.

If instruction bit 31 contains 1, the contents of CR[CRO] are undefined.

Registers Altered

• CR[CRn] where

n

is specified by the SF field Invalid Instruction Forms

• Reserved fields Programming Note

The PowerPC Architecture defines this instruction as cmp BF,L,RA,RB, where L selects operand size for 64-bit PowerPC implementations. For all 32-bit PowerPC implementations, L

=

0 is required (L

=

1 is an invalid form); hence for PPC405GP, use of the extended mnemonic cmpw BF,RA,RB is recommended.

Architecture Note

This instruction is part of the PowerPC User Instruction Set Architecture.

Table 24-10. Extended Mnemonics for cmp

Other Registers

Mnemonic Operands Function Altered

cmpw [SF,] RA, RS Compare Word; use CRO if SF is omitted.

Extended mnemonic for cmp BF,O,RA,RB

24-34 PPC405GP User's Manual Preliminary

cmpi SF, 0, RA, 1M

o

11 SF

6 9

CO:3 ~ 40

if (RA) < EXTS(IM) then

Co

~ 1 if (RA) > EXTS(IM) 'then c1 ~ 1 if (RA)

=

EXTS(IM) then c2 ~ 1

C3 ~ XER[SO]

n~BF

CR[CRn] ~ CO:3

cmpi

Compare Immediate

RA 1M

11 16 31

The 1M field is sign-extended to 32 bits. The contents of register RA are compared with the extended 1M field, using a 32-bit signed compare.

Dans le document PowerPC 405GP . Embedded Processor User's Manual (Page 67-94)