UML/MARTE
Logical time and temporal logics: comparing UML MARTE/CCSL and PSL
... The UML Profile for Modeling and Analysis of Real- Time and Embedded systems (MARTE [8]) provides a means to specify several aspects of embedded systems, ranging from large software systems on top of an ...
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Time Properties Verification Framework for UML-MARTE Safety Critical Real-Time Systems
... for UML-MARTE safety critical ...from UML architecture and behaviour models to executable and verifiable models expressed with Time Petri Nets ...
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Natural Interpretation of UML/MARTE Diagrams for System Requirements Specification
... UML extensions, we propose to reuse UML / MARTE constructs to build a set of pre-defined property patterns pertinent for the domain addressed. Another aspect of the related work is the advent of ...
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Multi-View Power Modeling based on UML MARTE and SysML
... on UML MARTE and SysML R´ esum´ e : Le d´eveloppement de SoC implique des activit´es diff´erents, habituellement ma- nipul´ees par des ...sur UML et deux de ses extensions: MARTE et ...
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Combining SystemC, IP-XACT and UML/MARTE in model-based SoC design
... II. O VERVIEW A. SystemC SystemC 1 is a Hardware Description Language, meant to represent circuits and SoCs at various levels of abstraction (in particular at RTL and TLM levels) [5]. Conceived as library extension of C ...
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Natural Interpretation of UML/MARTE Diagrams for System Requirements Specification
... to uml sequence diagrams to model well-known property speci cation ...like marte. Rather than encoding formula with uml extensions, we propose to reuse uml/marte constructs to build a ...
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Automatic Generation of S-LAM Descriptions from UML/MARTE for the DSE of Massively Parallel Embedded Systems
... Merging UML and IP-XACT in MDE-based design flows Several works have shown the importance of integrating IP-XACT while taking ad- vantage from MDE principles in their design ...a MARTE-based method- ology ...
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Clock Constraints in UML/MARTE CCSL
... pro l UML MARTE pour la Modélisation et l'Analyse de systèmes Temps Réel et Embarqués ( TRE ...de MARTE propose un large spectre de nouvelles possibilités nécessaires pour la modélisation de systèmes ...
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Property driven verification framework: application to real time property for UML MARTE software design
... This method was implemented as a prototype toolset that includes five contributions: definition of real-time property specific execution semantics for UML-MARTE architecture and behavior[r] ...
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Dealing with AADL End-to-end Flow Latency with UML MARTE
... upperBound . So object flows can be used to represent AADL communications using either event or event-data ports. UML allows the specification of a customized selection policy to se- lect which one of the tokens ...
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Dealing with AADL end-to-end Flow Latency with UML Marte.
... We exemplify this approach by dealing with the same example as used in AADL [4] to explain the computation of end-to-end flow latencies (and various other related features) in a case of three threads with various rates ...
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Logical time and temporal logics: Comparing UML MARTE/CCSL and PSL
... Unité de recherche INRIA Rennes : IRISA, Campus universitaire de Beaulieu - 35042 Rennes Cedex (France) Unité de recherche INRIA Rhône-Alpes : 655, avenue de l’Europe - 38334 Montbonnot [r] ...
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A Framework to Specify System Requirements using Natural interpretation of UML/MARTE diagrams
... interpret uml diagrams annotated with features from marte to specify system ...a uml based approach to capture properties in a bid to replace temporal logic properties like in ...from marte ...
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Modeling of Immediate vs. Delayed Data Communications: from AADL to UML MARTE
... and MARTE [2] are two such modeling formalisms, in part similar in their ...Conversely, MARTE explicit Time model with powerful logical time constraints allows to specify precisely and thoroughly the ...
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On the semantics of UML/Marte Clock Constraints
... A comprehensive informal description of CCSL has been presented in [2] and a partial formal declarative language- independent description is available in [7]. However, to im- plement CCSL and build a real-time UML ...
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CCSL: specifying clock constraints with UML/MARTE
... models is a problem. OMG Specifications are usually big and are not the right place to put formal specification. Leaving the formal semantics outside the specification leaves the interpretation to tools, possibly having ...
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UML/MARTE CCSL, Signal and Petri nets
... MARTE ( UML Pro le for Modeling and Analysis of Real-Time and Embedded systems) et plus spéci quement son modèle de temps. Ce pro l de temps vise à donner une interprétation précise mais su samment large ...
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Executing AADL models with UML/Marte
... 1. Introduction AADL and M ARTE are two frameworks that support modeling and analysis of embedded systems. Both pro- vide model elements to represent the application (logical, platform-independent solution), the ...
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Event-based vs. Time-Triggered Communications with UML Marte
... The MARTE Time subprofile, inspired from the theory of tag systems [9], provides a set of general mechanisms to define ...use MARTE, as a model architect, to build a partial MoCC suitable for ...in ...
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Polychronous Analysis of Timing Constraints in UML MARTE
... CCSL is a specification language that gives a timed causal- ity semantics to UML models. TimeSquare only supports interactive simulation and should rely on analysis-specific environments to provide advanced ...
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