combined together in strainedsilicon-on-insulator (sSOI) technology. The sSOI substrates are of immense
importance for new generations of CMOS technology. Strainedsilicon layers about 20 nm thick were grown on virtual substrates characterized by a thin SiGe layer having a thickness of 400nm (Fig. 1). The SiGe layers were relaxed by hydrogen or helium implantation and subsequently annealed resulting in threading dislocation densities as low as 110 5 cm -2 and dislocation
The performance improvements in CMOS circuits during the last decades result primarily from reductions in the dimensions of the individual transistors. The smaller device size permits a higher device density that has, for example, resulted in higher clock speeds of logic devices. As device dimensions approach values below 100nm, scaling becomes increasingly difficult. Strain engineering and material innovations have been identified as the main contributors to the continued performance improvement in CMOS devices. One example implemented recently is the silicon-on-insulator (SOI) material. Further improvements of the performance are obtained by an increased carrier mobility which has been reported for devices fabricated on strainedsilicon layers (for example [1-3]). Combining the advantages of SOI and strainedsilicon results in strainedsilicon on insulator (SSOI) substrates connecting the properties of both materials.
For high enough implanted fluences, the majority of platelets and subsequent micro-cracks are parallel to a 共001兲 Si wafer surface and the thickness of the transferred layer can be monitored by varying the beam energy. 1 However, the depth-straggling of the implanted ions results in a depth- distribution of platelets and micro-cracks which, in turn, re- sults in a quite severe roughness and relatively high defec- tivity of the transferred layers. For this reason, ultrathin 共few nanometer thick兲 layers, desirable for developing advanced silicon-on-insulator technologies, are difficult to fabricate us- ing ion implantation and require time-consuming and costly etching steps.
given; the length of the black lines is 100 nm. (b) Three synthetic models, corresponding to three different strain states and their corresponding diffraction patterns. The 2D sample description is shown in the plane indicated in (a) while the diffraction patterns are taken at the same D and q 3 values as the ones of (Figure 2, left column). (c) Intensity integrated along the q 3 direction, for the same D value. The specific features of the calculated diffraction patterns are emphasized by the white arrows and the dotted ellipse. The three strain states are as followed: (Left) The 3D strain- free crystal case. A 2D cut through the 3D amplitude is shown in (a). Note the assymetry in the spatial scale, which is underlined by the white lines, representing a 100 nm length. (Middle) Same calculation, obtained for a strained crystal: a displacement field with a radial symmetry is introduced at the edge of the structure. A 2D cut through the corresponding sample phase is shown at the top. (Right) Same as before with the simultaneous introduction of the displacement field at the edges and at the interface. This last model produces diffraction patterns in good agreement with the experimental ones.
and 36% for n-channel MOSFETs and p-channel MOSFETs, respectively, in sub- 40 nm devices (19). In addition, the gate leakage current was also reduced by 30%. All investigations suggest that the combination of biaxially strained SSOI and uniaxial strain by process-induced stressors is the optimum way for future requirements (2, 9, 18, 19). Uniaxial strained layers: A concept to realize uniaxial strain on wafer level was published in ref. (20). Two wafers were bent over a cylinder thereby creating a curved or bowed wafer with a strained state induced. The bending direction was parallel to . The curved wafers are brought into contact via direct wafer bonding and covalent bonds
Strain engineering has been used in the microelectronics industry since the 90 nm technology node. The main approach currently employed consists of depositing stressor layers on top of transistors. However, as the dimensions of nanowire-based transistors are becoming smaller than the required thickness of such an overlayer, it is difficult to implement this approach into smaller nodes or other nanowire-based architectures. Recently, it was demonstrated that ultrathin, globally strainedsilicon layers (nanomembranes) are the material of choice to generate strained Si nanowires using top-down nanofabrication processes [7, 10, 11]. Interestingly, upon nanoscale patterning of biaxial strained nanomembranes—a crucial step in the fabrication of strained nanowires—the formation of free surfaces induces a local relaxation of strain due to rearrangement of lattice atoms near the newly formed edges [10, 12–16]. In general, the extent of this phenomenon depends on dimension and geometry [12–16]. However, it is widely admitted that due to nanowire geometry (i.e. the high aspect ratio) the post-patterning stress becomes uniaxial, which means that the stress is fully relaxed along the width of the nanowire [7, 11]. However, as demonstrated in this work, this is not the case for nanowires fabricated directly on oxide. More precisely, the nanowire–substrate interface makes the strain redistribution rather complex as one of the four facets is stabilized by the underlying oxide layer. Exploring and understanding this subtle but important phenomenon is crucial for accurate strain nano- engineering and a precise prediction of the performance of strained Si nanowire-based devices. In order to accurately probe the evolution of strain in nanoscale, we have developed a method of high-resolution polarized Raman spectroscopy that allows the analysis of the individual contributions of longitudinal-optical (LO) and transverse-optical (TO) phonons and their profiles in a single nanowire [10
feature of the latest generation of micro- and nanoelec- tronic devices [ 1 ]. Strain dramatically increases the mobil- ity of carriers, either electrons ( 2 for strained Si) or holes ( 10 for strained Ge) [ 2 ], leading to significantly enhanced performances in metal-oxide-semiconductor field-effect transistors (MOSFETs) [ 3 ]. Strain is expected to play a significant role in future devices based on nano- wires [ 4 ] or in optoelectronic components [ 5 ]. Different techniques have been investigated to engineer strain in devices, such as the selective epitaxial growth of Si 1x Ge x in recessed source and drain regions which pro- duces uniaxial compressive stress in the Si channel of very short gate length p type MOSFETs [ 6 ]. The many process- ing routes and sample geometry produce different strain distributions. Performance gains can be understood and modeled only by knowing the exact strain distribution in two dimensions. Measuring strain in the active area of devices has therefore been a major characterization goal over the past few years but has proved difficult to achieve in practice [ 1 , 7 ].
The temperature-dependent behavior of integrated photonic devices is a fundamental issue that affects almost every aspect of circuit and device design and every technological platform. This is particularly true for silicon-on-insulator (SOI) and other semiconductor-based waveguides that exhibit thermo-optic coefficients almost ten times larger than that in silica. This results in large wavelength shifts of the order of several tens of picometers per degree in the optical communication bands and causes severe distortions of the device responses [1, 2]. In order to avoid or limit the use of energy-hungry active temperature control, several solutions have been proposed in the literature to mitigate the effect of temperature fluctuations by designing athermal devices. For wavelength filtering and routing, arrayed waveguide grating (AWG), lattice filter and echelle grating are the main device options, each with its advantages and shortcomings [3–6]. For AWGs and lattice filters in which the phase accumulation takes place in wire or ridge waveguides, athermal behavior may be achieved by using a material with a negative thermo-optic coefficient as the waveguide top cladding to counterbalance the positive coefficient of the core and substrates. Exploited materials include resins , sol-gel materials , polymers [9, 10], and amorphous titanium dioxide . In echelle gratings where the phase accumalation is in the slab free-propagation region, a similair method has been applied to devices based on III-V semiconductors . However, this method is ineffective in echelles based on a submicron silicon platform particularly for devices operating in the transverse electric (TE) polarization since the modal overlap with the cladding material is very small. Additionally, the use of these materials requires a substantial change to the standard SOI photonics fabrication processes, which may hinder their adoption outside of research scenarios. On the other hand, it is possible to utilize the dimensional dependece of the waveguide temperature sensitivity to engineer the overall device thermo-optic behavior [13, 14], and an athermal lattice filter has been reported exploiting this technique .
Selective CdTe (3600 sec) 615nm 95nm
The vertical dimension of the silicon nanopillar on the substrate which is indicative of the thickness of the silicon island is ~37nm. This is due to the over etching (~17nm into the silicon-dioxide) in the pattern transfer process with reactive ion etch because the chemistry used also etches silicon dioxide. The lateral growth rate of CdTe on the silicon islands is between 0.8-2.0Å/s while the vertical growth rate is between 0.1-0.3 Å/s which indicates a higher lateral growth rate versus vertical growth rate. This is probably due to the high surface area of the silicon nanoislands compared to the height that enhances the nucleation and growth of CdTe laterally. However, a clearly defined step shown by the AFM profile between the CdTe grown on the silicon nanopillars and the underlying silicon dioxide mask indicates that CdTe is growing selectively on the silicon islands.
BASE DE SOI
The simulation results are obtained using Taurus-Medici from Synopsys, a commercially available finite element semiconductor simulation program [9, 10]. Taurus Medici is a powerful 2D device simulator commonly used to simulate the current-voltage characteristics of various semiconductor devices. The first step for each simulation consists in drawing the different regions of the device with their known electrical characteristics (metal/semiconductor/insulator, doping level, etc.). The different electrical properties (charge density, electric field, potential, etc.) are obtained at each point of a calculation mesh specially adapted to the particular geometry of the device. The simulation program allows optimizing the mesh after an initial simulation: enhanced precision is obtained by increasing the number of points in regions where the electrical quantities vary rapidly in the x-y plane. Finally, notice that we have used a nonlinear expression for the hole mobility [11, 12, 13] in the channel of our SSD device since the electric field gets around 10 kV/cm, which is the onset of hot carrier effects in silicon , for only 1 V bias on a 1 µm-long channel.
3. Experimental demonstration
Samples were fabricated from commercial SOI substrates with 0.22 µ m thick silicon and 3
µ m thick BOX layers. The backside of the wafer was polished and coated with a 9-layer AR coating consisting of alternating films of SiO 2 and Nb 2 O 5 to minimize substrate Fabry-Pérot fringes in the reflectivity spectrum of p-polarized light in a wavelength band of λ = 1.5-1.55 µm. The SiO 2 gratings with a thickness of 180 nm and a pitch of 1.24 µm were fabricated by electron beam lithography using hydrogen silsesquioxane (HSQ) resist, which forms SiO 2 upon electron beam exposure. The grating size was 5 mm × 7 mm. For mass production the grating could be produced by other standard lithography tools, such as a UV stepper, or by holography. Figure 5a shows a photograph of a chip with two gratings. A scanning electron microscope (SEM) image of a fabricated HSQ grating is shown in Fig. 5b.
III. OPTICAL MEASUREMENTS
First, linear optical characterization was carried out in order to evaluate the linear propagation losses of the waveguides. The linear propagation loss measurements were done using an automated prober station across the whole 200-mm wafer, and light was injected via 1-dimensional grating couplers (7 dB/coupler). We derived average propagation losses of 0.3 dB/cm at 1550 nm for two-mode waveguides with cross-section dimensions (w × h) of 1400 nm × 730 nm and 1.7 dB/cm for normal dispersion single-mode waveguides with cross-section dimensions of 750 nm × 730 nm. The total insertion loss of several waveguides with different lengths was measured and the propagation losses of the fundamental transverse electric polarized mode was inferred from the slope of the insertion loss as a function of the waveguide length. These results were obtained on randomly chosen dies and wafers to ensure the film to be crack-free everywhere on each 200-mm wafers. The measurements were averaged across 20 dies of different wafers. As shown in the next section, these amount of losses are sufficiently low for enabling Kerr-based self-phase modulation (SPM) in our silicon nitride nanowires under reasonable input peak powers.
Figure 8. Shooting method results for calculating the bound exciton energy in a double well Ge-SiGe/Si layered system. The left panel depicts the result for a Si 0.85 Ge 0.15
quantum well 5 nm thick where the exciton energy obtained is approximately 1054 meV. On the right, a 2.5 nm strained Ge NC has been added. The lowest bound exciton energy in that case is 924 meV. The background energy is that of substrate bound excitons in silicon (1150 meV). The well structure shown illustrates reductions in that energy due to the presence of Ge in the SiGe alloy layer and/or in the Ge NC. The horizontal lines in the quantum wells represent the energy solutions for which the wavefunctions are well behaved well away from the quantum well in the growth direction.
substrate, instead of silicon. The reactants gases are silane and propane mixed in a pure hydrogen carrier gas. Wafers are placed on a SiC coated-susceptor. Growth is undergone at atmospheric pressure and typical growth temperature is 1450°C. Growth rate, doping level and morphology of the epitaxy were compared to those obtained on full 4H-SiC wafers. Prior to growth a slight H 2 etch was performed.
Label-free evanescent field sensors made of silicon- on-insulator (SOI) photonic waveguides with submicrom- eter dimensions have seen rapid development in recent years [ 1 – 5 ]. Because of the high refractive index of silicon, the optical modal field is strongly localized near the waveguide surface, resulting in a high response to surface perturbations, particularly when operating in the TM mode [ 2 ]. Highly compact SOI sensor arrays are readily manufacturable using standard complementary metal- oxide semiconductor processing. The use of ring resona- tors further amplifies the sensor response, because the light circulating in the ring effectively interacts with the same molecules many times [ 2 , 6 , 7 ]. These properties make Si wire resonators one of the most promising sensor platforms.
Samples were fabricated using SOI substrates with a
0.26 μm thick silicon and a 2 μm thick buried oxide layer.
Waveguides with the polarization rotator structure were defined in a single patterning step by electron beam litho- graphy with high contrast hydrogen silsesquioxane (HSQ) resist. Inductively coupled plasma reactive ion
FIG. 7. (a) Magnetic field dependence of the dynamics of the circular polarization degree (ρ circ ) measured at a lattice temperature of 7 K
and for a laser excitation energy of 1.165 eV and P AV = 10 mW. Experimental data obtained by applying a magnetic field strength of 20.6 (blue
dots), 32.3 (red dots), and 53.5 mT (black dots) and the corresponding fits (solid lines) have been shifted for clarity. ρ circ oscillates around zero
and the quantum beatings can be interpreted in terms of the Larmor precession of the electron spins due to the presence of an external magnetic field perpendicular to the quantization axis (Voigt configuration, see inset). (b) Dependence of the Larmor frequency ω on the magnetic field strength for a fully strained Ge 0.95 Sn 0.05 layer epitaxially deposited on a Ge buffered Si substrate. The dashed line corresponds to the linear
structures frustrate diffraction and behave like a homogeneous medium (metamaterial) provided the periodicity does not satisfy a Bragg condition for coupling to other confined or radiative modes [23,24].
Subwavelength gratings have been extensively used for antireflective coatings on bulk optical surfaces . Originally implemented as planar mirrors , subwavelength gratings have been used as efficient fibre-chip couplers , off-plane fibre couplers [28,29], antireflective gradient index structures and interference mirrors [30,31]. Subwavelength gratings were originally proposed as silicon waveguide cores  and as a composite waveguide cladding . Recently, subwavelength gratings have been experimentally demonstrated as efficient crossings  and adiabatic mode transformers and fibre-chip couplers .
The temperature dependence of the sheet resistance down to 360 mK for the two different aluminum-doped 4H-SiC samples is shown in Figs. 2共b兲 and 2共c兲 , respec- tively. One clearly sees that sample VLS93 is following an insulating behavior while sample VLS98 follows a metallic behavior d /dT⬍0. Assuming a doping efficiency of 100%, the critical concentration of aluminum for the doping- induced metal-insulator transition lies in the range between 3.4 and 8.7⫻10 20 cm −3 as determined from SIMS. In Fig.