Hardware simulator

Received December 4, 2012 Abstract A wireless communication system can be tested either in actual conditions or by a hardware simulator reproducing actual conditions. With a hardware simulator it is possible to freely simulate a desired type of a radio channel and making it possible to test “on table” mobile radio equipment. This paper presents an architecture for the digital block of a hardware simulator of MIMO propagation channels. This simulator can be used for LTE and WLAN IEEE 802.11ac applications, in indoor and outdoor environments. However, in this paper, specific architecture of the digital block of the simulator is presented to characterize a scenario form indoor to outdoor using TGn channel models. The switching between each environment in the scenario must be made in a continuous manner. Therefore, an Algorithm is designed to pass from a considered impulse response in the environment to another in other environment. The architecture of the digital block of the hardware simulator is presented and implemented on a Xilinx Virtex-IV FPGA. Moreover, the impulse responses are transferred into the simulator. The accuracy, the occupation on the FPGA and the latency of the architecture are analyzed.

Keywords: Hardware simulator; MIMO radio channel; FPGA; 802.11ac signal; Time-varying TGn channel models 1. Introduction Multiple-Input Multiple-Output (MIMO) systems make use of antenna arrays simultaneously at both transmitter and receiver to improve the channel capacity and the sys- tem performance. Because the transmitted electromagnetic waves interact with the propagation environment (in- door/outdoor), it is necessary to take into account the main propagation parameters for the design of the future com- munication systems.

[9] P. Almers, E. Bonek et al., “Survery of channel and Radio propagation models for wireless MIMO systems”, EURASIP Journal on Wireless Communications and Networking, Article ID 19070, 2007. [10] L. Schumacher, K. I. Pedersen and P.E. Mogensen, “From antenna spacings to theoretical capacities – guidelines for simulating MIMO systems”, in Proc. PIMRC Conf., vol. 2, pp. 587-592, Sep. 2002. [11] S. Picol, G. Zaharia, D. Houzet and G. El Zein, “Hardware simulator for

A wireless communication system can be tested either in actual conditions or with a hardware simulator reproducing actual conditions. With a hardware simulator it is possible to freely simulate a desired radio channel and making it possible to test “on table” mobile radio equipments. This paper presents new architectures for the digital block of a hardware simulator of MIMO propagation channels. This simulator can be used for LTE and WLAN IEEE 802.11ac applications, in indoor and outdoor environments. However, in this paper, specific architectures of the digital block of the simulator for shipboard environment are presented. A hardware simulator must reproduce the behavior of the radio propagation channel. Thus, a measurements campaign has been conducted to obtain the impulse responses of the shipboard channel using a channel sounder designed and realized at IETR. After the presentation of the channel sounder, the channel impulse responses are described. Then, the new architectures of the digital block of the hardware simulator, implemented on a Xilinx Virtex-IV FPGA are presented. Moreover, the measured impulse responses are implemented in the simulator. The accuracy, the occupation on the FPGA and the latency of the architectures are analyzed.

bachir.habib@insa-rennes.fr Abstract—A hardware simulator facilitates the test and validation cycles by replicating channel artifacts in a controllable and repeatable laboratory environment. Thus, it makes possible to ensure the same test conditions in order to compare the performance of various equipments. This paper presents new frequency domain and time domain architectures of the digital block of a hardware simulator of MIMO propagation channels. The two architectures are tested with LTE standard, in outdoor environment, using time-varying channel models. After the description of the general characteristics of the hardware simulator, the new architectures of the digital block are presented and designed on a Xilinx Virtex-IV FPGA. Their accuracy and latency are analyzed. The result shows that the architectures produce low occupation on the FPGA and decrease the error at the output. Therefore, they present the best solution to simulate systems with high MIMO arrays order.

The channel models can be obtained from standard models, as the TGn 802.11n [6] and the LTE models [7], or from measurements conducted with the MIMO channel sounder designed and realized at IETR [8]. In the MIMO context, little experimental results have been obtained regarding time- variations, partly due to several limitations of the channel sounding equipment [9]. However, theoretical models of time- varying channels can be obtained using Rayleigh fading [10]. At IETR, several architectures of the digital block of a hardware simulator have been studied [11, 12]. Typically, radio propagation channels are simulated using finite impulse response (FIR) filters, as in [11, 12, 14]. The Fast Fourier Transform (FFT) modules can also be used to obtain an algebraic product, as in [11, 13]. In [15], a method fitting the cross-correlation matrix to the estimated matrix of a real-world channel was presented. This solution shows that the error can be important.

Abstract This paper presents a new frequency domain architecture for the digital block of a hardware simulator of MIMO propagation channels. This simulator can be used for LTE and WLAN IEEE 802.11ac applications, in indoor and outdoor environments. It accepts signals in streaming mode. A hardware simulator must reproduce the behavior of the radio propa- gation channel, thus making it possible to test “on table” the mobile radio equipments. The advantages are: low cost, short test duration, possibility to ensure the same test conditions in order to compare the performance of various equipments. After the presentation of the general characteristics of the hardware simulator, the new architecture of the digital block is presented and designed on a Xilinx Virtex-IV FPGA. It is tested with time-varying 3GPP TR 36.803 channel model EVA and TGn channel model E. Finally, its accuracy is analyzed .

At IETR, several architectures of the digital block of a hardware simulator have been studied [8]. Typically, radio propagation channels are simulated using Finite Impulse Response (FIR) filters, as in [8, 9]. The Fast Fourier Transform (FFT) modules with algebraic product can also be used, as in [8, 10]. However, these considered frequency architectures operate correctly for signals not exceeding the FFT size. Thus, new frequency architecture avoiding this limitation has been presented and tested [11, 12]. Moreover, [12, 13] show that the time domain architecture is better in terms of occupation on FPGA, output error and latency.

measurements by using a time domain MIMO channel sounder designed and realized at IETR [10], [11], as shown in Fig. 1. Figure 1. MIMO channel sounder: receiver (left) and transmitter (right). At IETR, several architectures of the digital block of a hardware simulator have been studied, in time and frequency domains [12], [13]. Moreover, a new method based on determining the parameters of the simulator by fitting the space time-frequency cross-correlation matrix to the estimated matrix of a real-world channel was presented in [14]. This solution shows that the error can be important. Typically, wireless channels are commonly simulated using finite impulse response (FIR) filters, as in [13], [15] and [16]. However, for a hardware implementation, it is easier to use the FFT (Fast Fourier Transform) module to obtain an algebraic product. Thus, frequency architectures are proposed, as in [12] and [14]. The previous considered frequency architectures operate correctly only for signals with a number of samples not exceeding the size of the FFT. Therefore, in this paper, a new frequency domain architecture avoiding this limitation, and a new time domain architecture are both tested with time-varying TGn 802.11n channel model B.

Keywords: Hardware simulator; FPGA; MIMO radio channel; 802.11ac; LTE; 1. Introduction Tests of a radio communication system, conducted under actual conditions are difficult, because tests taking place on outdoor, for instance, are affected by random movements or even by the weather. Thus, to evaluate the performance of the recent communication systems, a channel hardware simulator is considered. With hardware simulators, it is possible to very freely simulate desired types of radio channels. Moreover, it provides the necessary processing speed and real time performance, as well as the possibility to repeat the tests for any Multiple-Input Multiple-Output (MIMO) system.

Institute of Electronics and Telecommunications of Rennes, IETR, UMR CNRS 6164, Rennes, France Email adress: Bachir.habib@insa-rennes.fr (B. Habib) Abstract: A hardware simulator facilitates the test and validation cycles by replicating channel artifacts in a controllable and repeatable laboratory environment. This paper presents an overview of the digital block architectures of Multiple-Input Multiple-Output (MIMO) hardware simulators. First, the simple frequency architecture is presented and analyzed. Then, an improved frequency architecture, which works for streaming mode input signals, is considered. After, the time domain architecture is described and analyzed. The architectures of the digital block are presented and designed on a Xilinx Virtex-IV Field Programmable Gate Array (FPGA). Their accuracy, occupation on the FPGA and latencies are analyzed using Wireless Local Area Networks (WLAN) 802.11ac and Long Term Evolution System (LTE) signals. The frequency and the time approaches are compared and discussed, for indoor (using TGn channel models) and outdoor (using 3GPP-LTE channel models) environments. It is shown that the time domain architecture present the best solution for the design of the architecture of the hardware simulator digital block. Finally, a 2×2 MIMO time domain architecture is described and simulated with input signal that respects the bandwidth of the considered standards.

Keywords— Hardware simulator; FPGA; MIMO channels; LTE; WLAN 802.11 ac; implementation algorithm I. I NTRODUCTION Multiple-Input Multiple-Output (MIMO) systems offer significant increases in data throughput and link range without additional bandwidth or increased transmit power. Several recent publications have shown an increased MIMO order such as 8×8 and higher [1]. This is made possible by advances at all levels of the simulator platforms [2].

Brette et al. [8] surveyed and discussed the existing work on SNN simulation in 2007. All the simulators discussed in this report as well as the more recent Brian [9] target the simulation of biological SNN. More recently, Bichler et al. [10] proposed Xnet, a C++ event-driven simulator dedicated to the simulation of hardware SNN. In our work, we share the goals of Xnet: “intermediate modeling level, between low- level hardware description languages and high-level neural networks simulators used primarily in neurosciences”, and “the integration of synaptic memristive device modeling, hardware constraints and any custom features required for the targeted application”. In addition to these goals, we put an emphasis on flexibility and usability to allow the study of various kinds of hardware designs (possibly by other researchers than us),

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4 1.3 Objectives of the Current Work The Boolean satisfiability problem is inherently massively parallel. As detailed below, verifying that a particular problem clause is satisfied can be done independently of the verification of all other remaining clauses with the only limiting factor being the number of evaluation units available. As such, it is natural to assume that SAT would map very well to FPGAs given their ability to perform many computations in parallel. However, an FPGA board has several limitations and restrictions that impact the amount of parallelism extracted when mapping a problem. Examples of this include the amount of on and off-chip memories that are available, the maximal frequencies at which reading from these memories is possible as well as their number of physical read ports. Thus, one of our principal objectives has been to explore and evaluate the impact of FPGA on-chip memory on SAT resolution as well as the different trade-offs necessary to garner maximal parallelism for execution speed. To characterize these issues, a solver prototype was implemented using VHDL and targeted to an Altera Cyclone II DE2-70 FPGA board. In addition, a software counterpart with an identical execution model was also developed and used to simulate the hardware on problem instances.

Programming with hardware/software functions 3 1 Introduction FPGAs (Field Programmable Gate Arrays) are a promising class of circuits for building the next genera- tion of computers. Performance-wise, they are one or two generations behind the most advanced general purpose processors. However, they are much more flexible, since dedicated hardware can be synthesized on them for performing specific tasks, whose execution is orders of magnitudes faster than functionally- equivalent software running on a standard processor. This opens the way for new hardware architectures, consisting of softcore processors co-existing with dedicated hardware accelerators. With such an archi- tecture, the programmer can choose between calling software functions or running dedicated Intellectual Properties (IPs) for implementing a given functionality of her program. Such choices are guided by the need to achieve speed (IPs are much faster than software code) while taking into account the intrinsic limitations of the hardware (not all functionalities of a program can be implemented in hardware due to space limitations).

Cette dernière contribution fait l'objet d'une attention particulière an de surmonter cer- tains problèmes de conception qui limitaient auparavant la faisabilité de l'approche couplée RNS/NTT pour des grands paramètres. En particulier, nous proposons une solution pour précalculer localement les valeurs nécessaires aux opérations de NTT, sans impact sur les per- formances. Ceci est obtenu grâce à deux contributions : la conception d'un circuit de NTT changeant ses corps nis de dénition à la volée, et la conception d'un générateur de facteur de rotation pour les NTT sur les diérents corps nis. Enn, pour répondre à la question de la grande variation des paramétrages en fonction des diérentes applications du chire- ment homomorphe, la génération automatique des descriptions HDL (Hardware Description Language) de nos circuits a été explorée.

ea h EU to every other EU in the LA, thanks to the distributors. We have hosen not to have any dire t data path between EUs in the same node to simplify the hardware 5 . Hen e if a µ op takes as input a data produ ed by another µ op in the same node but on a dierent EU, this data must travel around the lane to rea h the onsumer µ op. If a short ommuni ation laten y between 2 µ ops is needed for performan e, we must try to map these 2 µ ops on the same EU, so that the onsumer µ ops an at h the data from the LEQ top. If we nd during loop building that the loop annot be exe uted by the LA, the loop keeps exe uting

We used STM from the former category, to instrument pro- grams without needing to synchronize and compute a times- tamp when recording a tracepoint. We showed a 10 times decrease in time overhead when tracing a user-space pro- gram on a Pandaboard. We then studied program tracers, i.e. hardware modules to record the flow of executed instruc- tions. These do not provide the same information as tracers do but can be suited for tracing, depending on one’s needs. On ARM platforms, ETM offers good efficiency because of its trace compression and triggering capabilities: tracing a program takes 30% to 50% less time when hardware-assisted. On Intel x86, the BTS registers are not adapted to event recording, mainly because they lack automatic enabling/dis- abling with address matching and trace compression. How- ever, they can be used for this purpose by tracing every branch. Using BTS for recording user-space tracepoints on an Intel Core i7-3770 is 30% to 60% slower than using LT-

In proton therapy, mainly two techniques can be used: the scattering and the spot scanning. However, we focused on the spot scanning delivery strategy. It consists of a thin proton beam scanned across the tumor volume. It provides a good conformity to complex tumor shapes, which reduces toxicity to healthy tissues. However, this accuracy is greatly degraded when the patient moves during the treatment, which is unavoidable since the patient is alive and the lungs and other organs (e.g., the heart) are constantly in motion. Such motions are called intra-fraction motions. The problem of intra-fraction motion has some impact on the overall treatment. The improvement of the treatment’s ro- bustness to motion requires the capacity of dose computation on dynamic patient dataset (i.e., a 4-dimensions (4D) treatment planning). Studies are often conducted with the researcher’s in-house treatment planning system or an expensive clinical treatment plan- ning system. The limited availability of 4D treatment planning system makes it difficult to study this subject by a broader category of researchers. This is why we developed an open-source 4D dose computation and evaluation software, MSPT (Motion Simulator for Proton Therapy). The main interest of this simulator lies in the ability to render the impact of a predicted patient motion on a prescribed treatment plan. This capa- bility makes it an innovative research tool to evaluate and compare different methods of motion management or mitigation. While the main objective of MSPT is to quantify the treatment degradation induced by particular motions, it can also be used to elaborate some compensation methods to improve treatment robustness such as the one we propose.