• DC to 1.0 MHz Operation at VDD = 5 V

(1)

The MC14500B Industrial Control Unit (ICU) is a single–bit CMOS processor. The ICU is designed for use in systems requiring decisions based on successive single–bit information. An external ROM stores the control program. With a program counter (and output latches and input multiplexers, if required) the ICU in a system forms a stored–program controller that replaces combinatorial logic. Applications include relay logic processing, serial data manipulation and control. The ICU also may control an MPU or be controlled by an MPU.

• 16 Instructions

• DC to 1.0 MHz Operation at VDD = 5 V

• On–Chip Clock (Oscillator)

• Executes One Instruction per Clock Cycle

• 3 to 18 V Operation

• Low Quiescent Current Characteristic of CMOS Devices

• Capable of Driving One Low–Power Schottky Load or Two Low–Power TTL Loads over Full Temperature Range

BLOCK DIAGRAM

DATA

X1 X2 I0 I1 I2 I3 RST

3 14 13 7 6 5 4 1

INST REG OSC D C IEN

LU

D C RESULT REG. (RR)

MUX D C

16 2

8 WRITE

VDD VSS

15 12 11 10 9

RR JMP RTN FLAG O FLAG F + V

OEN STOC

STO

X1 — OSCILLATOR OUTPUT X2 — OSCILLATOR INPUT

SEMICONDUCTOR TECHNICAL DATA

REV 3 1/94

L SUFFIX CERAMIC CASE 620

ORDERING INFORMATION

TA = – 55 ° to 125°C for all packages.

P SUFFIX PLASTIC CASE 648

DW SUFFIX SOIC CASE 751G

PIN ASSIGNMENT MC14XXXBCP Plastic

MC14XXXBCL Ceramic

MC14XXXBDW SOIC

13 14 15 16

9 10 11 12 5

4 3 2 1

8 7 6

JMP X2 X1 VDD

FLAG F FLAG O RTN I3

DATA WRITE RST

VSS I0 I1 I2

RR

(2)

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

MAXIMUM RATINGS* (Voltages Referenced to VSS)

ÎÎÎÎ

Symbol

ÎÎÎÎÎÎÎÎÎÎÎ

Parameter

ÎÎÎÎÎÎ

Value

ÎÎÎ

Unit

ÎÎÎÎ

VDD

DC Supply Voltage

ÎÎÎÎÎÎ

– 0.5 to + 18.0

ÎÎÎ

V

ÎÎÎÎ

Vin, Vout

Input or Output Voltage (DC or Transient)

ÎÎÎÎÎÎ

– 0.5 to VDD + 0.5

ÎÎÎ

V

ÎÎÎÎ

Iin, Iout

Input or Output Current (DC or Transient), per Pin

ÎÎÎÎÎÎ

± 10

ÎÎÎ

mA

ÎÎÎÎ

PD

Power Dissipation, per Package†

ÎÎÎÎÎÎ

500

ÎÎÎ

mW

ÎÎÎÎ

Tstg

Storage Temperature

ÎÎÎÎÎÎ

– 65 to + 150

ÎÎÎ

_ C

ÎÎÎÎ

TL

Lead Temperature (8–Second Soldering)

ÎÎÎÎÎÎ

260

ÎÎÎ

_ C

* Maximum Ratings are those values beyond which damage to the device may occur.

†Temperature Derating:

Plastic “P and D/DW” Packages: – 7.0 mW/ _ C From 65 _ C To 125 _ C Ceramic “L” Packages: – 12 mW/ _ C From 100 _ C To 125 _ C

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS)

ÎÎÎÎÎÎÎÎÎÎ

Characteristic

ÎÎÎÎ

Symbol

ÎÎÎ

VDD Vdc

ÎÎÎÎÎÎ

– 55 _ C

ÎÎÎÎÎÎÎÎ

25 _ C

ÎÎÎÎÎÎ

125 _ C

ÎÎÎ

Unit

Characteristic

ÎÎÎÎ

Symbol

ÎÎÎ

VDD Vdc

ÎÎÎ

Min

ÎÎÎÎ

Max

ÎÎÎ

Min

ÎÎÎÎ

Typ #

ÎÎÎ

Max

ÎÎÎÎ

Min

ÎÎÎ

Max

ÎÎÎ

Unit

Output Voltage “0” Level Vin = VDD or 0

“1” Level Vin = 0 or VDD

ÎÎÎÎ

VOL

ÎÎÎ

5.0 10 15

ÎÎÎ

—

ÎÎÎÎ

0.05 0.05 0.05

ÎÎÎ

—

ÎÎÎÎ

0 0 0

ÎÎÎ

0.05 0.05 0.05

ÎÎÎÎ

—

ÎÎÎ

0.05 0.05 0.05

ÎÎÎ

Vdc

“1” Level Vin = 0 or VDD

ÎÎÎÎ

VOH

ÎÎÎ

5.0 10 15

ÎÎÎ

4.95 9.95 14.95

ÎÎÎÎ

—

ÎÎÎ

4.95 9.95 14.95

ÎÎÎÎ

5.0 10 15

ÎÎÎ

—

ÎÎÎÎ

4.95 9.95 14.95

ÎÎÎ

—

ÎÎÎ

Vdc

Input Voltage “0” Level RST, D, X2

(VO = 4.5 or 0.5 Vdc) (VO = 9.0 or 1.0 Vdc) (VO = 13.5 or 1.5 Vdc)

“1” Level (VO = 0.5 or 4.5 Vdc)

(VO = 1.0 or 9.0 Vdc) (VO = 1.5 or 13.5 Vdc)

ÎÎÎÎ

VIL

ÎÎÎ

5.0 10 15

ÎÎÎ

—

ÎÎÎÎ

1.5 3.0 4.0

ÎÎÎ

—

ÎÎÎÎ

2.25 4.50 6.75

ÎÎÎ

1.5 3.0 4.0

ÎÎÎÎ

—

ÎÎÎ

1.5 3.0 4.0

ÎÎÎ

Vdc

“1” Level (VO = 0.5 or 4.5 Vdc)

(VO = 1.0 or 9.0 Vdc) (VO = 1.5 or 13.5 Vdc)

ÎÎÎÎ

VIH

ÎÎÎ

5.0 10 15

ÎÎÎ

3.5 7.0 11

ÎÎÎÎ

—

ÎÎÎ

3.5 7.0 11

ÎÎÎÎ

2.75 5.50 8.25

ÎÎÎ

—

ÎÎÎÎ

3.5 7.0 11

ÎÎÎ

—

ÎÎÎ

Vdc

Input Voltage # “0” Level I0, I1, I2, I3

(VO = 4.5 or 0.5 Vdc) (VO = 9.0 or 1.0 Vdc) (VO = 13.5 or 1.5 Vdc)

“1” Level (VO = 0.5 or 4.5 Vdc)

(VO = 1.0 or 9.0 Vdc) (VO = 1.5 or 13.5 Vdc)

ÎÎÎÎ

VIL

ÎÎÎ

5.0 10 15

ÎÎÎ

—

ÎÎÎÎ

0.8 1.6 2.4

ÎÎÎ

—

ÎÎÎÎ

1.1 2.2 3.4

ÎÎÎ

0.8 1.6 2.4

ÎÎÎÎ

—

ÎÎÎ

0.8 1.6 2.4

ÎÎÎ

Vdc

“1” Level (VO = 0.5 or 4.5 Vdc)

(VO = 1.0 or 9.0 Vdc) (VO = 1.5 or 13.5 Vdc)

ÎÎÎÎ

VIH

ÎÎÎ

5.0 10 15

ÎÎÎ

2.0 6.0 10

ÎÎÎÎ

—

ÎÎÎ

2.0 6.0 10

ÎÎÎÎ

1.9 3.1 4.3

ÎÎÎ

—

ÎÎÎÎ

2.0 6.0 10

ÎÎÎ

—

ÎÎÎ

Vdc

Output Drive Current Source Data, Write

(VOH = 4.6 Vdc) (VOH = 9.5 Vdc) (VOH = 13.5 Vdc)

ÎÎÎÎ

IOH

ÎÎÎ

5.0 10 15

ÎÎÎ

– 1.2 – 3.6 – 7.2

ÎÎÎÎ

—

ÎÎÎ

– 1.0 – 3.0 – 6.0

ÎÎÎÎ

– 2.0 – 6.0 – 12

ÎÎÎ

—

ÎÎÎÎ

– 0.7 – 2.1 – 4.2

ÎÎÎ

—

ÎÎÎ

mAdc

(VOL = 0.4 Vdc) Sink (VOL = 0.5 Vdc)

(VOL = 1.5 Vdc)

ÎÎÎÎ

IOL

ÎÎÎ

5.0 10 15

ÎÎÎ

1.9 3.6 7.2

ÎÎÎÎ

—

ÎÎÎ

1.6 3.0 6.0

ÎÎÎÎ

3.2 6.0 12

ÎÎÎ

—

ÎÎÎÎ

1.1 2.1 4.2

ÎÎÎ

—

ÎÎÎ

mAdc

Output Drive Current Source Other Outputs

(VOH = 2.5 Vdc) (VOH = 4.6 Vdc) (VOH = 9.5 Vdc) (VOH = 13.5 Vdc)

ÎÎÎÎ

IOH

ÎÎÎ

5.0 5.0 10 15

ÎÎÎ

– 3.0 – 0.64

– 1.6 – 4.2

ÎÎÎÎ

—

ÎÎÎ

– 2.4 – 0.51

– 1.3 – 3.4

ÎÎÎÎ

– 4.2 – 0.88 – 2.25 – 8.8

ÎÎÎ

—

ÎÎÎÎ

– 1.7 – 0.36

– 0.9 – 2.4

ÎÎÎ

—

ÎÎÎ

mAdc

(VOL = 0.4 Vdc) Sink (VOL = 0.5 Vdc)

(VOL = 1.5 Vdc)

ÎÎÎÎ

IOL

ÎÎÎ

5.0 10 15

ÎÎÎ

0.64 1.6 4.2

ÎÎÎÎ

—

ÎÎÎ

0.51 1.3 3.4

ÎÎÎÎ

0.88 2.25 8.8

ÎÎÎ

—

ÎÎÎÎ

0.36 0.9 2.4

ÎÎÎ

—

ÎÎÎ

mAdc

#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.

This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, pre- cautions must be taken to avoid applications of any voltage higher than maximum rated volt- ages to this high–impedance circuit. For proper operation, Vin and Vout should be constrained to the range VSS v (Vin or Vout) v VDD.

Unused inputs must always be tied to an

appropriate logic voltage level (e.g., either VSS

or VDD). Unused outputs must be left open.

(3)

ELECTRICAL CHARACTERISTICS — continued (Voltages Referenced to VSS)

Characteristic

ÎÎÎÎ

Symbol

ÎÎÎ

VDD Vdc

ÎÎÎÎÎÎ

–55 _ C

ÎÎÎÎÎÎÎÎ

25 _ C

ÎÎÎÎÎÎ

125 _ C

ÎÎÎ

Unit

Characteristic

ÎÎÎÎ

Symbol

ÎÎÎ

VDD Vdc

ÎÎÎ

Min

ÎÎÎÎ

Max

ÎÎÎ

Min

ÎÎÎÎ

Typ #

ÎÎÎ

Max

ÎÎÎÎ

Min

ÎÎÎ

Max

ÎÎÎ

Unit

Input Current, RST

ÎÎÎÎ

Iin

ÎÎÎ

15

ÎÎÎ

25

ÎÎÎÎ

—

ÎÎÎ

—

ÎÎÎÎ

150

ÎÎÎ

—

ÎÎÎÎ

—

ÎÎÎ

250

ÎÎÎ

µAdc

Input Current

ÎÎÎÎ

Iin

ÎÎÎ

15

ÎÎÎ

—

ÎÎÎÎ

± 0.1

ÎÎÎ

—

ÎÎÎÎ

± 0.00001

ÎÎÎ

± 0.1

ÎÎÎÎ

—

ÎÎÎ

± 1.0

ÎÎÎ

µ Adc

Input Capacitance (Data)

ÎÎÎÎ

Cin

ÎÎÎ

—

ÎÎÎ

—

ÎÎÎÎ

—

ÎÎÎ

—

ÎÎÎÎ

15

ÎÎÎ

—

ÎÎÎÎ

—

ÎÎÎ

—

ÎÎÎ

pF

Input Capacitance (All Other Inputs)

ÎÎÎÎ

Cin

ÎÎÎ

—

ÎÎÎ

—

ÎÎÎÎ

—

ÎÎÎ

—

ÎÎÎÎ

5.0

ÎÎÎ

7.5

ÎÎÎÎ

—

ÎÎÎ

—

ÎÎÎ

pF

Quiescent Current

(Per Package) Iout = 0 µA, Vin = 0 or VDD

ÎÎÎÎ

IDD

ÎÎÎ

5.0 10 15

ÎÎÎ

—

ÎÎÎÎ

5.0 10 20

ÎÎÎ

—

ÎÎÎÎ

0.005 0.010 0.015

ÎÎÎ

5.0 10 20

ÎÎÎÎ

—

ÎÎÎ

150 300 600

ÎÎÎ

µAdc

**Total Supply Current at an External Load Capacitance (CL) on All Outputs

ÎÎÎÎ

IT

ÎÎÎ

—

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

IT = (1.5 µA/kHz) f + IDD IT = (3.0 µA/kHz) f + IDD IT = (4.5 µA/kHz) f + IDD

ÎÎÎ

µ Adc

** The formulas given are for the typical characteristics only at 25 _ C.

#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.

SWITCHING CHARACTERISTICS* (TA = 25_C; tr = tf = 20 ns for X and I inputs; CL = 50 pF for JMP, X1, RR, Flag O, Flag F;

CL = 130 pF + 1 TTL load for Data and Write.)

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Characteristic

ÎÎÎÎ

Symbol

ÎÎÎÎÎ

VDD Vdc

All Types

ÎÎÎ

Unit

Characteristic

ÎÎÎÎ

Symbol

ÎÎÎÎÎ

VDD Vdc

ÎÎÎÎ

Min

ÎÎÎÎ

Typ #

ÎÎÎÎ

Max

ÎÎÎ

Unit

Propagation Delay Time, X1 to RR

ÎÎÎÎ

tPLH, tPHL

ÎÎÎÎÎ

5.0 10 15

ÎÎÎÎ

—

ÎÎÎÎ

250 125 100

ÎÎÎÎ

500 250 200

ÎÎÎ

ns

X1 to Flag F, Flag O, RTN, JMP

ÎÎÎÎ

ÎÎÎÎÎ

5.0 10 15

ÎÎÎÎ

—

ÎÎÎÎ

200 100 85

ÎÎÎÎ

400 200 170

ÎÎÎ

ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

X1 to Write

ÎÎÎÎ

ÎÎÎÎÎ

5.0 10 15

ÎÎÎÎ

—

ÎÎÎÎ

225 125 100

ÎÎÎÎ

450 250 200

ÎÎÎ

X1 to Data

ÎÎÎÎ

ÎÎÎÎÎ

5.0 10 15

ÎÎÎÎ

—

ÎÎÎÎ

250 120 100

ÎÎÎÎ

500 240 200

ÎÎÎ

RST to RR

ÎÎÎÎ

ÎÎÎÎÎ

5.0 10 15

ÎÎÎÎ

—

ÎÎÎÎ

250 125 100

ÎÎÎÎ

500 250 200

ÎÎÎ

RST to X1

ÎÎÎÎ

ÎÎÎÎÎ

5.0 10 15

ÎÎÎÎ

—

ÎÎÎÎ

450 200 150

ÎÎÎÎ

Note 1

ÎÎÎ

RST to Flag F, Flag O, RTN, JMP

ÎÎÎÎ

ÎÎÎÎÎ

5.0 10 15

ÎÎÎÎ

—

ÎÎÎÎ

400 200 150

ÎÎÎÎ

800 400 300

ÎÎÎ

RST to Write, Data

ÎÎÎÎ

ÎÎÎÎÎ

5.0 10 15

ÎÎÎÎ

—

ÎÎÎÎ

450 225 175

ÎÎÎÎ

900 450 350

ÎÎÎ

Clock Pulse Width, X1

ÎÎÎÎ

tW(cl)

ÎÎÎÎÎ

5.0 10 15

ÎÎÎÎ

400 200 180

ÎÎÎÎ

200 100 90

ÎÎÎÎ

—

ÎÎÎ

ns

Rent Pulse Width, RST

ÎÎÎÎ

tW(R)

ÎÎÎÎÎ

5.0 10 15

ÎÎÎÎ

500 250 200

ÎÎÎÎ

250 125 100

ÎÎÎÎ

—

ÎÎÎ

ns

Setup Time — Instruction

ÎÎÎÎ

tsu(l)

ÎÎÎÎÎ

5.0 10 15

ÎÎÎÎ

400 250 180

ÎÎÎÎ

200 125 90

ÎÎÎÎ

—

ÎÎÎ

ns

Data

ÎÎÎÎ

tsu(D)

ÎÎÎÎÎ

5.0 10 15

ÎÎÎÎ

200 100 80

ÎÎÎÎ

100 50 40

ÎÎÎÎ

—

ÎÎÎ

Hold Time — Instruction

ÎÎÎÎ

th(l)

ÎÎÎÎÎ

5.0 10 15

ÎÎÎÎ

100 50 50

ÎÎÎÎ

0 0 0

ÎÎÎÎ

—

ÎÎÎ

ns

Data

ÎÎÎÎ

th(D)

ÎÎÎÎÎ

5.0 10 15

ÎÎÎÎ

200 100 100

ÎÎÎÎ

100 50 50

ÎÎÎÎ

—

ÎÎÎ

NOTE 1. Maximum Reset Delay may extend to one–half clock period.

ÎÎÎ

#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.

(4)

Figure 1. Typical Clock Frequency versus Resistor (RC)

RC, CLOCK FREQUENCY RESISTOR

10 kΩ 100 kΩ 1 MΩ

f Clk

, CLOCK FREQUENCY (Hz)

100 k 1 M

10 k

ÎÎÎÎ

Pin No.

ÎÎÎÎÎÎÎÎÎ

Function

ÎÎÎÎÎ

Symbols

ÎÎÎÎ

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

ÎÎÎÎÎÎÎÎÎ

Chip Reset Write Pulse Data In/Out

MSB Instruction Word Bit 2 Instruction Word Bit 1 Instruction Word LSB Instruction Word Negative Supply (Ground) Flag on NOP F

Flag on NOP O Subroutine Return Flag Jump Instruction Flag Oscillator Input Oscillator Output Result Register Positive Supply

ÎÎÎÎÎ

RST Write Data I3 I2 I1 I0 VSS Flag F Flag O RTN JMP X2 X1 RR VDD

Table 1. MC14500B Instruction Set

ÎÎÎÎÎÎ

Instruction Code

ÎÎÎÎÎ

Mnemonic

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Action

ÎÎÎ

0 1 2 3 4 5 6 7 8 9 A B C D E F

ÎÎÎÎ

0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111

ÎÎÎÎÎ

NOPO LD LDC AND ANDC

OR ORC XNOR

STO STOC

IEN OEN JMP RTN SKZ NOPF

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

No change in registers. RR RR, Flag O Load result register. Data RR

Load complement. Data RR Logical AND. RR Data RR

Logical AND complement. RR Data RR Logical OR. RR + Data RR

Logical OR complement. RR + Data RR Exclusive NOR. If RR = Data, RR 1 Store. RR Data Pin, Write

Store complement. RR Data Pin, Write Input enable. Data IEN Register Output enable. Data OEN Register Jump. JMP Flag

Return. RTN Flag and skip next instruction Skip next instruction if RR = 0

No change in registers. RR RR, Flag F

Figure 2. Outline of a Typical Organization for a MC14500B–Based System MEMORY

PROGRAM COUNTER

MC14500B CLOCK ICU

DATA I/O ADDRESS

I0, I1, I2, I3

ADDITIONAL OUTPUT DEVICES

MC14599B 8–BIT ADDRESSABLE LATCH

WITH BIDIRECTIONAL DATA MC14512 8–CHANNEL DATA SELECTOR

ADDITIONAL INPUT DEVICES

INPUTS 8 OUTPUTS 8

TO PERIPHERAL DEVICES

4 BIT OP CODE DA TA BUS

MEMOR Y ADDRESS

(5)

TIMING WAVEFORMS

Instructions NOPO, NOPF

Instructions RR, IEN, OEN remain unaffected

Instructions SKZ, JMP, RTN

Instructions RR, IEN, OEN remain unaffected X1

RST

IEN REGISTER OEN REGISTER

RR 4–BIT INSTRUCTION

FLAG 0

FLAG F

tW(R) tPHL (RESET TO XI)

tPHL (RESET TO RR)

NOP0 NOPF NOPO

tPLH (DATA TO FLAG)

tPHL

X1

4–BIT INSTRUCTION

RST

RR

JMP FLAG

RTN FLAG SKP F/F INTERNAL

* Instructions Ignored.

tW(cl)

SKZ * JMP RTN * JMP

tPHL

(RESET TO JUMP)

(6)

TIMING WAVEFORMS

Instructions STO, STOC, OEN

Instructions LD, LDC, AND, ANDC Instructions OR, ORC, XNOR, IEN

ÉÉÉÉÉÉ

1 X1

4–BIT INSTRUCTION

DATA

RR

OEN REGISTER (INTERNAL)

WRITE

STO STOC

NOP OEN STO

STOC

tPLH, tPHL (X1 TO DATA)

tPHL tPLH VALID WHEN RST = L

NOTE 1. Valid output data.

X1

4–BIT INSTRUCTION

DATA

RR

IEN REGISTER (INTERNAL)

LD, etc.

tsu(D)

tsu(I)

NOP IEN LD, etc.

th(I)

th(D)

tPLH, tPHL (X1 TO RR)

VALID WHEN RST = L

(7)

OUTLINE DIMENSIONS

P SUFFIX PLASTIC DIP PACKAGE

CASE 648–08 ISSUE R

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982.

2. CONTROLLING DIMENSION: INCH.

3. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL.

4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.

5. ROUNDED CORNERS OPTIONAL.

–A–

B

F C

S

H G

D

J

L

M

16 PL

SEATING

1 8

9 16

K

PLANE

–T–

A M

0.25 (0.010) M T

DIM MIN MAX MIN MAX MILLIMETERS INCHES

A 0.740 0.770 18.80 19.55 B 0.250 0.270 6.35 6.85 C 0.145 0.175 3.69 4.44 D 0.015 0.021 0.39 0.53 F 0.040 0.70 1.02 1.77

G 0.100 BSC 2.54 BSC

H 0.050 BSC 1.27 BSC

J 0.008 0.015 0.21 0.38 K 0.110 0.130 2.80 3.30 L 0.295 0.305 7.50 7.74 M 0 10 0 10 S 0.020 _ 0.040 _ 0.51 _ 1.01 _ L SUFFIX

CERAMIC DIP PACKAGE CASE 620–10

ISSUE V

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982.

2. CONTROLLING DIMENSION: INCH.

3. DIMENSION L TO CENTER OF LEAD WHEN FORMED PARALLEL.

4. DIMENSION F MAY NARROW TO 0.76 (0.030) WHERE THE LEAD ENTERS THE CERAMIC BODY.

–A–

–B–

–T–

F

E G

N K

C

SEATING PLANE

16 PL

D

A S

0.25 (0.010) M T

16 PL

J

B S

0.25 (0.010) M T M

L

DIM MIN MAX MIN MAX MILLIMETERS INCHES

A 0.750 0.785 19.05 19.93 B 0.240 0.295 6.10 7.49

C ––– 0.200 ––– 5.08

D 0.015 0.020 0.39 0.50

E 0.050 BSC 1.27 BSC

F 0.055 0.065 1.40 1.65

G 0.100 BSC 2.54 BSC

H 0.008 0.015 0.21 0.38 K 0.125 0.170 3.18 4.31

L 0.300 BSC 7.62 BSC

M 0 15 0 15 N 0.020 _ 0.040 _ 0.51 _ 1.01 _

16 9

1 8

(8)

MOTOROLA CMOS LOGIC DATA MC14500B OUTLINE DIMENSIONS

DW SUFFIX PLASTIC SOIC PACKAGE

CASE 751G–02 ISSUE A

DIM MIN MAX MIN MAX INCHES MILLIMETERS

A 10.15 10.45 0.400 0.411 B 7.40 7.60 0.292 0.299 C 2.35 2.65 0.093 0.104 D 0.35 0.49 0.014 0.019 F 0.50 0.90 0.020 0.035

G 1.27 BSC 0.050 BSC

J 0.25 0.32 0.010 0.012 K 0.10 0.25 0.004 0.009

M 0 7 0 7

P 10.05 10.55 0.395 0.415 R 0.25 0.75 0.010 0.029

B M

0.010 (0.25) M

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION.

4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE.

5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.13 (0.005) TOTAL IN EXCESS OF D DIMENSION AT MAXIMUM MATERIAL CONDITION.

–A–

–B– 8X P

G

14X

D

16X

SEATING PLANE

–T–

A S

0.010 (0.25) M T B ^S

16 9

8 1

F J

R X 45 _

_ _ _ _ M

C

K

How to reach us:

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