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MICROSYSTEM

COMPONENTS HANDBOOK

1986

About Our Cover:

The design on our front cover is an abstract portrayal of the unlimited interface linking options available with Intel microsystem components. Intel microprocessors and associated peripherals are the building blocks which provide total systems development solutions. Intel's superior technology, reliability and support provides easier solutions to specific development problems. Thereby, cutting "time-to-market" and creating

a

may appear in this document nor does it make a commitment to update the information contained herein.

Intel retains the right to make changes to these specifications at any time, without notice.

Contact your local sales office to obtain the latest specifications before placing your order.

The following are trademarks of Intel Corporation and may only be used to identify Intel Products:

Above, BITBUS, COMMputer, CREDIT, Data Pipeline, GENIUS, i,

t.

iCEL, iCS, iDBp, iDIS, 1²1CE, iLBX, im , iMDDX .. iMMX, Insite, Intel, intel, intelBOS, Intelevision, inteligent Identifier, inteligent Programming, Intellec, Intellink, iOSP, iPOS, iPSC, iRMX, iSBC, iSBX, iSOM, iSXM, KEPROM, Library Manager, MCS, Megachassis, MICROMAINFRAME, MULTIBUS, MULTI- CHANNEL, MULTIMODULE, ONCE, Open NET, Plug-A-Bubble, PROMPT, Promware, QUEST, QueX,Ripplemode, RMX/80, RUPI, Seamless, SLO, UPI, and VLSiCEL, and the combination of ICE, iCS, iRMX, iSBC, iSBX, MCS, or UPI and a numerical suffix.

MOS is an ordering code only and is not used as a product name or trademark. MOSII!> is a registered tr;ldemark of Mohawk Data Sciences Corporation.

*MULTIBUS is a patented Intel bus.

Additional copies of this manual or other Intel literature may be obtained from:

I ntel Corporation Literature Distribution Mail Stop SC6-59 3065 Bowers Avenue Santa Clara, CA 95051

"INTEL CORPORATION 1985

Table of Contents

NUMERIC INDEX ... vi CHAPTER 1

OVERVIEW

Introduction ... '. . . . 1-1

CHAPTER 2

8080, 8085 MICROPROCESSORS DATA SHEETS

8080A/8080A-1/8080A-2 8-Bit N-Channel Microprocessor ... 2-1 8085AH/8085AH-2/8085AH-1 8-Bit HMOS Microprocessor ... 2-10 8155H/8156H/8155H-2/8156H-2 2048-Bit Static HMOS RAM with I/O Ports and Timer .... 2-26 8185/8185-2 1024 x 8-Bit Static RAM for MCS®-85 ... 2-38 8224 Clock Generator and Driver for 8080A CPU ... 2-43 8228/8238 System Controller and Bus Driver for 8080A CPU ... 2-48 8237A/8237A-4/8237A-5 High Performance Programmable DMA Controller... 2-52 82C37A-5 CHMOS High Performance Programmable DMA Controller... .. 2-67 8257/8257-5 Programmable DMA Controller ... 2-78 8259A/8259A-2/8259A-8 Programmable Interrupt Controller... .. 2-95 82C59A-2 CHMOS Programmable Interrupt Controller... ... .. 2-113 8755A/8755A-2 16, 384-Bit EPROM with I/O ... 2-133 APPLICATION NOTES

AP-59 Using the 8259A Programmable Interrupt Controller ... 2-144

CHAPTER 3

8086, 8088, 80186, 80188 MICROPROCESSCORS DATA SHEETS

8086 16-Bit HMOS Microprocessor ... 3-1 80C86/80C86-2 16-Bit CHMOS Microprocessor ... 3-25 80186 High Integration 16-Bit Microprocessor ... 3-52 iAPX 88/10 8-Bit HMOS Microprocessor ... 3-106 80C88/80C88-2 8-Bit CHMOS Microprocessor ... : ... 3-133 80188 High Integration 8-Bit Microprocessor ... 3-162 8087/8087-2/8087-1 Numeric Data Coprocessor ... 3-218 8282/8283 Octal Latch ... 3-241 8284A/8284A-1 Clock Generator and Driver for iAPX 86, 88 Processors ... 3-246 82C84A/82C84A-5 CHMOS Clock Generator and Driver for 80C86, 80C88 Processors ... 3-254 8286/8287 Octal Bus Transceiver ... 3-263 8288 Bus Controller for iAPX 86, 88 Processors . . . .. . . .. 3-268 82C88 CHMOS Bus Controller for 80C86, 80C88 Processors ... 3-275 82188 Integrated Bus Controller for iAPX 86, 88,186,188 Processors ..•... 3-283 8289/8289-1 Bus Arbiter ... 3-299 APPLICATION NOTES

AP-67 8086 System Design ... 3-310 AP-113 Getting Started with the Numeric Data Processor ... 3-373 AP-186 Introduction to the 80186 ... 3-435

CHAPTER 4

80286 MICROPROCESSORS DATA SHEETS

iAPX 286/10 High Performance Microprocessor

with Memory Management and Protection ... 4-1 80287 80-Bit HMOS Numeric Processor Extension ... , .. '. . .. 4-56 82258 Advanced Direct Memory Access Coprocessor ... 4-82 82284 Clock Generator and Ready Interface for iAPX 286 Processors ... 4-139 82288 Bus Controller for iAPX 286 Processors ... 4-148 82289 Bus Arbiter for iAPX 286 Processor Family ... 4-167

CHAPTER 5

80386 MICROPROCESSORS DATA SHEETS

80386 High Performance Microprocessor with Integrated Memory Management.. . . .. 5-1 82384 Clock Generator and Reset Interface for 80386 Processors ... 5-2

iii

-VOLUME 2- CHAPTER 6

MEMORY CONTROLLERS DATA SHEETS

8202A Dynamic RAM Controller ... . 8203 64K Dynamic RAM Controller ...•...

8206/8206-2 Error Detection and Correction Unit ....•...•...

8207 Dual-Port Dynamic RAM Controller ....•.•...•.•.•.•...

8208'Dynamic RAM Controller ... " ... , ...•...

82C08 CHMOS Dynamic RAM Controller ..•...•.... ~ ..•...

USERS M A N U A L ' ,

Introduction ... . Programming the 8207 ... . RAM Interface .. ; ... ' ... . Microprocessor Interfaces ...•...•...

8207 with ECC (8206) •...•...

Appendix ...•.. ' ... "

APPLICATION NOTES

AP-97A Interfacing Dynamic RAM to iAPX 86/88 Using the 8202A & 8203 ....•...

AP-141 8203/8206/2164A Memory Design ... . AP-167 Interfacing the 8207 Dynamic RAM Controller to the iAPX 186 ... . AP-168 Interfacing the 8207 Advanced Dynamic RAM Controller to the iAPX 286 .•...

ARTICLE REPRINTS

AR-364 FAE News 1/84 "8208 with 186" ...•.

AR-231 Dynamic RAM Controller Orchestrates Memory Systems ... . SUPPORT PERIPHERALS

DATA SHEETS

8231 A Arithmetic Processing Unit ... : ... . 8253/8253-5Programmable Interval Tim,er ...•...•..•...

8254 Programmable Interval Timer ... : ... '.

82C54 CHMOS Programmable Interval Timer ...•... , ... . 8255A/8255A-5 Programmable Peripheral Interface ...•...

82C55A CHMOS Programmable Peripheral Interface ...•...

8256AH Multifunction Microproces,sor Support Controller ... . 8279/8279-5 Programmable Keyboard/Display Interface ... . APPLICATION NOTES

AP-153 Designing with the 8256 ... . AP-183 8256AH Application Note '

FLOPPY DISK CONTROLLERS DATA SHEETS

8272A Single/Double Density Floppy Disk Controller ...•...

" APPLICATION NOTES

AP-116 An Intelligent Data Base System Using the 8272 ... . AP-121 Software Design and Implementation of Floppy Disk Systems ... . HARD DISK CONTROLLERS

DATA SHEETS

82062 Winchester Disk Controller ... . 82064 Winchester Disk Controller with On-Chip Error Detection and Correction ... . APPLICATION NOTES

AP-182 Multimode Winchester Controller Using the 82062 .. ',' ... . UNIVERSAL PERIPHERAL INTERFACE SLAVE MICROCONTROLLERS

DATA SHEETS

UPI-452 Slave Microcontroller (8051) ... . UPI-41 8-Bit Slave Microcontroller ... . UPI-42 8-Bit Slave Microcontroller ...•...

8243 MCS-48 Input/Output Expander ... .

iv

6-1 6-15 6-30 6-52 6-98 6-121 6-151 6-152 6-157 6-166 6-174 6-177 6-181 6-217 6-223 6-228 6-235 6-246

6-253 6-263.

6-274 6-290 6-307 6-328 6-351 6-374 6-386 6-461

~-478 6-497 6-538

6-608 6-635 6-667

6-729 6-768 6-780 6-799

UPI-41/42 USERS MANUAL

Introduction ...•...•...•...•... ' •..• 6-805 Functional Description ...•...•... 6-810 Instruction Set .. " ...•. ~ ... 6-827 Single-Step, Programming, and Power-Down Modes ...•..•..•. 6-854 System Operation ...•...•....•..•... 6-859 Applications ... 6-865 AP-161 or 61 Complex Peripheral Control with the UPI-42 ...•.•...•. 6-939 AP-90 An 8741 A/8041 A Digital Cassette Controller ... 6-995 APPLICATION NOTES

Applications Using the 8042 UPI^T• Microcontroller ...•...•.... 6-1003 SYSTEM SUPPORT

ICE-42 8042 In-Circuit Emulator ....•..•...•.•...•... 6-1007 MCS-48 Diskette-Based Software Support Package ...•. 6-1015 iUP-200/iUP-201 Universal PROM Programmers ...•.•...••....•...• 6-1017

CHAPTER 7

ALPHANUMERIC TERMINAL CONTROLLERS DATA SHEETS

8275H Programmable CRT Controller ...•... 7-1 8276H Small System CRT Controller ... 7-25 APPLICATION NOTES

AP-62 A Low Cost CRT Terminal Using the 8275 ... 7-42 ARTICLE REPRINTS

AR-178 A Low Cost CRT Terminal Does More with Less ... 7-84 GRAPHICS DISPLAY PRODUCTS

DATA SHEETS

82720 Graphics Display Controller ...•... 7-91 ARTICLE REPRINTS

AR-255 Dedicated VLSI Chip Lightens Graphic Display Design Load ... 7-128 AR-298 Graphics Chip Makes Low Cost High Resolution, Color Displays Possible... .... 7-136 TEXT PROCESSING PRODUCTS

DATA SHEETS

82730 Text Coprocessor.. .. . .. ... .. . .. ... ... .... ... . ..•.•.. . .. .. ...•... .. 7-143 ARCHITECTURAL OVERVIEW

The 82786 CHMOS Graphics Coprocessor. . . • . . • . . . . • . . • . • . • . . . .. 7-187 ARTICLE REPRINTS

AR-305 Text Coprocessor Brings Quality to CRT Displays ...•.•...•... 7-205 AR-297 VLSI Coprocessor Delivers High Quality Displays ...•...•... 7-213 AR-296 Mighty Chips ...•...•.•...•....•.•..•... 7-216

CHAPTER 8

ERASABLE/PROGRAMMABLE LOGIC DEVICES DATA SHEETS

5C1211200 Gate CHMOS H-Series Eraseable/Programmable Logic Device ... 8-1 5C060 600 Gate CHMOS H-Series Erasable/Programmable Logic Device... 8-15

v

Numeric Index

5C121 1200 Gate CHMOSH-Series Eraseable/Programmable Logic Device ... 8-1 5C060 600 Gate CHMOS H-Series Eraseable/Programmable Logic Device .: ... 8-15 80186 (iAPX 186) High Integration 16-Bit Microprocessor ... 3-52, 3-435 80188 (iAPX 188) High Integration 8-Bit Microprocessor ... 3-162 80286 (iAPX 286/10) High Performance Microprocessor with Memory Management

and Protection ...• 4-1, 6-228, 6-247 80287 80-Bit HMOS Numeric Processor, Extension ... .4-56 80386 High Performance Microprocessor with Integrated Memory Management ...• 5-1 8041A/8641A/8741A UlJiversal Peripheral Interface

8-Bit Slave Micro Controller ... : ... 6-768, 6-805, 6-994 8042/8742 Universal Peripheral Interface

8-Bit Slave Micro Controller ... ; ... 6-780, 6-805, 6-939, 6-1002, 6-1006 80452/83452/87452 Universal Peripheral Interface 8-Bit Slave Micro Controller ... 6-729, 6-805 8080Al8080A-1/8080A-2, 8-Bit N-Channel Microprocessor ....•... , ... 2-1 8085AH/8085AH-2/8085AH-1 8-Bit HMOS Microprocessors ...•... 2-10 8086 (iAPX 86/10) 16-Bit HMOS Microprocessor .•...•.. 3-1, 3-310, 6-181 80C86/80C86-2 16-Bit Microprocessor ... ; ...•...

8087/8087-2/8087-1 Numeric Data Coprocessor ... 3-218, 3-373 8088 (iAPX 88/10) 8-Bit HMOS Microprocessor ...•.. ; .. 3-106, 6-181 80C88/80C88-2 8-Bit CHMOS

... 3-133 8155H/8156H/8155H-2/8156H-2 2048-8it Static HMOS RAM with I/O Ports and Timer .... 2-26 8185/8185-2 1024 x 8-Bit Static RAM for MCS®-85 ... 2-38 8202A Dynamic RAM Controller ...• 6-1, 6-181 820364K Dynamic RAM Controller ....•... 6-15, 6-181, 6-217 8205 High Speed 1 out of 8 Binary Decoder ... : ...•...

8206 Error Detection and Correction Unit ... 6-30, 6-217, 6-247 82062 Winchester Disk Controller ... ;

... 6-608, 6-667 82064 Winchester Disk Controller with On-Chip Error Detection and Correction ... 6-635 8207 Dual-Port Dynamic RAM Controller ... 6-52, 6-150, 6-223, 6-228, 6-247 8208 Dynamic RAM Controller ... 6-98, &235 82C08 Dynamic RAM Controller ... 6-121 82188 Integrated Bus Controller for iAPX86, 88, 186, 188 Processors ... 3-283 8224 Clock Generator And Driver for 8080A CPU ...•... ,2-43 82258 Advanced Direct Memory Access Coprocessor ... .4-82 8228/8238 System Controller and Bus Driver for 8080ACPU ... 2-48 82284 Clock Generator and Ready Interface for iAPX 286 Processors .•...•... 4-139 82288 Bus Controller for iAPX 286 Processors ... 4-148 82289 Bus Arbiter for iAPX 286 Processor Family ... ; ... 4-167 8231 A Arithmetic Processing Unit ... 6-253 8237A/8237A-4/8237A-5 High Performance Programmable DMA Controller ... 2-52 82C37A-5 CHMOS High Performance Programmable DMA Controller ... 2-67 82384 Clock Generator And Reset I nterface for 80386 Processors ... 5-2 8243 MCS-48 Input/Output Expander ... 6-799,6-805

vi

8253/8253-5 Programmable Interval Timer ... 6-263 8254 Programmable Interval Timer ... 6-274 82C54 CHMOS Programmable Interval Timer ... 6-290 8255A/8255A-5 Programmable Peripheral Interface ... 6-307 82C55A CHMOS Programmable Peripheral Interface ... 6-328 8256AH Multifunction Microprocessor Support Controller ... 6-357, 6-386, 6-461 8257/8257-5 Programmable DMA Controller ... 2-78 8259A/8259A-2/8259A-8 Programmable Interrupt Controller ... 2-95, 2-144 82C59A-2 CHMOS Programmable Interrupt Controller ... 2-113 8272A Single/Double Density Floppy Disk Controller ...

... 6-478, 6-497, 6-538 82720 Graphics Display Controller ... 7-91,7-128,7-136,7-205,7-213,7-216 82730 Text Coprocessor 7-136, 7-143, 7-205, 7-213, 7-216 .. , ... , ... , . 8275H Programmable CRT Controller ...

... 7-1, 7-42 8276H Small System CRT Controller ...•... 7-25, 7-84 82786 ... 7-187 8279/8279-5 Programmable Keyboard/Display Interface ... , ... 6-374 8282/8283 Octal Latch ... " . . . .. 3-241 8284A/8284A-1 Clock Generator and Driver for iAPX 86, 88 Processors ... 3-246 82C84A/82C84A-5 CHMOS Clock Generator And Driver

For 80C86, 80C88 Processors ... ,... 3-254 8286/8287 Octal Bus Transceiver 3-263 ... . 8288 Bus Controller for iAPX 86, 88 Processors ... 3-268 82C88 CHMOS Bus Controller for 80C86, 80C88 Processors ... ' ... 3-275 8289/8989-1 Bus Arbiter ... 3-299 8755A/8755A-2 16,384-Bit EPROM with I/O ... 2-133

vii

CUSTOMER SUPPORT

CUSTOMER SUPPORT

Customer Support is Intel's complete support service that provides Intel customers with Customer Training, Software Support and Hardware Support;

After a customer purchases any system hardware or software product, service and support become major factors in determining whether that product will continue to meet a customer's expectations.

Such support requires an international support organization and a breadth of programs to meet a variety of customer needs. intel's extensive customer support includes factory repair services as well as worldwide field service offices providing 'hardware repair services, software support services and customer training classes.

HARDWARE SUPPORT.

Hardware Support Services provides maintenance on Intel supported products at board and system level. Both field and factory services are offered. Services include several types of field maintenance agreements, instailation and warranty services, hourly contracted services (factory return for repair) and specially negotiated support agreements for system integrators and large volume end-users having unique service requirements. FO,r more information contact your local Intel Sales Office.

SOFTWARE SUPPORT

. Software Support Service provides maintenance on software packages via software support contracts which include subscription services, information phone support, and updates. Consulting services can be arranged for on-site assistance at the customer's location for both short-term and long-term needs.

For complex products such as NDS II or PICE, orientation/ installation packages are available through membership in Insite User's Library, where customer-submitted programs are catalogued and made available for a minimijm fee to members. For more information contact your local Intel Sales Office.

CUSTOMER TRAINING

Customer Training provides workshops at customer sites (by agreement) and on a regularly scheduled basis at Intel's facilities. Intel offers a breadth of workshops on microprocessors, operating systems and programming languages, etc. For more information on these classes contact the Training Center nearest you.

TRAINING CENTER LOCATIONS

To obtain a complete catalog of our workshops, call the nearest Training Center in your area.

Boston (617) 692-1000 London (0793) 696-000

Chicago (312) 310-5700 Munich (089) 5389-1

San Francisco (415) 940-7800 Paris (01) 687-22-21

Washington, D.C. (301) 474-2878 Stockholm (468) 734-01-00

Israel (972) 349-491-099 Milan 39-2-82-44-071

Tokyo 03-437-6611 Benelux (Rotterdam) (10) 21-23-77

Osaka (Call Tokyo) 03-437-6611 Copenhagen

198-033

Toronto, Canada (416) 675-2105 Hong Kong 5-215311-7

viii

OVERVIEW

INTRODUCTION

Intel microprocessors and peripherals provide a complete solution in increasingly complex application environ- ments. Quite often, a single peripheral device will replace anywhere from 20 to 100 TTL devices (and the associated design time that goes with them).

Built-in functions and standard Intel microprocessor/

peripheral interface deliver very real time and perfor- mance advantages to the designer of microprocessor- based systems.

REDUCED TIME TO MARKET

When you can purchase an off-the-shelf solution that replaces a number of discrete devices, you're also replac- ing all the design, testing, and debug time that goes with them.

INCREASED RELIABILITY

At Intel, the rate offailure for devices is carefully tracked.

Highest reliability is a tangible goal that translates to higher reliability for your product, reduced downtime, and reduced repair costs. And as more and more functions are intergrated on a single VLSI device, the resulting system requires less power, produces' less heat, and requires fewer mechanical connections-again re- sulting in greater system reliability.

LOWER PRODUCTION COST

By minimizing design time, increasing reliability, and

replacing numerous parts, microprocessor and peripheral solutions can contribute dramatically to lower product costs.

HIGHER SYSTEM PERFORMANCE

Intel microprocessors and peripherals provide the highest system performance for the demands of today's (and tomorrow's) microprocessor-based applications. For exam- ple, the 80386 32 bit offers the highest performance for multitasking, multiuser systems. Intel's peripheral pro- ducts have been designed with the future in mind. They support all of Intel's 8, 16 and 32 bit processors.

HOW TO USE THE GUIDE

The following application guide illustrates the range of microprocessors and peripherals that can be used for the applictions in the vertical column of the left. The peripherals are grouped by the I/O function they control.

CRT datacommunication, universal (user programmable), mass storage dynamic RAM controllers, and CPU/bus support.

An "X" in a horizontal application row indicates a potential peripheral or CPU, depending upon the features desired. For example, a conversational terminal could use either of the three display controllers, depending upon features like the number of characters per row or font capability. A "Y" indicates a likely candidate, for example, the 8272A Floppy Disk Controller in a small business computer.

The Intel microprocessor and peripherals family provides a broad range of time-saving, high performance solutions.

inter Intel's Microsystem Components Kit Solution

[1 ^<i£ 1-

I'

1-

"'nt,'

FLOPPY DISK CONTROL 8272A

MEMORY SUPPORT 8203 8206 8207 8208/82C08

ROM/EPROM

CPU SUPPORT 8231 A 8254/82C54 8255/82C55 8256AH 8294A

LOCAL AREA NETWORKING 82501 82502 82586 82588

CPU 8086 8088 80186 80188 80286

8251A 8273173-4 8274 82530-530-6 8044/8344/8744

HARD DISK CONTROL 82062 82064

SPECIAL PERIPHERAL CONTROL UPI'· 8041A UPI'· 8042 UPI'· 8741A UPI'· 8742

HARD COPY CONTROL UPI'· 8042/8742

KEYBOARD CONTROL 8279-5 UPI'· 8041A UPI'· 8042 UPI'· 8741A UPI'· 8742

CRT CONTROL 8275 8276 82720 82730

INSTRUMENTATION BUS (GPIB) 8291 8292

Get Your Kit Together!

-~

-- 8

_/L&£W

September 1985 Order Number: 230664-004

APPLICATION CHART

POTENTIAL APPLICATION X-TYPICAL APPLICATION Y

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Printers

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Plotters X X

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TERMINALS Conversational Graphics CRT Editing Intelligent Videotex

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INDUSTRIAL AUTO Robotics

Network Numeric Control Process Control Instrumentation Aviation/Navigation INDUSTRIAUDATA ACO.

Laboratory Instrumentation Source Data

Auto Test Medical

Test Instrumentation Security'

COMMERCIAL DATA PROCESSING

POS Terminal Financial Transfer Automatic Teller Document Processing WORKSTATIONS

Office Engineering CAD

MINI MAINFRAME Processor & Control Store Database Subsystems I/O Subsystem Comm. Subsystem 'Single Source Product

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8202A

DYNAMIC RAM CONTROLLER

• Provides All Signals Necessary to Con- trol 2117, or 2118 Dynamic Memories

• Directly Addresses and Drives Up to 64K Bytes Without External Drivers

• Provides Address Multiplexing and Strobes

• Provides a Refresh Timer and a Refresh Counter

• Refresh Cycles May be Internally or Exter-.

nally Requested

• Provides Transparent Refresh Capability

• Fully Compatible with Intel® 8080A, 808SA, iAPX 88, and iAPX 86 Family Micro- processors

• Decodes CPU Status for Advanced Read Capability with the 8202A-1 or 8202A-3

• Provides System Acknowledge and Trans- fer Acknowledge Signals

• Internal Clock Capability with the 8202A·1 or 8202A-3

The Intel® 8202A is a Dynamic Ram System Controller designed to provide all signals necessary to use 2117 or 2118 Dynamic RAMs in microcomputer systems. The 8202A provides multiplexed addresses and address strobes. as well as refresh/access arbitration. The 8202A-1 or 8202A-3 support an internal crystal oscillator.

AHQ-AHS

REFRESH COUNTER

R i S I S 1 - - - I ... - - - 1 i i C s - - - o j

REFRO/ALE - - - 1

COLUMN ADDRESS

""X

ROW ADDRESS

""X

60

Figure 1. 8202A Block Diagram 6-1

...

TIMING GENERATOR

RA'So

m, m2

RAs3

CAS WE

SACK XACK

AH, AH, AH, AH, AHa ALa aiJTo AL, M1 AL, M2 AL, 0iJf3 AL4 0iJf4 ALS 5lJfs ALO 0uT6 GNO

Vee AHs AH,

N.C.

REFRO/AlE

Figure 2. Pin Configuration 205215-001

Pin Symbol No. Type

ALo 6 I

ALI 8 I

Al2 10 I

AL3 12 I

AL4 14 I

Al5 16 I

Al6/ 18 I

AHO 5 I

AHI 4 I

AH2 3 I

AH3 2 I

AH4 1 I

AH5 39 I

AH6 38 I

BO 24 I

Bl/ 0P l 25 I

PCS 33 I

WR 31 I

RD/Sl 32 I

REFRQ/ 34 I ALE

OUTO 7 0

OUTI 9 0

OUT2 11 0

OUT3 13 0

OUT4 15 0

OUT5 17 0

OUT6 19 0

WE 28 0

CAS 27 0

Table 1. Pin Descriptions Name and Function

Address Low: CPU address in·

puts used to generate memory' row address.

Address High: CPU address in·

puts used to generate memory column address.

Bank Select Inputs: Used to gate the appropriate RASO·

RAS3 output for a memory cy·

cle. B 1/ OP 1 option used to se·

lect the Advanced Read Mode.

Protected Chip Select: Used to enable the memory read and write inputs. Once a cycle is started, it will not abort even if PCS goes inactive before cycle completion.

Memory Write Request.

Memory Read Request: SI function used in Advanced Read mode selected by OP 1 (pin 25).

External Refresh Request: ALE function used in Advanced Read mode, selected by OP 1 (pin 25).

Output of the Multiplexer:

These outputs are designed to drive the addresses olthe Dynamic RAM array. (Note that the OUT 0.6 pins do not require inverters or drivers for proper operation.)

Write En,able: Drives the Write Enable inputs of the Dynamic RAM array.

Column Address Strobe: This output is used to latch the Col·

umn Address into the Dynamic RAM array.

6-2

Pin

Symbol No. Type Name and Function RASO 21 0 Row Address Strobe: Used to RAS1 22 0 latch the Row Address into the RAS2 23 0 bank of dynamic RAMs, select·

RAS3 26 0 ed by the 8202A Bank Select pins (BO, Bl/0Pl).

XACK 29 0 Transfer Acknowledge: This output is a strobe indicating val·

id data during a read cycle or data written during a write cycle.

XACK can be used to latch valid data from the RAM array.

SACK 30 0 System Acknowledge: This output indicates the beginning of a memory access cycle. It can be used as an advanced trans·

fer acknowledge to eliminate wait states. (Note: If a memory access request is made during a refresh cycle, SACK is delayed until XACK in the memory ac·

cess cycle).

(XO) OP2 36 110 Oscillator Inputs: These inputs (XI) ClK 37 110 are designed for a quartz crystal to control the frequency of the oscillator. If XO/ OP2 is connect·

ed to a 1 Kfl resistor pulled to

+ 12V then XI / ClK becomes a TTL input for an external clock.

N.C. 35 Reserved for future use.

Vce 40 Power Supply:+5V.

GND 20 Ground.

NOTE: Crystal mode for the B202A·l or 8202A·3 only.

I--...

cs*

lKn

±5%

Cs < 10pF FUNDAMENTAL XTAl

x,

8202A-l or 8202A-3

Figure 3. Crystal Operation for the 8202A-1 and the 8202A-3

205215-001

inter ^8202A

Functional Description

The 8202A provides a complete dynamic RAM controller for microprocessor systems as well as expansion memory boards. All of the necessary control signals are pro- vided for 2117 and 2118 dynamic RAMs.

All 8202A timing is generated from a single reference clock. This clock is provided via an external oscillator or an on chip crystal oscillator. All output signal transitions are synchronous with respect to this clock reference, ex- cept for the CPU handshake signals SACK and XACK (trailing edge).

CPU memory requests normally use the RD and WR in- puts. The advanced READ mode allows ALE and S 1 to be used in place of the RD input.

Failsafe refresh is provided via an internal refresh timer which generates internal refresh requests. Refresh re- quests can also be generated via the REFRQ input.

An on-chip synchronizer / arbiter prevents memory and re- fresh requests from affecting a cycle in progress. The READ, WRITE, and external REFRESH requests may be asynchronous to the 8202A clock; on-chip logic will syn- chronize the requests, and the arbiter will decide if the re- quests should be delayed, pending completion of a cycle in progress.

Option Selection

The 8202A has two strapping options. When OP,is se- lected (1SK mode only). pin 32 changes from a RD input to an S 1 input, and pin 34 changes from a REFREQ input to an ALE input. See "Refresh Cycles" and "Read Cycles"

for more detail. OP1 is selected by tying pin 25 to +12V through a 5.1 K ohm resistor on the 8202A-1. or 8202A-3 only.

When OP2 is selected, by connecting pin 3a to + 12V through a 1 K ohm resistor, pin 37 changes from a crystal input (X 1) to the CLK input for an external TIL .clock.

Refresh Timer

The refresh timer is used to monitor the time since the last refresh cycle occurred. When the appropriate amount of time has elapsed, the refresh timer will request a refresh cycle. External refresh requests will reset the refresh timer.

Refresh Counter

The refresh counter is use'd to sequentially refresh all of

Description Pin # Normal Function

B1/0P1 25 Bank (RAS) Select

the memory's rows. The 8-bit counter is incremented after every refresh cycle.

Address Multiplexer

The address multiplexer takes the address inputs and the refresh counter outputs, and gates them onto the address outputs at the appropriate time. The address outputs, in conjunction with the RAS and CAS outputs, determine the address used by the dynamic RAMs for read, write, and refresh cycles. During the first part of a read or write cy- cle, ALo-ALa are gated to OUTO-OUTS, then AHo-AHa are gated to the address outputs.

During a refresh cycle, the refresh counter is gated onto the address outputs. All refresh cycles are RAS-only re- fresh (CAS inactive, RAS active).

To minimize buffer delay, the information on the address outputs is inverted from that on the address inputs.

OUT O-OUT a do not need inverters or buffers unless addi- tional drive is required.

Synchronizer / Arbiter

The 8202A has three inputs, REFRQ / ALE (pin 34), RD (pin 32) and WR (pin 31). The RD and WR inputs allow an external CPU to request a memory read or write cycle, respectively. The REFRQ/ ALE allows refresh requests to be requested external to the 8202A.

All three of these inputs may be asynchronous with re- spect to the 8202A's clock. The arbiter will resolve con- flicts between refresh and memory requests, for both pending cycles and cycles in progress. Read and write re- quests will be given priority over refresh requests.

System Operation

The 8202A is always in one of the following states:

a) IDLE b) TEST Cycle c) REFRESH Cycle d) READ Cycle e) WRITE Cvcle

The 8202A is normally in the IDLE state. Whenever one of the other cycles is requested, the 8202A will leave the IDLE state to perform the desired cycle. If no other cycles are pending, the 8202A will return to the IDLE state.

Option Function

Advanced-Read Mode (see text) XO/OP2 36 Crystal Oscillator (8202A-1 or 8202A-3) External Oscillator

.... igure 4. 8202A Option Selection

6-3 205215-001

Test Cycle

The TEST Cycl!;! is used to check operation of several 8202A internal functions. TEST cycles are requested by activating the RD and WR inputs, independent of PCS. The TEST Cycle will reset the refresh address counter. It will perform a WRITE Cycle if PCS is low.

The TEST Cycle should not be used in normal system operation, since it would affect the dynamic RAM refresh.

Refresh Cycles

The 8202A has two ways of providing dynamic RAM re- fresh:

1) Internal (failsafe) refresh 2) External (hidden) refresh

Both types of 8202A refresh cycles activate all of the RAS outputs, while CAS, WE, SACK, and XACK remain inac-

tive. .

Internal refresh is generated by the on-chip refresh timer.

The timer uses the 8202A clock to ensure that refresh of all rows of the dynamic RAM occurs every 2 milliseconds.

If REFRQ is inactive, the refresh timer will request a re- fresh cycle every 10-16 microseconds.

External refresh is requested via the REFRQ input (pin 34).

External refresh control is not available when the Ad- vanced-Read mode is selected. External refresh requests are latched, then synchronized to the 8202A clock.

The arbiter will allow the refresh request to start a refresh cycle orily if the 8202A is not in the middle of a cycle.

Simultaneous memory request and external refresh re- quest will result in the memory request being honored first.

This 8202A characteristic can be used to "hide" refresh cycles during system operation. A circuit similar to Figure 5 can be used to decode the CPU's instruction fetch status to generate an external refresh request. The refresh request is latched while the 8202A performs the instruction fetch; the refresh cycle will start immediately after the memory cycle is completed, even if the RD input has not gone inactive. If the CPU's instruction decode time is long enough, the 8202A can complete the refresh cycle before the next memory request is generated.

Certain system configurations require complete external refresh requests. If external refresh is requested faster than the minimum internal refresh timer (tREF), then, in ef- fect, all refresh cycles will be caused by the external re- fresh request, and the internal refresh timer will never generate a refresh request.

6-4

SO~

-""

'-__________

8202A

Figure 5. Hidden Refresh

Read Cycles

The 8202A can accept two different types of memory, Read requests:

1) Normal Read, via the RD input

2) Advanced Read, using the S1 and ALE inputs The user can select the desired Read request configura- tion via the B1 /OP1 hardware strapping option on pin 25.

Normal Read Advanced Read

Pin 25 81 input +12 Volt Option

Pin 32 RD input Sl input

Pin 34 REFRQ input ALE input

# RAM banks 4 (RAS 0.3) 2 (RAS 2-3) Ext. Refresh Req. Yes No

Figure 6. 8202A Read Options

Normal Reads are requested by activating the RD input, and keeping it active until the 8202A responds with an XACK pulse. The RD input can go inactive as soon as the command hold time (tCHS) is met.

Advanced Read cycles are requested by pulsing ALE while S 1 is active; if S 1 is inactive (low) ALE is ignored.

Advanced Read timing is similiar to Normal Read timing, except the falling edge of ALE is used as the cycle start reference.

If a Read cycle is requested while a refresh cycle is in progress, then the 8202A will set the internal delayed- SACK latch. When the Read cycle is eventually started, the 8202A will delay the active SACK transition until XACK goes active, as shown in the AC timing diagrams. This de-' lay was designed to compensate for the CPU's READY setup and hold times. The delayed-SACK latch is cleared after every READ cycle.

Based on system requirements, either SACK or XACK can be used to generate the CPU READY signal. XACK will

205215-001

8202A

normally be used; if the CPU can tolerate· an advanced READY, then SACK can be used, but only if the CPU can tolerate the amount of advance provided by SACK. If SACK arrives too early to provide the appropriate number of WAIT states, then either XACK or a delayed form of SACK should be used.

Write Cycles

Write cycles are similiar to Normal Read cycles, except for the WE output. WE is held inactive for Read cycles, but goes active for Write cycles. All 8202A Write cycles are

"early-write" cycles; WE goes active before CAS goes ac- tive by an amount of time sufficient to keep the dynamiC RAM output buffers turned off.

General System Considerations

All memory requests (Normal Reads, Advanced Reads, Writes) are qualified by the PCS input. PCS should be sta- ble, either active or ·inactive, prior to the leading edge of RD, WR, or ALE. Systems which use battery backup should pullup PCS to prevent erroneous memory requests, and should also pullup WR to keep the 8202A out of its test mode.

In order to minimize propagation delay, the 8202A uses an inverting address multiplexer without latches. The system must provide adequate address setup and hold times to guarantee RAS and CAS setup and hold times for the RAM. The 8202A tAD AC parameter should be used for this system calculation.

The BO-B 1 inputs are similiar to the address inputs in that they are not latched. BO and B 1 should not be changed during a memory cycle, since they directly control which RAS output is activated.

The 8202A uses a two-stage synchronizer for the memory request inputs (RD, WR, ALE), and a separate two stage synchronizer for the external refresh input (REFRQ). As with any synchronizer, there is always a finite probability of metastable states inducing system errors. The 8202A synchronizer was designed to have a system error rate less than 1 memory cycle every three years based on the full operating range of the 8202A.

6-5

A microprocessor system is concerned with the time data is valid after RD goes low. See Figure 7. In order to calcu- late memory read access times, the dynamic RAM's A.C.

specifications must be examined, especially the RAS-ac- cess time (tRAC) and the CAS-access time (tCAC). Most configurations will be CAS-access limited; i.e., the data from the RAM will be stable tcc,max (8202A)

+

Since the 8202A normally performs "early-write" cycles, the data must be stable at the RAM data inputs by the time CAS goes active, including the RAM's data setup time. If the system does not normally guarantee sufficient write data setup, you must either delay the WR input signal or delay the 8202A WE output.

Delaying the WR input will delay all 8202A timing, including the READY handshake signals, SACK and XACK, which may increase the number of WAIT states generated by the CPU.

If the WE output is externally delayed beyond the CAS ac- tive transition, then the RAM will use the falling edge of WE to strobe the write data into the RAM. This WE transition should not occur too late during the CAS active transition, or else the WE to CAS requirements of the RAM will not be met.

Ro~ I

______

"': q - - - t R l D V !IE I

~ _ _ _ I

DATA

---« B--

I :

t - t R A C - . . . J

I I

RAS

---""""'~ i ; -

I I tCAC I

4----+1

CAS - - - " ' ' \

1;-

Figure 7. Read Access Time

205215-001

OTITO-6 ... r---

AS-15

~

^r

ALE 80-1

8088 8202A _-

{16K MODE) WE

~

ADO-7 CAS CAS

f - ^RAS

RO

r=p

WR WR

1

RAS,

E-

-

-< SACK ^RAS2t:: RAS3 r ' ^AO-6

XACK

~

t----

I I

~ AO-.

:::

- -

,TT.

.. ~ AO- •

c.-===:

~S~

DATA

V ^{1" T I}

DATA-BUS LATCH IN

--1\

Figure 8. Typical 8088 System

6-6

D'N DOUT

J

2118 DYNAMIC RAM ARRAY

BAL

l

'1, +

BAL

,ID'N DIN DOUT

DOUT

J ^j

. " . . - -

O'N DOU1

U

D'N DOUT

:u

D'N

IT

D'N D'N DOUT ^DOUT

Dour

.---

205215-001

inter

ABSOLUTE MAXIMUM RATINGS'

Ambient Temperature Under Bias ... O'C to 70'C Storage Temperature ... -6S0C to +150°C Voltage On any Pin

With Respect to Ground ... -0.5V to +7V4 Power Dissipation ... 1.5 Watts

• NOTE: Stresses above those listed under "Absolute Maxi- mum Ratings" may cause permanent damage to the device.

This is a stress rating only and functional operation of the de- vice at these or any other conditions above those indicated in the operational sections of this specification is not implied.

Exposure to absolute maximum rating conditions for ex- tended periods may affect device reliability.

D.C. CHARACTERISTICS TA

=

=

=

=

Symbol Parameter Min Max Units Test Conditions

Vc Input Clamp Voltage -1.0 V IC

=

ICC Power Supply Current 270 rnA

IF Forward Input Current

ClK -2.0 rnA VF

=

All Other Inputs3 -320 p.A VF

=

IR Reverse Input Current3 40 p.A VR

=

VOL Output low Voltage

SACK,XACK 0.45 V 10l

=

All Other Outputs 0.45 V 10l

=

VOH Output High Voltage Vil

=

SACK,XACK 2.4 V. 10H

=;

All Other Outputs 2.6 V 10H

=

Vil Input low Voltage 0.8 V VCC = 5.0V (Note 2)

VIHI Input High Voltage 2.0 V VCC = 5.0V

VIH2 Option Voltage V (Note 4)

F = 1 MHz

CIN Input Capacitance 30 pF VB lAS = 2.SV, VCC = 5V

TA = 2S'C NOTES:

1. IR = 200l'A for pin 37 (elK) for external clock mode.

2. For test mode RD & WR must be held at GND.

3. Except for pin 36.

4. 8202A-l and 8202A-3 supports both OP, and OP,. 8202A only supports OP,.

+12 Volt ' K 36

±10%

1

OP,

8202A 5.1 K

2S OPI

Resistor Tolerance: ±5%

6-7 205215-001

A.C. CHARACTERISTICS

TA = O'C to 70'C, vcc "" 5V ± 10%, VCC = 5V ± 5% for 8202A-3

Measurements made with respect to RASO-RAS3, CAS, WE,OUTo-OUTe are at 2.4V and 0.8V. All other pins are measured at 1.5V. All times are in nsec.

Symbol Parameter Min Max

tp Clock Period 40 54

tpH External Clock High Time 20

tpL External Clock Low Time-above (» 20 mHz 17

tpL External Clock Low Time-below «) 20 mHz 20

tRC Memory Cycle Time 10tp - 30 12tp

tREF Refresh Time (128 cycles-16K mode) 264tp 288tp

tRP RAS Precharge Time 4tp - 30

tRSH RAS Hold After CAS 5tp - 30

tASR Address Setup to RAS tp - 30

tRAH Address Hold From RAS tp - 10

tASC Address Setup to CAS tp - 30

tCAH Address Hold from CAS 5tp - 20

tCAS 'CAS Pulse Width 5tp - 10

twcs WE Setup to CAS tp - 40

tWCH WE Hold After CAS 5tp - 35

tRS RD, WR, ALE, REFRQ delay from RAS 5tp

tMRP RD, WR setup to RAS 0

tRMS REFRQ setup to RD, WR 2tp

tRMP REFRQ setup to RAS 2tp

tpcs PCS Setup to RD, WR, ALE 20

tAL S 1 Setup to ALE 15

tLA S 1 Hold from ALE 30

tCR RD, WR, ALE to RAS Delay tp

+

+

tcc RD, WR, ALE to CAS Delay 3tp

+

+

tsc CMD Setup to Clock 15

tMRS RD, WR setup to REFRQ 5

tCA RD, WR, ALE to SACK Delay 2tp

+

tcx CAS to XACK Delay 5tp - 25 5tp

+

tcs CAS to SACK Delay 5tp - 25 5tp

+

tACK XACK to CAS Setup 10

txw XACK Pulse Width tp - 25

tCK SACK, XACK turn-off Delay 35

tKCH CMD Inactive Hold after SACK, XACK 10

tLL REFRQ Pulse Width 20

tCHS CMD Hold Time 30

tRFR REFRQ to RAS Delay 4tp

+

tww WR to WE Delay 0 50

tAD CPU Address Delay 0 40

6-8

Notes

4,5

3 3 3 3 3

8

5

5

2 2 1

2,9

2,10

7

11 e 8 3

205215-001

WAVEFORMS

Normal Read or Write Cycle

Advanced Read Mode

ALE

XACK

SACK

8202A

tRS ---+-

I A S -

~~1~-

__

- M A X ICC

- t C A -

6-9 205215-001