This manual contains diagrams for use with System/360 Model 40 2040 Processing Unit, Field Engineering Maintenance Manual, Order No. SY22-2841, and also with the following manuals:

System/360 Model 40 2040 Processing Unit

il ^{~ gj ~} Field Engineering

Diagram Manual

SY22-2842-3

SY22-2842-3 FES: SY22-6827

PREFACE

This manual contains diagrams for use with System/360 Model 40 2040 Processing Unit, Field Engineering Maintenance Manual, Order No. SY22-2841, and also with the following manuals:

System/360 Model 40 Comprehensive Introduction, Field Engineering Theory of Operation Manual, Order No. SY22-2840.

System/360 Model 40 Functional Units, Field Engineering Manual of Instruction, Order No. SY22-2843.

System/360 Model 40 Theory of Operation, Field Engineering Theory of Operation Manual, Order No. SY22-2844.

System/360 Model 40 Power Supplies, Features, and Appendix, Field Engineering Manual of Instruction, Order No. S223-2845.

Power Supplies, SLT, SLD, ASLT, MST, Field Engineering Theory of Operation Manual, Order

No. SY22-2799. This manual may be used for maintenance or instruction purposes. It contains Data Flow Charts, Simplified Logic Diagrams (SLD) , Condensed Logic Flow Charts (CLF), Malfunction Analysis Procedures (MAP), and 1401/1460 Emulator Flow Charts.

The EC level of Control Automation System (CAS) Logic Diagrams referenced within this manual is 255263. ALD references are at EC level 254814 for all diagrams except the 1401/1460 emulator flow charts, which are at EC level 255264. The Mid-Pac power supply is at EC level 255055 and

the 2. 5 kHz HF Power Supply is at EC level 266316. Subsequent engineering changes may alter the con- tents of this manual.

Fifth Edition (January 1970)

This manual, Order Number SY22-2842-3, is a reprint of Y22-2842-2 incorporating changes released in FE Supplement Y22-6809, November 28, 1969.

Changes are continually made to the specifications herein; any such changes will be reported in subsequent revisions or FE Supplements.

This manual has been prepared by the IBM Systems Development Division, Product Publications, Dept B96, PO Box 390, Poughkeepsie, N. Y. 12602. A form for readers' comments is provided at the back of this publication. If the form has been removed, comments may be sent to the above address.

©

Copyright International Business Machines Corporation 1966, 1970

CONTENTS Figure Title

DATA FLOW CHARTS

011 Selector Channel Data Flow 012 CPU Data Flow

013 Microprogram Data Flow 014 CPU Microprogram Flow Chart 015 ROS Control Word

101 Multiplex and MS Unit Data and Control SIMPLIFIED LOGIC DIAGRAMS (SLD)

501 LSAR Parity Generation 502 Clock Control (SP)

504 Main Storage Control and Timing Circuits (2 Sheets) 505 Function and Control Registers

506 Decimal Filler 507 Decimal Correction 508 Carry Latches

509 Selector Channel Controls (2 Sheets)

510 Mid-Pac Power Supply Wiring Diagram (2 Sheets) 510A 2040 Mid-Pac Wall Frame Wiring Diagram 511 2.5 kHz HF Power Supply Wiring Diagram 512 Multiplex Channel Controls

513 Main Storage X-Dimension Drive CONDENSED LOGIC FLOW CHARTS (CLF) 599 How to Use Flow Charts 600 Instruction Matrix

601 Instruction Fetch Microprogram

602 2nd Level Instruction Fetch, RX Fixed Point 603 2nd Level Instruction Fetch, RX Floating-Point 604 2nd Level Instruction Fetch, RS and Sl Operations 605 2nd Level Instruction Fetcl)., SS Logical

606 2nd Level Instruction Fetch, SS Decimal

607 Machine Status at 1st and 2nd Level Function Branches 608 Branch and Link

609 Set and Insert Storage Key 610 Convert Decimal to Binary 611 RR Fixed Point Sign Operation 612 Branch on Count

613 Convert Binary to Decimal 614 Set Program Mask

615 RR and RX Fixed Point Arithmetic and Logic 616 RX Fixed Point Add and Subtract

617 RX Compare Algebraic 618 Branch on Condition

620 RR and RX Fixed Point Multiply 621 RR and RX Fixed Point Multiply, Notes

622 RR and RX Fixed Point Multiply, Detail of Loops 623 Fixed Point Divide Initialization

624 Fixed Point Divide Loop

625 RR Floating-Point Sign Operations

626 RR and RX Floating-Point Operation (2 Sheets) 627 Floating-Point Load and Store

628 Floating-Point Multiply/Divide Initialization (2 Sheets) 629 Floating-Point Multiply Loop

630 Floating-Point Divide Loop 631 Test Under Mask

632 Branch on Index 633 Set System Mask

634 RS Load and Store Multiple 635 Shifts

636 SIOperations, AND, OR, EXOR, MOVE 637 Read Direct and Write Direct

638 Load PSW (2 Sheets) 639 Diagnose Instruction 641 SS Translate

642 SS Translate and Test

643 Edit, Edit and Mark (2 Sheets) 644 SS Edit, Refill

647 SS Logical Operations, Move Zone and Numeric 648 SS Logical Operations, Move Complete

649 SS Logical Operations, Compare 650 SS Decimal Divide

651 Decimal Divide Example

652 Decimal Divide Add/Subtract Paths 653 SS Decimal Multiply

654 Decimal Pack 655 Decimal Unpack

656 Decimal Move

with

Offset

657 General Flow Chart for Decimal Add Sub Compare 658 SS Decimal Load and Process Operand 1

659 SS Decimal Load Zero and Add Entry 660 SS Decimal Load Operand 2 and Process 661 SS Decimal Terminate

662 SS Decimal Compare

665 Start I/O Instruction (Multiplex Channel)

666 I/O Codes, Common Decoding; Test Channel and Mpx Halt I/O (2 Sheets)

667 Start I/O Microprogram Mpx Channel (2 Sheets) 668 Test I/O Multiplex Channel Microprogram 669 Multiplex Channel Microprogram (4 Sheets) 670 Multiplex Channel Status

671 I/O Interrupts and Update Timer Microprogram 674 Selector Channel Status

675 Selector Channel I/O Instructions Microprogram (4 Sheets)

686 Store PSW - General Flow

MALFUNCTION ANALYSIS PROCEDURES (MAP) 901 Interpret Errors (2 Sheets)

906 Control Check 907 Early Check 908 Late Check

911 Read Only Storage (3 Sheets) 912 Local Storage

913 Storage Protect

914 Main Storage (64K MAP) 915 Multiplex Channel 916 Selector Channel 917 Mid-Pac Power Supply 918 2.5 kc HF Power Supply

1401/1460 COMPATIBILITY FEATURE FLOW CHARTS 6200 1401 Instruction Fetch

6200A 6200B 6201 6202 6202A 6203 6203A 6204 6205 6206 6207 6207A 6207B 6207C 6208 6208A 6208B 6209 6209A 6209B 6210 6211 6212 6213 6213A 6214 6215 6216 6217 6218 6219 6220 6221 6222

1401 Instruction Fetch 1401 Instruction Fetch 1401 N Operation 1401 Add and Subtract 1401 Add and Subtract 1401 Compare

1401 Compare

Store 1401 AAR or BAR Multiway Branch

1401 Increment-Decrement Scatter--Gather

Scatter--Gather

Scatter (OOS Compatibility Feature) (2 Sheets) Gather (OOS Compatibility Feature)

1401 Multiply and Divide 1401 Multiply and Divide 1401 Multiply and Divide

1401 Move, Load, Zero and Add, Zero and Subtract 1401 Move, Load, Zero and Add, Zero and Subtract 1401 Move, Load, Zero and Add, Zero and Subtract 1401 I/O M, L, U Operations

1401 Unit Record Operations

1401 Carriage Control and Stacker Select 1401 Address Modify

1401 Address Modify

1401 Set Word Mark, Clear Word Mark, Clear Storage, and Special Clears

1401 Move Characters and Suppress Zeros 1401 1 and 2Byte Data Service

Set Selector Channel to 1401 Mode 1401 Tape Operations

1401 Branch if: Word Mark or Zone, Bit Equal or Character Equal

1401 Emulator Program Entry 1401 Diagnose

1401 Branch Tests

6223 1401 Move and Binary Decode 6224 1401 Move and Binary Code

6225 1401 Read and Punch Column Binary 6226 1401 Index Factor Fetch

6227 1401 Index Add

1410/7010 COMPATIBILITY FEATURE FLOW CHARTS (CLF) 6300 1410/7010 Operation Codes in EBCDIC-II

6301 1410E Instruction Fetch-Overall 6302 1410E Instruction Fetch Start 6303 1410E X Control Field Readout 6304 1410E Address Readout

6305 1410E Instruction Fetch Ending

6306 1410E NOP and Non-Interruptible Op Codes 6307 1410E Chaining

6308 1410E Indexing (Two Sheets) 6309 1410E Branch on Channel Status 6310

6311 6312 6313 6314 6315 6316 6317 6318 6319 6320 6321 6322 6323 6324 6325 6326 6327 6328 6329 6330 6331 6332 6333 6334 6335 6336 6337 6338 6339 6340 6341 6342 6343 6344

INDEX X-I X-2 X-3

1410E Priority Test and Branch, Branch on Internal Indicator 1410E Branch if: Character, WM/Zone, or Bit Equal

1410E Store Address Register (Two Sheets) 7010E Store and Restore Status

1410E Set/Clear WM and Clear Storage 1410E Table Lookup

1410E Add, Subtract, Multiply, and Divide 1410E Add, Subtract-Initial Loop

1410E Add, Subtract-Main Loop

1410E Add, Subtract-Special Loop and Ending 1410E Multiply-First Scan

1410E Multiply Loop 1410E Divide Initial Loop 1410E Divide Loop and Ending

1410E Data Move, Zero Add/Subtract, and Compare 1410E Zero Add/Subtract-Initial Loop

1410E Zero Add/Subtract-Main and SpeCial Loops 1410E Data Move Minus Scan-Initial Loop

1410E Data Move Minus Scan, Zero Add/Subtract A Cycles 1410E Data Move Plus Scan-Initial Loop

1410E Data Move Plus Scan-Main Loop 1410E Compare-Initial Loop

1410E Compare-Main Loop

1410E Compare Character and Ending

1410E Unit Control, I/O Move/Load-Initial Loop 1410E X-control Field Translation

1410E I/O Unit Selection 1410E One-Byte Data Service 1410E Two-Byte Data Service

1410E Forms Control and Stacker Select 1410E Diagnose Instructions, I-Fetch Linkages 1410E Edit Diagnose

1410E Scatter/Gather Diagnose 1410E Gather Diagnose

1410E Disk Diagnose--End of Storage or GMWM Scan

Bus In Selector Channel Interface Bus Out

FIGURE 011. SELECTOR CHANNEL DATA FLOW

PC TO PO

Halds Byte Count T Register

PC T1

7 PO 7

Start Address XOlll000XXXOO

~ ^... ...

S Register

SX SO

6 Bits tL2 Constant m 0 1 1 1()

~ ~

SI

N

() ()

~ _~

D~ll

Channel Key P4 - 7

Cond

() ( ) ( )

"B'C

~ ~~

..,'"

o -

..,,,,

12 11 10 9 8 7 6 5 4 3 2 1 0

ROSCAR

-

Bus

ALU Extention

ALU

ALU Compress

R Bus 2 and Extension

ROS Bus

--

CA Field from ROS

~13

^{Bits and}

p~~"'",,",,~",,~~ ROSAB--~~~

I

r - -

Prot Store 4 Bits 128 Wds ~

... 5 Bits

f

7 Storage Address Bits and Yl Mpx !;.

Stono ' 12BWd.

0-3 PSN PSN 4-7

-

Select Mpx

Star

I/C Byte

X Bits 5&6

OR STOR ADR DISPLAY Byt. Byte 0 Byte I Byte I

X Bits Bits Bit 7 Bit 7 0-7 0-6

6 Bits andYl

6 Bits and VI

' / / / / /

~ ~

P. ... AA~L'U~I.EPx.':lnU.'R

•• 9 . . .

~

. . .

~===ALU~~P~~~~~~~~8y~te~=-"~~/'~+-"""""""""

V

I

Manual AddreH Entry Switches

I I

MS Address Compare

I

T 1

~ ^{r -}

//////////I17~'~ Tr:t~- Z

In Logic

I

PSN 5-7

Trans-

l

late

i L1

^ic

l

Any EX! I,p"

Mpx SCI SC2

o ~ 7

Interrupt Request Latch-J

Main storage. PG

Emit Field

Mpx Store STAT/CIZER

r -==.:~ f.} -%- ~

I ~B~~

I .."...1

7'-'--'Y7.L....L--'~

^•

L _ .-RO"-P,-"S",N,,,--6--, I[

External Interrupts

t

^{Control Accept D;,.ct-~}

o - ⁷

DC In

PSNO-3.

PCPG

Data

t

~ ~

~

~ ~l

h~7 ,LfWdJ i

II II

L: __

^{To BO}

,j ...

_D.C_ln.'t.ru.ct.;o.n.'~)1

(

PO-3

K.y

PC PO- _ _

BO Bl

Ir;E-

^{SN4- ~}

'--_ _ +_C:;:o;;:m=DO"~ • .:B~U,I.. _ _ _ _ oIoI~"""~~

--

7 -- 7

L..T" _ _

+-_...;...;....;..;;;:;.;;.'--_...,I-_._~v_';'g_I~_.t1_~n

_ _ _ _ _ _ _

r-lu.-___ yUI-.--

r ALU Extn Output ALU Output Bus

~

ALU Compress

AX

n,

Log-Out Error Entries

AO

Ister

AI

yt.

I

r

,----i

^{E£ P}

-ed

^{Q -}

I ' - - - . -

! ~r2Ex";W"'t-+P...;0--ri-~-f:+~""~-~-~~"'~::-I- -i

I

I ^;::,',ry

lpn.., pn _ 7 I

I F61Mo! 2 ~LU- I

__ t" ~nar~

I , - ~PG _ut^P/ I

I I '7ALtr. I

I I ~.:!jrollr,Dec,~al I I

I I I

I I

Emit Field

C Register

CX CO Cl

1>5-7 Ipo - 7 IPO - 7

f

II II

.----=---:-""'-_...,

II I I

1-,--",D"::-:3Regri;;'i"t.!...' ----::::i

II 1-1

ASCII I I

~ DO-~

Dl -

i:

:=1-;:I==yc===I=:=1 =:1

rPO"--~-~7~~~PO~-~7~1~:=_;:I==Y=CD=;:I~1

- I: I_I D;sobl.1

~

:~OP5Nll-1

^Wgit

I ~

I~-I ^PMA

I I

I R~~_'*I=~*I

=ll II "

IMA II

II

_I

l

^{D;'.ct Control Pre~ent}

I I I

I

I

Manual Control Adr

: I

.. Rl ~ Entry, Load Adr Entry,

~~~Q5Z~Q5Ji~;J~lJ~Z~Q2flIIData Entry, Store

I

l> 2 Bytes Plus 3 Bits I Select Entry

.RX~RO~

..1\.2 Bvtes P us 3 Bits I Data

I PO - ⁷

DC Out

I /, Mpx /

2~t~ :::::::~~2~8y:t~~~::::::::::::::::::::::::::~II~I~IIIIIIII~~~~~~;;;;~~::::::~M~PX~Bu~,~~uut

~~""'~VY~'X~XS;>6("~xZ:;<,.~v:21)('Z7<.~,/V';2S;~'X~x~x.~V"X~X'ZY:~~lSI~RJB~u,J2l:!B~~t;e,!JP~'u;!'13!Ex!!:, '>(:sQQ~X~Q~~)(~')(2X~X~Z X6;~2lZ'2~~~'X~X~~ZX~SC362~~~?:2~~~Y~0Q11 ^X I

^{I I _ M Bu, I}

~ !! _~

^{.!R _ :R}

^t

^{eg.,.l7:t·., •}

_~

^{RO RI}

~POG E'~"

^-7',

~PG-

P12

r ,,,,,-"'!.: N

ROS Bu.

k ""-""-""-""-""-""-""-""-""-""-""-""-""-""- ""-""'-l -

l'-.. ""-""-""-""-""-""-""-""-""-""-""-""-""-""-""-""-""-""-""-""-""-""-'"

I I

11 ~

^j

~~;~c -.~c -

: I

'1.

Read Only 5to,,"g.

~~ ~:~;ral

-- -- RX RO Rl

,eid ROS Bit Function Control Decoder* P5-7 PO - 7 PO - 7

- ~. - A 0 -3 ROS Next Address - Latches I I C t ,

ROBAR PG ROAR B 4 -7 B Condition Tests Special Controls .,....---, B I

~::o ~

_ a P1 _ 0 C 8- 11 C Condition Tests ~~ C ROS Word

D 12-13 ROS Address Control ~~ ,6,ddress

PSNO-3

~N.

^4-7

Incr -2 ±j a

lit ^{ttl :}

¹⁴¹⁸¹⁷ ~:~Fldl:,."Pa';'YB;' ~ ^{''PC' -}

G 19-20 ALU Funcl;an Control Ii'

r:===~~~~~dJ~c

^{- LOCAL}

f<:-..",-..-",,.,,-J H 21-25 Locol Storage Address Control ~ H c~~tr:~d Logical STORAGE

~ '~""-tJ.R05AB"""-""-""-""-""-""-""-""-""-""-"~-"" J

26-2B R-R.g;,t.rlnputConhol m

~===t~·gI--':'-iJg=1~:I

Channel Te," 144HALFWORDS

Reg Formot

~ ~-

~. ~s;~1IIIIj LSAR

I

^ROS _Compare ^Addre..

I

K 29 Skew Control Of ALU Q Entry ~ J- . ~ "'""'!""""" Conditions 22 BITS L

30 -

32 R-Register Output Control

r

tt:!pq::j::lP';L;::t::j~

M 33 - 36 ALU Output Control ~ ~

-#- ...

N :5l-40 StatAndFunctionReg.lnput-Ctrl. ~ ~ ~~

P 41 -43 AlU Input From P Bus 1-+--.----i~Up ~ ^ontrol

Q 44-47 ALU Input From ^Q Bu, 1-+--+----i+l::9:

~ ~~~n:1

R 48-50 Miscellaneous ~=:::t=~;;::=...L.=~---lJr-- Data Flow

S 51 Word Parity Bit t-

Jx

^{5254 53} JW.ld~~;on 0 g

LP~X~~55~~P~FI~.~ld~ExN~~N~;on~ __________ ~ __ ~---

* All Decoders Are Checked Expect LAnd M Indicators On Internol CE Panel

l

ManUal Data Entry Switches

I L.J

^{ROS Word}

1

14- - - ' - ''----'''Ch''''ec;;;.k_-''

FIGURE 012, CPU DATA FLOW

.i!

I

^{PO-3 4-7}

_ LS,RBUS

Manual Adr Entry Sw

H

PO - 7 PO -

- =

LEGEND 1 Bi t Data Path

Extension (PSN P5-7) Data Path Half Byte Bus (4 Bits + Parity) 6 Bi t Address Bus 1 Byte Bus (8 Bits + Pority)

14 Bit Address Bus \13 Bits Plus Parity) 17 Bit Address Bus

2 Bytes Bus (16 Bits + 2 Parity Bits) 2 Bytes + Ext Bus (19 Bits + 3 Pari!)' Bits~

Special Data Path For Dump log Out Or Manual Display Operations Crossing Buses Bus Distribution Parity Checker Parity Generation Indicator

r 1 ,

HARDWARE CYCLES (T CLOCK STOPPED) LTJ

¢

jl.PROGRAM CYCLES (T CLOCK RUNNING)

~

, CONSOLE SWITCHES

r /.

V· SELECTOR CHANNEL BREAK IN. THEY CAN r~OCCUR WHENEVER MAIN STORAGE FREE

//DUMPS CAUSED BY )J-PROGR INTERRUPTS

L/

THESE CAN OCCUR BETWEEN ANY TWO

~" MICRO INSTRUCTION PROVIDING THE INHIBIT 'DUMP(YB)STAT IS OFF E, MAIN STORAGE IS FREE

I FETCH

EXECUTION

t

STATUS AFTER

~~jEST

FIGURE 013. MICROPROGRAM DATA FLOW

STADB- .

----.

TERMI~'

~-

.---'

~

~

PRI

~

SUPERVISOR CALL INSTR.

t

~ ~

COM. CHAIN.

+

DEY. END

.J----

FETCH CCW

.~

RE 4

SELECT

•

.---

~

/ /

1

DATA CHAINING

.~.

----::::..-

i

/"- PROGRAM LOG-OUT

1

FETCH

I

NEXT CCW

+

t

ACCEPT

i

STATUS

+

LOOP ON ROS

UPDATE

t

PSW INTO LOCAL STORE

+

;::.;.;:::-. ... _ _ .;... _ _ _ .j.i.iW;.;;"AIT OR I FETCH

LOOP ON M.S.

(GENERATES PRJ SETS HALT LATCH IF A REG

=ADDR.SW)

HARDWARE SYSTEM RESET

~

CPUE, CHN.

1

CHECKOUT

~

DISPLAY

1

ROUTINE (STORE)

j

POWER ON (HALT)

)J-PROGRAM SYSTEM RESET

HALT

STORE PSW FROM LSTOR INTO MS

LOAD PSW FROM MS INTO L STOR

t

IPL ROUTINE

IPL END

V6 Set by Start Key Causes Ignoring PRJ

Instruction Fetch 223-2842 l'Igs 601 - 606

Flow Cha .... lor { ,?p Codes in

223-2842

No

Instruction Fetch Start

Stop or LOOP~

V J..

To Program Check Interrupt Microprogram

To Supervisor Call Interrupt Microprogram

To Program Check Interrupt Microprogram

No SAB=Addr

~----='--""'Keys During

r---"=.

M,S Write

.'V'

Ves

These decisions are effective a any time during the execution of the instruction.

223-2841

223-2841

Error Routine

Microprogram Controlled Log Out of Local Storage and Data Flow into

lVoin Siorage - Set Y7 to Indicate Log Out - Set Y4, Y5 and Y6

De endent on Channel errors

223-2844 {

Hardstop on Control Check Errors onl

L

_N_m. __ l_. __

C_O~

^{__ lt_lorg __}

t_~_t_c.

^__

~

^__

~_~

^__

~_m_l_n_N_~_p_t_(P_R_)

___________________ QD_3 __

~Hb~lt_la~t~ch~~~~~~~

^{a. Stop key} __________________ QD_4 ___ ^o. Ex_te_ma __ Console attention (interrupt pushbutton on console depressed)

l_in_t_e~_u_p_b_m_~

^__

~

^__ to_a_I_IOW ____________________ - J

1

CD

Channel interrupt if masked to allow b. Instruction step mode b. Interval timer in main storage has timed out Stop on MS ) • dd . h External interrupts 3 through 7

®

4 bit timer nonzero (cancelled by disable interval timer switch) d. loop on MS via a ress compare SWltc System reset pushbutton

f. Power on Pushbutton

223-2844

FIGURE 014. CPU MICROPROGRAM flOW CHART (CHANNEL DATA SERVICE NOT SHOWN)

"Current" PSW is modified to indicate latest status (condition codes etc.) and is stored in main storage.

Main storage location is determined b the t e of intelTu t. The stored PSW is now the "old" PSW

To Load FiBt Customer PSW from MS Location 00000

223-2842 { Fig 638

A "new^{l l} PSW is transferred from main storage to local storage. Main storage location is determined by the type of interrupt.

Ref.r to { Mach ine Status

Charts

Th is "new" PSW is now the "current' r PSW

To PRI Scan Microprogram

Ves

Manual Stop microinstruction

"Manual" light glowing on console Exit only under console switch control

Hardware Controlled System Reset

CPU and Ch~nnel Checkout Microprogram Oiardstop on any Error) .

Microprogram Controlled System Reset

No

To Instruction Fetch

No

To Program Check Microprogram

Ves

(To other built - in diagnostic microprograms selected by diagnostic control switch)

CD main storage validated if Y15 on

®

if log out, only channels in error are reset

Exit Conditions from System Reset. Take One Leg Only

Interrupt Routine

223-2842- Model 40 Diagrams Manual 223-2844- Model 40 Theory of Operations 223-2841- Model 40 Maintenance Manual

CA FielD CB FIELD

I

lOS ^Port

1

oddreu, ^{of next}

I

dependent on

CB & CD fields

I

Controh bit I of next ROS address

CB field contents

o

I 2 3 4 5 6 7 8 9 10 11 12 13 14 15

y~ I/O 10.3

CPU

Function

o

I VCD L2,0 ALUfO VO V2 V4 V6 FXP TO ALU7 IZT IDQ ASCII Minus 'NO

rC"'S""'f;-.,-d...L'u-nc-';-on"""' contents

o

I 2 3 4 5 6 7 8 9 10 11 12 13 14 15

o

I VCO ADR-I ALUfO Halt

V.

V6 Lood ALU7

~~-~C

'NS

Bit I is set to

o if CB = 0-13 and CD "" 1 013 When CD,.- 1 or3,

the CB field does not control bit I.

It brings up special control

lines as shown below:

10 CC FielD

Controls bit

o of next ROS address

11 12 13

CD FIELD

o I

Works with CB field to determine

the next ROS odeIress

~~I/O_

Q

_CPU

CC field Function CC field Function

contents contents

o 0 o 0

I I I I

2 VCO 2 YCD

3 L4f

3 "

4 ALUfO • ALUfO

5 VI 5 DUll'

6 Y3 6 MSC

7 V5 7 V5

8 V7 8 V7

9 AlU6 9 HLOfl

10 AllJO 10 CDA

11 QIljoIO 11 STA-I

12 PIli 12

13 VCI 13 BU<I

14 SAT 14 SAT

15 Q.TV IS OP-I

I

~3

r---''<~~~ ~>''----_,

CB field contents

o

I 2

•

3 5 6 7 8 9 10 11 12 13 14 15

Function ADR-O CMD-O SVC-O Sel ISO 1-+IR O-+IR CL-CH

,0.-0

ICC REINT Dump HIO 'NS

• FIGURE 015. ROS CONTROL WORD

I or 3

contents

o

I 2 3 4 5 6 7 8 9 10 11 12 13 14 15

STAN DC-IN 1.00 SSM SWEA STPCI Monuol O ... SlO Edit SMSC OAT

SU'-O UndlM'lP 'NO

14 IS 16

CE FielD

I 2

Emit field Darn murce for loco I store address

formation as controlled by the CH field Data source for the set or reset of stats as controlled by CN field Data source for setting the ALU function register as controlled by

CN;; 15 Data source for ALU Par Q

inputs as controll.d by CP or CQ fields

17 18 19 20 CF CG FIELD

I

CF field - is the parity bit of the current ROS control word- must match the parity of the ROAR address

ALU function control CG field Function contents

o YB =0 Indirect function ?

o VS:I 0">

1 AND.

2 MINS-

3 PLUS+

CJ field contenll

o

I 2 3

•

5 6 7

21 22 23 24

CH FIELD

Local storage address

I

control, affects lSAR, J Reg, K Reg, use CE field to M!t addresW!s. Ule CJ

or CL field to control reod or write CH field contents

o

I 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 2' 25 26 27 28 29 30 31

Gated to' SAS LAS SDS CIT LSTOR

Function

,

BE+!.. I

,

H+l :L+H AE+L Il.J AE+LIL+J BE+lIL+J QE+L!L+J J+l IL ... J BE+L :~NT

,

H+L Il-I.H 1 AE ... l~L-I.J BE+l'l-l.S QE+l. :L-I.J J-+l ,L-I+J 8E-+l IREST

,

H.a. ~L+I+H

AE+LIL+I+J 8E+L :L.,.I+J QE+LIL+I+J J+L :l+I+J JE+L ,l ... J JE+LI AE+ll 1 AE+l:L+H BE+l ,L+H QE+l.ll+H J-+I. IL-2+.J

fCJ field contenll

o

I 2 3 4 5 6 7

I

Gated Z

to'

A B C o

HJ LSTOR CIS

I

V ••

No

27 28 29 30 31 32

CJ FiElD CK CL FielD

I

_",.w ^CK _control

I

^field

I

R bus input control

I

Manual state-stot

VIO No

R bus output control Cl field Gate contents R to

o Z

I lSTOR

2 S

3 HJ

• A

5 S

6 C

7 0

ALU output control CM field contents

o

I 2 3 4 5 6 7 8 9 10 11 12 13 14 15

ALU gated to Z AX AD Al DATA 80 SI S' CX CO CI V 00 01

V ••

Reinterpret >-'=---~I

CJ field contents

o

I 2 3 4 5 6 7

Gated to' CST 5 T WIll W2 W3.

33 34 35

CM FIELD

NO<?

Reinterpret Yeo

CM field Function contenti

o

I 2 3

•

5 6 7 8 9 10 11 12 13 14 15

W, CfL Tl CS' SI SO SX

36 37 38 39

CN FIELD

I 2

I

Stats and function control CN field Function contents

o

1 -+YA

2 YA:1

3 VAn

4 ... YB

5 YB;!

6 VSQ

7 YD:1

8 YDO

9 VE:l

10

11 YCHO

12 YCH:l

13 Note 1 14 15 Indirect

I

function as set by CE field

Function function register 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 lOll 1100 1101 1110 1111

O.

DSQ SUQ

•

AND OS.

SUP .NQ Q XO' QN' OSH LSH DAD ADD

42 43 CP FielD

I 2

ALU input control to P bus

Y

""to. No channel

Yeo

CP field Goted contenh to P

o

I

2 SO

3 SI

• TO

5 Tl

6 CSB

7 WIl

44 45 46

CQ FIELD

I 2

I

ALU input control to Q bus CO field Gated contents to Q bu

o Z

I SO

2 SI

3 CX

4 CO

5 CI

6 DO

7 01

8 EO

9 OE

10 V

11 DATA

12 CHI

13 EXI

14 SP

15

CP field Gated contents to P

o Z

I AX

2 AD

3 Al

• 80

5 SI

6 EO

7 OE

Note 1: Set Relocate Latches G' 10 Byte 0 Bih I 2 3

o 0 I

o I 0

o I I I 0 0 I 0 I I I 0 I I I

Hex Base

04000 08000 OCOOO 10000 14000 18000 ICOOO

Relocate latch (on) 3 2 I - - X - X - - X X X - - X - X X X - X X X

1401 Bose

16k 32k 481<

64k 10k 96k 112k

47 49

CR FIELD

Mise control CR field contents

Op

o NoOp

1 Read 2 Write 3 TRAP 4 lOS

5 CPU

6 0 SK

50 51 52 53 54 55

CS CT FIELD

I

Pority of this ROS word. Odd parity is mointoined by a

o or 1 in this position

EXTENSION

I

ExtE:nds fields _J

I I

and P

Corry control CT field contents

Op NoOp M

o

I

7 ADCMP

LSAR Load LA Bits 0-3 E Field Parity

- - - - ' - - - f N I - . . . . _ - - - L _ - - 1

RL401

Q Bits 0-3 Odd

LSAR Load LQ Bits 0-3 Plus Pty

LSAR Load LB Bits 0-3 Se leet SC 2 Early Thru Sw

I/O State Early

Register H Bit Pty

LSAR Load H Bits 0-3 P I us Pty

LSAR Load J Bits 4-7 Register J Bit Pty

LSAR Load LJ Bits 4-7 Register J Bit 6

Register J Bit 7

RL40l E Field Bit 2 Powered E Field Bit 3 Powered

Log Mem Call Reset Trap

Set LSAR From Data Sw Addr Sw Rl Bit Parity

FIGURE 501. LSAR PARITY GENERATION

LSAR Parity

Bit LSAR Odd Pty

OR FL

Reset LSAR

RL401

_l_o..::g_O_ut_S_w_i_tc_h _ _ _ ~,...--,...--

MSS 1 Early A

~St~op~H~a~lf~C~lo~c~k~l~_~~

PI Del A

~T~3~0~r~T~3~D~e~I~~~~~~

Repeating on ROS latch A

~I~~k

Repeat ROS (Console) latch

h Stop Clock latch

_N~ot~l~~~l_l~a_tc _ _ _ ~~ OR~---~~F7l-'---'~~~~~~

P3 Del A

_P~3~0~r~P~3~D~e~I _ _ _ _ _ ~~

Manual Set ROS Addr A Not MSS 2

System Reset Stop T Clock

Dump Stop ,--_ _ -/...-- Undump Stop T Clock

P3

R-

Not Hardstop

1

A

~

' - - - - '

~

Not Power Good OR

Hardstop ^{L - -}

Trap latch OR Inhibit B Gate Clock

SlO or ICC Hardstop

~~E_rr_or_w_il_I_St_o~P_C_I_OC_k

_ _ _ _ _ _

-4_~~~

---~---.---~~---~

T4

PI Del

_N~0~t~Re7pe~a~to-n-RO~S-l-a-tc-h-r_,r--r-­

Gate Hardstop

P3 A

T1 Del

ROS Address Compare -

Stop Half Clock 1

Not Dump Cycle Start T lS Write ...;B~;---.:,,14 ______ -l1 A

Set ROS Inh ibit

Gate Stop on ROS Compare D - 3

I

Stop ROS or Stop ROS and MS A O R ! , B

~

^Hardstop

~- r---ir~Fl,-}-~~~~

Stop Half Clock 2

Not T3 Dell A

- 1

Cycle with T Clock Stop

Not T4

1 11---'---.:....

' - - - - '

Push Switch latch and not MSS 2

~l~o..::g~l-la-t-ch----~1

OR I,

I--'-~

Hardstop

1

Inhibit

A on Error

~P4~or~P4~D~e~1

__

~~~r---l~ OR~--_t--~F~l~---~I~n~hi~b~it~o~n~E~r~ro~r

Error will Stop Clock

Not B; 4 Not D; 3

Set ROS Inh ibi t

_ Not

lswEA

OR

OR

A

Hardstop

Inhibit ROS (Inhibits setting of ROS output Sense latches)

A

_ Allows

L . - - - -...

-~---l-

A--' L-

^Display Hardstop Allows Display

~ ~~1---~----~~

' - - -

Microprogram Stop

Not Start log latch

Microprogram log

0---

~----+--l-L.:.J

N 1---1

KcOai"

...---.

Repeat ROS '---1

I

Gate Hardstop -.".-..:.-,---,,---,,...,--,-,---1 I OR 1---____ :....-

Single Cycle Mode ,

Repeating on ROS latch System Reset Bat P2 Del

OR ^~ _ _ _ _ _ ....J

Display ROAR-ROSCAR

log Out Start T Clock r _ _

Dump Cycle Start T l S Write Trap Start T

Undump Start T

System Reset Start

log Out Switch MSS 1

Not Error Stat Y12 A

Start

I L ~ ~h

Start log latch

P2

~M7a~n~u~a~1 ~Se~t~R~O~A~R~

_ _ _

~OR~---rT-C~I~o-ck~~S~ta~rt-T~C~1o~c~k

_ _ _ _ _ _ _ _ _4 -:N:"o~t_'R:.:e:=-pe~a~t~R:..:O:::S~:___:____I,...-- Fl

~ ORr---~ Fl ~---~~--- _M_ic_r_op~r_'og~r_a~m~l~o~g _ _ _ ~r--r--

A _p_4_D_e:...I ______________ ----l1 A OR

~_-I

Repeating on ROS latch

P2 or P2 Del A

Set Repeat ROS Address L~ A

~~

CPU Check Status

Stop on Error ...---.

_E"'r_ro:..;,r--;S:-'-ta"-t--:Y'-:1;..:;2;--_ _ _

-l1

OR

I

Error Stop load Stat Y15

RY121

FIGURE 502. CLOCK CONTROL (KC071-KC081)

P2

KC071

Not Hardstop

Stop Half Clock 2

~----+-~ N~--~---~~~~----~

Repeating on ROS latch Repeat ROS

P4

A

A

System Reset B at P2 Del L - -

TcOal

~~~~~~~---/

Repeat ROS Addr

Fl

KC071

Set Repeat ROS Address

Start Switch

..:.M:;.:S=.S..:..l _ _ _

---I'

^A

Stop Half Clock 2

l

P2 System Reset B at P2 Del _

Single Cycle Mode

l

OR

lJ.-_--l

Not Repeat ROS (Console)

I I

' - - - - '

A

A

Repeating on ROS

Fl

Hardstop Allows Display

Repeating on ROS latch

A

C

o

x R/W Term Gate Tmg

X Gate Decade

~

^{X Read} Term Gote ^XR,ad

Ank-,

~

Lr

^XWdt.

I

X Write

I

Term Gate

~ ~ !

Gate Decade Output

x R/W StatUi

~O __________________ --;~~-X~G~at~'~O~.~~o~OO~

1....-¹: . . . - - - . , Gat. 1 of 16 Active

X Gate Decode 15 r - - - 0 XROO - - G

MBo7I

1"":f---l-1---tr-:-l

14

_{Nat IS Road}

'---t-t

_- ~~---'''---I ^IS

s::,r~

lt~

llll -=~

^{r - OXWOO}

To X Ovn t-- G 1--''-=-=----'

A X Read

-8. _r-jW:'l

o

R.ad 07

8~X~W~'~ite~--_+~--_r o

Write H )( R,fN TOIl ~

15 14 5

S 4 2

X Driver

~I----"---\ IS

- 7XROO

t-- G

~ r - - - 7 XWOO - - G

Y R/W Term K Gate Tmg

Lr

^{Y Road}

Y Read

I

Term Gate

Lr

^YWdt.

I

256 X line,

~

Y Gate Decode Selection

rh I

~

Y

Y

wri~

Term Gate

. Diodes 130

~ $

Gote Decode Out~t Y ~t!LStatu, Driver Output

Y Gate Decod. 00

~~s---'Gm'

>---

^{16 Gate Inputs}

~ 0 YR 00 - - G

1..-..:.9 ________________ --; Oecode

10

Y Gat. Decode 15

C )-_Yc.Ro=ad=--____ --,

1~1~1--~~---iL-~

:~ Road ~---+~~ o YR 15

IS

1.1.1.1.

⁰⁰ __ --C;I-":O-,-YW __ .:::OO,-~ ____ -,

L)-Y~R~/w~T~~~

^____

~r-

Write

O>,-Yc.W~'~1t~·---{~O~j---1-~-t~O=--Y~W~I~S---i _~

Bit 13 Gate Decode 0

~:

It-____

-'G'''a'''to:..:O,,.:::cad= • ..:....1 1 ..-.:.Not:=.:..;8::;lb::..;:IS'-__________ _I Decade

M8291

c Y Read o

Road M Bump Ovr Trng

MB 291

o YWrite

o

Bump Decode Selection

SAB 15 13

o 0 0

1 0 1

2 1 0

3 1 1

__ ~1---'R"".a"'d-"8"'um=pI0-/

Read Bump 1

-

__ (;-I_--^W,,-''''''=-' ::.:8u::;:mr..P0=--t

Write Bump 1

Write j---L __ ..J

MB 371

G

Not 14

1 I

I r = - - - H - - l S •• 8

6

=L.J

.---.

Not 6 ]

I

Ir-""'--"---H---l See C

14 =LJ

~.:.:14'---_I_-il

^A

I

^{Sog 0}

6

=LJ

10

IplOll 213141S16171pI0111213141s 6 7

OR •• ;n2040

l'7j 1611S 14113 112111 110 I

9

Is 17 I 6 IS 14 13 12 I' 0

Data 8u.

SegA Z Tmg Z Drivers

~

Z Bit 00 Seg~:~ Sense Bit 00 Seg ::::::~

AR ~t---~---~---iAR

~~_~ ~t--

11

I - AR =~Sog 8 AR

~

- rSog: TO t--OR r_

\-- AR - L-.! Sog C AR

Oata-In f---~I--_+r---=--'---...,f-'>---i---jl-, Final Amp

-G--

^powering

^r.-

^{AR -} Z Bit 00 Seg D

AR ~

Data Bit LIM MC 021 Nat 00 ' - - - - -

AR ' - - - -

SAB 15 14 6

A 0 0 0

B O O 1 C O l O D O l I Z Sense Segment

Selection

F Strobe B T mg E Strobe A T mg

Strobe

1..-~!O:"':-'~"-4---+--_+_{J ^A J~-'St"'.abo=-"8Y"'tt.'-'0"-_I~

_SagA

_{1-:J_.}

Nat 6

A

I

Strobe Byte 1

f-C-J

Not 14

~6"'Na-:t.."-;-4---+---+r-rA-,, Strobe By!e a J I

Sog 8

~ot

¹⁴

I

Strobe Byte 1

I~~----_+--T~-IA ~==~~

~t 6 -~ Strobe Byte 1

Ir'~---I--__t__i A II-=:'==-":""-\

Not 6 Seg C

A I Strobe Bvte 0

f-L-J

14

~"-~ 4:---i:---t---r--11 Strobe Byte 1

J

A I

SogO Ir-"14'---t--IJ

A~

I-"St"',ob"'"-• ..,8"'t.'!....!!.0-\

L...L.J

SA8

14

6 A 0 0

8' 0 1

C 1 0

o 1 I Strobe-Segement

Selection

~

.>-____

l-____________________________ ~Add::~:.:.0:.:c:ad:.~8~;b~ __________________________ ~L_ ________________________________________________________________________ _L ______________ ~7::_---______________________________ --'

Sheet Inhibit

Strobe Timing MA 041

1 Addressing

FIGIaE SCM. MAIN STORAGE CONTIOt. _ TIMING CIRCUITS (SHEET 2 OF 2) So""

Fun Reg

CN=15

ction

I

ister

Note 1

Note 2

Note 3 P

P

i

I

-

_CE

~

0 1 2 3

i

0-3

CK

..

I

⁴

I

~

E Field 0- 3 lood Reg F

K Field Bit 0

Register 0-3

4 KPOOI

,

To Skew Control

Set By CN = 15 At T4 Del Reset By Relooding G

ROS Field

Note 1

Note 3

Note 2

I

{

. ^,

P

I

~ r

To Function Check Ckts

{ sel: Emit { F Re 0-3

Sel F

A

A

A

Control Register

,

CG

~

0 1

0 - 3

~

-

To Decoders For AlU Control

OR

Control latches Reset At T4 Del Special If Not Inhibit ALU Control

Control Register

CG Field Control Bits

Set Direct If CG = 0 (& Y8 =1) Or CG = 1 - 3 Boolean Expression

Position 0 Gland GO}

~ ~~

See Chart Opposite 3 Gl or GO

Select F Register If CG = 0 (and Y8=0) And CN

'f

15 Select Emit If CG = 0 (ond Y8=0)

AndCN=15

To Change Function Register & Use In Same Cycle,

P Or Q P And Q P Minus Q P Plus Q

Both Control And Function Resisters Set By Emit Field At T4 Delay.

Function Register Not Gated To Control Register Until After T4 Delay During Normal Operation.

Calling Select Emit Avoids Waiting For Function Register To Be Set And Then Setting The Control Register.

Bits

0 0

0 0 0 0 0

0 5 0

0 3 0 0

15 1

FIGURE 505. FUNCTION & CONTROL REGISTERS

2 3 0 0

0

CPU Logic

+J A

+ P 1

r--

OR A + P2

- J

...

_OR

~ f - - A - PI OR

- P2 ...

AVOOI

+J OR

- P2

- J A

+ P 2

AVOOI

- J

fBI

- P2 +J +P2

AVO 11

Bi t Position 0 Bi t Position 1

Bit Position 2 (Inversion)

FIGURE 506. DECIMAL FILLER

r-.

-P~ OR

+P~

r.--

^A

OR 'r-.

OR A OR

+ P2

Boolean Expression Decimal Add Operation

J PI P2 orJPI P2 JP2

Normal Operation

or JPI or JP2

+ PO

+ PI

2nd Level J

Not PO PI J Not PO P2 PO J Not PI Not P2 Not J PO

J Not P I Not P2 PI J P2 Not J PI

J NotP2 Not J P2

Note: Bit Position 3 Unchanged Bits 4-7 Not Shown As Logic Is Some As For Bits 0-3

A

f...- A

r--

^OR AlU Input P Bit 0 A

r--

A

AVOOI

A

-

A OR AlU Input P Bit I

-

A

AVOOI

A

OR ALU Input P Bit 2

-

A AVOOI

Binary Output Bit 0

A OR Binary Output Bit 1

Binary Output Bit 2 Binary Output Bit 0

-

A Not MSD Correct

Not Binary Output Bit 0

-

A Binary Output Bit 1

Not Binary Output. Bit 2 Binary Output Bit 3 MSD Correction

AV202

A R

Not BinaIY. Outp-ut Bit 2 MSD Correction

A Biner Out ut Bit 2

Not Bina Out ut Bit Not MSD Correct

A Binor Out ut Bit 1

AV202

AV202

A 0 Binar Out ut Bit 2

Not Bina Out ut Bit MSD Correction Not Bina Out ut Bit 0 MSD orrection Not Bina Out ut Bit 2

Not Binary Output Bit

a

Not Bino Out ut Bit 2

AL~ '-ontrol H Not ALU Carry Bit 0

Baalean Expression MSD A

A

AV202

A OR

AV202

Bit 0 0.1.2 + 0.1.2.3 Bit 1 1.2 + 1.2 Bit 2 Invert

Bit 3 No Change {Not 'Shown}

FIGURE 507 DECIMAL CORRECTION

A Bino Out ut Bit 6

ut Bit 4 ALU Out ut Bit

ALU Qutout Bit 0 A

AV212

A 0

Not Bina Out ut Bit 6

A

Binor Out ut Bit 6 ALU Out ut Bit

LSD Correction tic

A Bi a

AV212

A 0

LSD Corre tion

A Not Bi na Out ut Bit 6

AV212

AV212

A R

~D LSD Correction

Not ALU Car Bit 4

AV212 Boolean Expression LSD

Bit 4 4.5.6 Bit 5 5.6 + 5.6 Bit 6 Invert

Bit 7 No Change {Not Shown}