ZiLOG Worldwide Headquarters • 532 Race Street • San Jose, CA 95126-3432 Telephone: 408.558.8500 • Fax: 408.558.8300 •www.ZiLOG.com
User Manual
UM008003-1202
This publication is subject to replacement by a later edition. To determine whether a later edition exists, or to request copies of publications, contact:
ZiLOG Worldwide Headquarters 910 E. Hamilton Avenue
Campbell, CA 95008 Telephone: 408.558.8500 Fax: 408.558.8300 www.ZiLOG.com
Document Disclaimer
ZiLOG is a registered trademark of ZiLOG Inc. in the United States and in other countries. All other products and/or service names mentioned herein may be trademarks of the companies with which they are associated.
©2002 by ZiLOG, Inc. All rights reserved. Information in this publication concerning the devices, applications, or technology described is intended to suggest possible uses and may be superseded. ZiLOG, INC. DOES NOT ASSUME LIABILITY FOR OR PROVIDE A REPRESENTATION OF ACCURACY OF THE INFORMATION, DEVICES, OR TECHNOLOGY DESCRIBED IN THIS DOCUMENT. ZiLOG ALSO DOES NOT ASSUME LIABILITY FOR INTELLECTUAL PROPERTY INFRINGEMENT RELATED IN ANY MANNER TO USE OF INFORMATION, DEVICES, OR TECHNOLOGY DESCRIBED HEREIN OR OTHERWISE. Except with the express written approval of ZiLOG, use of information, devices, or technology as critical components of life support systems is not authorized. No licenses are conveyed, implicitly or otherwise, by this document under any intellectual property rights.
Table of Contents
Overview . . . .1
Architecture . . . .1
CPU Registers . . . .2
Arithmetic Logic Unit (ALU) . . . .5
Instruction Register and CPU Control . . . .6
Pin Description . . . .6
Overview . . . .6
Pin Functions . . . .7
Timing . . . .11
Overview . . . .11
Instruction Fetch . . . .12
Memory Read Or Write . . . .13
Input or Output Cycles . . . .14
Bus Request/Acknowledge Cycle . . . .15
Interrupt Request/Acknowledge Cycle . . . .16
Non-Maskable Interrupt Response . . . .17
HALT Exit . . . .18
Power-Down Acknowledge Cycle . . . .19
Power-Down Release Cycle . . . .20
Interrupt Response . . . .22
Overview . . . .22
Interrupt Enable/Disable . . . .22
CPU Response . . . .24
Hardware and Software Implementation Examples . . . . .27
Hardware . . . .27
Minimum System . . . .27
Adding RAM . . . .29
Memory Speed Control . . . .30
Interfacing Dynamic Memories . . . 31
Software Implementation Examples . . . 33
Overview of Software Features . . . 33
Examples of Specific Z80 Instructions . . . 34
Examples of Programming Tasks . . . 37
Z80 CPU Instruction Description . . . 41
Overview . . . 41
Instruction Types . . . 41
Addressing Modes . . . 44
Instruction Op Codes . . . 48
Z80 Instruction Set . . . 75
Z80 Assembly Language . . . 75
Z80 Status Indicator Flags . . . 76
Add/Subtract Flag . . . 77
Z80 Instruction Description . . . 80
8-Bit Load Group . . . 81
16-Bit Load Group . . . 102
Exchange, Block Transfer, and Search Group . . . 122
8-Bit Arithmetic Group . . . 140
General-Purpose Arithmetic and CPU Control Groups . . . 166
16-Bit Arithmetic Group . . . 179
Rotate and Shift Group . . . 190
Bit Set, Reset, and Test Group . . . 224
Jump Group . . . 238
Call And Return Group . . . 255
Input and Output Group . . . 269
List of Instructions
ADC A, s . . . .146
ADC HL, ss . . . .180
ADD A, (HL) . . . .143
ADD A, (IX + d) . . . .144
ADD A, (IY + d) . . . .145
ADD A, n . . . .142
ADD A, r . . . .140
ADD HL, ss . . . .179
ADD IX, pp . . . .182
ADD IY, rr . . . .183
AND s . . . .152
BIT b, (HL) . . . .226
BIT b, (IX+d) . . . .228
BIT b, (IY+d) . . . .230
BIT b, r . . . .224
CALL cc, nn . . . .257
CALL nn . . . .255
CCF . . . .170
CP s . . . .158
CPD . . . .137
CPDR . . . .138
CPI . . . .134
CPIR . . . .135
CPL . . . .168
DAA . . . .166
DEC IX . . . .188
DEC IY . . . .189
DEC m . . . .164
DEC ss . . . .187
DI . . . .174
DJNZ, e . . . .253
EI . . . 175
EX (SP), HL . . . 125
EX (SP), IX . . . 126
EX (SP), IY . . . 127
EX AF, AF' . . . 123
EX DE, HL . . . 122
EXX . . . 124
HALT . . . 173
IM 0 . . . 176
IM 1 . . . 177
IM 2 . . . 178
IN A, (n) . . . 269
IN r (C) . . . 270
INC (HL) . . . 161
INC (IX+d) . . . 162
INC (IY+d) . . . 163
INC IX . . . 185
INC IY . . . 186
INC r . . . 160
INC ss . . . 184
IND . . . 275
INDR . . . 277
INI . . . 272
INIR . . . 273
JP (HL) . . . 250
JP (IX) . . . 251
JP (IY) . . . 252
JP cc, nn . . . 239
JP nn . . . 238
JR NC, e . . . 244
JR C, e . . . 242
JR e . . . 241
JR NZ, e . . . 248
JR Z, e . . . 246
LD (BC), A . . . .95
LD (DE), A . . . .96
LD (HL), n . . . .89
LD (HL), r . . . .86
LD (IX+d), n . . . .90
LD (IX+d), r . . . .87
LD (IY+d), n . . . .91
LD (IY+d), r . . . .88
LD (nn), A . . . .97
LD (nn), dd . . . .110
LD (nn), HL . . . .109
LD (nn), IX . . . .111
LD (nn), IY . . . .112
LD A, (BC) . . . .92
LD A, (DE) . . . .93
LD A, (nn) . . . .94
LD A, I . . . .98
LD A, R . . . .99
LD dd, (nn) . . . .106
LD dd, nn . . . .102
LD HL, (nn) . . . .105
LD I,A . . . .100
LD IX, (nn) . . . .107
LD IX, nn . . . .103
LD IY, (nn) . . . .108
LD IY, nn . . . .104
LD r, (HL) . . . .83
LD r, (IX+d) . . . .84
LD r, (IY+d) . . . .85
LD R, A . . . .101
LD r, r' . . . .81
LD r,n . . . .82
LD SP, HL . . . .113
LD SP, IX . . . .114
LD SP, IY . . . 115
LDD . . . 131
LDDR . . . 132
LDI . . . 128
LDIR . . . 129
NEG . . . 169
NOP . . . 172
OR s . . . 154
OTDR . . . 286
OTIR . . . 283
OUT (C), r . . . 280
OUT (n), A . . . 279
OUTD . . . 285
OUTI . . . 282
POP IX . . . 120
POP IY . . . 121
POP qq . . . 119
PUSH IX . . . 117
PUSH IY . . . 118
PUSH qq . . . 116
RES b, m . . . 236
RET . . . 260
RET cc . . . 261
RETI . . . 263
RETN . . . 265
RL m . . . 202
RLA . . . 191
RLC (HL) . . . 196
RLC (IX+d) . . . 198
RLC (IY+d) . . . 200
RLC r . . . 194
RLCA . . . 190
RLD . . . 220
RR m . . . 208
RRA . . . .193
RRC m . . . .205
RRCA . . . .192
RRD . . . .222
RST p . . . .267
SBC A, s . . . .150
SBC HL, ss . . . .181
SCF . . . .171
SET b, (HL) . . . .233
SET b, (IX+d) . . . .234
SET b, (IY+d) . . . .235
SET b, r . . . .232
SLA m . . . .211
SRA m . . . .214
SRL m . . . .217
SUB s . . . .148
XOR s . . . .156
List of Figures
Figure 1. Z80 CPU Block Diagram . . . .2
Figure 2. Z80 CPU Register Configuration . . . .3
Figure 3. Z80 I/O Pin Configuration . . . .7
Figure 4. Basic CPU Timing Example . . . .12
Figure 5. Instruction Op Code Fetch . . . .13
Figure 6. Memory Read or Write Cycle . . . .14
Figure 7. Input or Output Cycles . . . .15
Figure 8. Bus Request/Acknowledge Cycle . . . .16
Figure 9. Interrupt Request/Acknowledge Cycle . . . .17
Figure 10. Non-Maskable Interrupt Request Operation . . . .18
Figure 11. HALT Exit . . . .19
Figure 12. Power-Down Acknowledge . . . .19
Figure 13. Power-Down Release Cycle No. 1 . . . .20
Figure 14. Power-Down Release Cycle No. 2 . . . .20
Figure 15. Power-Down Release Cycle No. 3 . . . .21
Figure 16. Mode 2 Interrupt Response Mode . . . .26
Figure 17. Minimum Z80 Computer System . . . .28
Figure 18. ROM and RAM Implementation . . . .29
Figure 19. Adding One Wait State to an M1 Cycle . . . .30
Figure 20. Adding One Wait State to Any Memory Cycle . . . .31
Figure 21. Interfacing Dynamic RAMs . . . .32
Figure 22. Shifting of BCD Digits/Bytes . . . .36
List of Tables
Table 1. Interrupt Enable/Disable, Flip-Flops . . . .24
Table 2. Bubble Listing . . . .37
Table 3. Multiply Listing . . . .39
Table 4. Hex, Binary, Decimal Conversion Table . . . .49
Table 5. 8-Bit Load Group LD . . . .51
Table 6. 16-Bit Load Group LD, PUSH and POP . . . .55
Table 7. Exchanges EX and EXX . . . .56
Table 8. Block Transfer Group . . . .58
Table 9. Block Search Group . . . .58
Table 10. 8-Bit Arithmetic and Logic . . . .60
Table 11. General-Purpose AF Operation . . . .61
Table 12. 16-Bit Arithmetic . . . .62
Table 13. Rotates and Shifts . . . .63
Table 14. Bit Manipulation Group . . . .66
Table 15. Jump, Call, and Return Group . . . .69
Table 16. Restart Group . . . .70
Table 17. Input Group . . . .72
Table 18. 8-Bit Arithmetic and Logic . . . .73
Table 19. Miscellaneous CPU Control . . . .73
Manual Objectives
This user manual describes the architecture and instruction set of the Z80 CPU.
About This Manual
ZiLOG recommends that the user read and understand everything in this manual before setting up and using the product. However, we recognize that users have different styles of learning: some will want to set up and use their new evaluation kit while they read about it; others will open these pages only to check on a particular specification. Therefore, we have designed this manual to be used either as a how to procedural manual or a reference guide to important data.
Intended Audience
This document is written for ZiLOG customers who are experienced at working with microprocessors or in writing assembly code or compilers.
Manual Organization
The Z80 CPU User’s Manual is divided into four chapters.
Overview
Presents an overview of the User’s Manual Architecture, Pin descriptions, timing and Interrupt Response.
Hardware and Software Implementation
Presents examples of the User’s Manual hardware and software.
Z80 CPU Instruction Description
Presents the User’s Manual instruction types, addressing modes and instruction Op Codes.
Z80 Instruction Set
Presents an overview of the User’s Manual assenbly language, status indicator flags and the Z80 instructions.
Related Documents
Manual Conventions
The following assumptions and conventions are adopted to provide clarity and ease of use:
Use of the Words Set and Clear
The words set and clear imply that a register bit or a condition contains the values logical 1 and logical 0, respectively. When either of these terms is followed by a number, the word logical may not be included, but it is implied.
Notation for Bits and Similar Registers
A field of bits within a register is designated as: Register (n–n). For example: PWM_CR (31–20). A field of bits within a bus is designated as:
Busn–n. For example: PCntl7–4. A range of similar (whole) registers is designated as: Registern–Registern. For example: OPBCS5–OPBCS0.
Part Number Title DC number
Part Number Title DC number
Part Number Title DC number
Use of the Terms LSB and MSB
In this document, the terms LSB and MSB, when appearing in upper case, mean least significant byte and most significant byte, respectively. The lowercase forms, msb and lsb, mean least significant bit and most significant bit, respectively.
Courier Font
Commands, code lines and fragments, register (and other) mnemonics, values, equations, and various executable items are distinguished from general text by the use of the Courier font. This convention is not used within tables. For example: The STP bit in the CNTR register must be 1. Where the use of the font is not possible, as in the Index, the name of the entity is presented in upper case.
Hexadecimal Values Designated by H
Hexadecimal values are designated by a uppercase H and appear in the Courier typeface. For example: STAT is set to F8H.
Use of All Uppercase Letters
The use of all uppercase letters designates the names of states and commands. For example: The receiver can force the SCL line to Low to force the transmitter into a WAIT state. The bus is considered BUSY after the Start condition. A START command triggers the processing of the initialization sequence.
Use of Initial Uppercase Letters
Initial uppercase letters designate settings, modes, and conditions in general text. For example: The Slave receiver leaves the data line High. In Transmit mode, the byte is sent most significant bit first. The Master can generate a Stop condition to abort the transfer.
Register Access Abbreviations
Register access is designated by the following abbreviations:
Trademarks
Z80, Z180, Z380 and Z80382 are trademarks of ZiLOG, Inc.
Designation Description
R Read Only
R/W Read/Write
W Write Only
– Unspecified or indeterminate
Overview
ARCHITECTURE
The ZiLOG Z80 CPU family of components are fourth-generation enhanced microprocessors with exceptional computational power. They offer higher system throughput and more efficient memory utilization than comparable second- and third-generation microprocessors. The speed offerings from 6–
20 MHz suit a wide range of applications which migrate software. The internal registers contain 208 bits of read/write memory that are accessible to the programmer. These registers include two sets of six general purpose registers which may be used individually as either 8-bit registers or as 16-bit register pairs. In addition, there are two sets of accumulator and flag registers.
The Z80 CPU also contains a Stack Pointer, Program Counter, two index registers, a REFRESH register, and an INTERRUPT register. The CPU is easy to incorporate into a system since it requires only a single +5V power source. All output signals are fully decoded and timed to control standard memory or peripheral circuits; the Z80 CPU is supported by an extensive family of peripheral controllers.
Figure 1 illustrates the internal architecture and major elements of the Z80 CPU.
Figure 1. Z80 CPU Block Diagram
CPU Registers
The Z80 CPU contains 208 bits of R/W memory that are available to the programmer. Figure 2 illustrates how this memory is configured to eighteen 8-bit registers and four 16-bit registers. All Z80 registers are implemented using static RAM. The registers include two sets of six general-purpose registers that may be used individually as 8-bit registers or in pairs as 16-bit registers. There are also two sets of accumulator and flag registers and six special-purpose registers.
CPU and13 System Control Signals
Inst.
Register
Data Bus Control
Internal Data Bus
RegistersCPU
ALU
ControlCPU
Address Control
16-Bit Address Bus +5V GND CLK
I n
Figure 2. Z80 CPU Register Configuration
Special-Purpose Registers
Program Counter (PC)
The program counter holds the 16-bit address of the current instruction being fetched from memory. The PC is automatically incremented after its contents have been transferred to the address lines. When a program jump occurs, the new value is automatically placed in the PC, overriding the incrementer.
Stack Pointer (SP)
The stack pointer holds the 16-bit address of the current top of a stack located anywhere in external system RAM memory. The external stack memory is organized as a last-in first-out (LIFO) file. Data can be pushed onto the stack from specific CPU registers or popped off of the stack to specific CPU registers through the execution of PUSH and POP
instructions. The data popped from the stack is always the last data pushed onto it. The stack allows simple implementation of multiple level interrupts,
General Purpose Registers Accumulator
H '
Special Purpose Registers Index Register
Index Register Stack Pointer Program Counter
Interrupt Vector I
H L L '
D E D ' E '
B C B ' B '
A F A ' F '
Flags Accumulator Flags Alternate Register Set Main Register Set
Memory Refresh R IX IY SP PC
unlimited subroutine nesting and simplification of many types of data manipulation.
Two Index Registers (IX and IY)
The two independent index registers hold a 16-bit base address that is used in indexed addressing modes. In this mode, an index register is used as a base to point to a region in memory from which data is to be stored or retrieved. An additional byte is included in indexed instructions to specify a displacement from this base. This displacement is specified as a two's complement signed integer. This mode of addressing greatly simplifies many types of programs, especially where tables of data are used.
Interrupt Page Address Register (I)
The Z80 CPU can be operated in a mode where an indirect call to any memory location can be achieved in response to an interrupt. The I register is used for this purpose and stores the high order eight bits of the indirect address while the interrupting device provides the lower eight bits of the address. This feature allows interrupt routines to be dynamically located anywhere in memory with minimal access time to the routine.
Memory Refresh Register (R)
The Z80 CPU contains a memory refresh counter, enabling dynamic memories to be used with the same ease as static memories. Seven bits of this 8-bit register are automatically incremented after each instruction fetch.
The eighth bit remains as programmed, resulting from an LD R, A
instruction. The data in the refresh counter is sent out on the lower portion of the address bus along with a refresh control signal while the CPU is decoding and executing the fetched instruction. This mode of refresh is transparent to the programmer and does not slow the CPU operation. The programmer can load the R register for testing purposes, but this register is normally not used by the programmer. During refresh, the contents of the I register are placed on the upper eight bits of the address bus.
Accumulator and Flag Registers
The CPU includes two independent 8-bit accumulators and associated 8-bit flag registers. The accumulator holds the results of 8-bit arithmetic or logical operations while the FLAG register indicates specific conditions for 8-bit or 1 16-bit operations, such as indicating whether or not the result of an operation is equal to zero. The programmer selects the accumulator and flag pair with a single exchange instruction so that it is possible to work with either pair.
General Purpose Registers
Two matched sets of general-purpose registers, each set containing six 8-bit registers, may be used individually as 8-bit registers or as 16-bit register pairs. One set is called BC, DE, and HL while the complementary set is called BC', DE', and HL'. At any one time, the programmer can select either set of registers to work through a single exchange command for the entire set. In systems that require fast interrupt response, one set of general- purpose registers and an ACCUMULATOR/FLAG register may be reserved for handling this fast routine. One exchange command is executed to switch routines. This greatly reduces interrupt service time by eliminating the requirement for saving and retrieving register contents in the external stack during interrupt or subroutine processing. These general-purpose registers are used for a wide range of applications. They also simplify programing, specifically in ROM-based systems where little external read/write memory is available.
Arithmetic Logic Unit (ALU)
The 8-bit arithmetic and logical instructions of the CPU are executed in the ALU. Internally, the ALU communicates with the registers and the external data bus by using the internal data bus. Functions performed by the ALU include:
•
Add•
Subtract•
Logical AND•
Logical OR•
Logical Exclusive OR•
Compare•
Left or Right Shifts or Rotates (Arithmetic and Logical)•
Increment•
Decrement•
Set Bit•
Reset Bit•
Test bitInstruction Register and CPU Control
As each instruction is fetched from memory, it is placed in the
INSTRUCTION register and decoded. The control sections performs this function and then generates and supplies the control signals necessary to read or write data from or to the registers, control the ALU, and provide required external control signals.
PIN DESCRIPTION Overview
The Z80 CPU I/O pins are illustrated in Figure 3 and the function of each is described in the following paragraphs.
Figure 3. Z80 I/O Pin Configuration
Pin Functions
A15–A0
Address Bus (output, active High, tristate). A15-A0 form a 16-bit address bus. The Address Bus provides the address for memory data bus exchanges (up to 64 Kbytes) and for I/O device exchanges.
System Control
CPUControl
CPUBus Control
Z80 CPU
Address Bus
DataBus A0
A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15
D0 D1 D3 D4 D5 D6 D7 D2 30
31 32 33 34 35 36 37 38 39 40
14 15 12 8 7 9 10 13 1 2 3 4 5 M1
MREQ IORQ RD WR RFSH HALT
INT NMI RESET BUSRQ BUSACK
CLK +5V GND WAIT
27 19 20 21 22
26 18 24 16 17 28
25 23
6 11 29
BUSACK
Bus Acknowledge (output, active Low). Bus Acknowledge indicates to the requesting device that the CPU address bus, data bus, and control signals MREQ, IORQ RD, and WR have entered their high-impedance states. The external circuitry can now control these lines.
BUSREQ
Bus Request (input, active Low). Bus Request has a higher priority than NMI and is always recognized at the end of the current machine cycle.
BUSREQ forces the CPU address bus, data bus, and control signals MREQ IORQ, RD, and WR to go to a high-impedance state so that other devices can control these lines. BUSREQ is normally wired-OR and requires an external pull-up for these applications. Extended BUSREQ periods due to extensive DMA operations can prevent the CPU from properly refreshing dynamic RAMS.
D7–D0
Data Bus (input/output, active High, tristate). D7–D0 constitute an 8-bit bidirectional data bus, used for data exchanges with memory and I/O.
HALT
HALT State (output, active Low). HALT indicates that the CPU has executed a HALT instruction and is waiting for either a non-maskable or a maskable interrupt (with the mask enabled) before operation can resume.
During HALT, the CPU executes NOPs to maintain memory refresh.
INT
Interrupt Request (input, active Low). Interrupt Request is generated by I/O devices. The CPU honors a request at the end of the current instruction if the internal software-controlled interrupt enable flip-flop (IFF) is enabled.
INT is normally wired-OR and requires an external pull-up for these applications.
IORQ
Input/Output Request (output, active Low, tristate). IORQ indicates that the lower half of the address bus holds a valid I/O address for an I/O read or write operation. IORQ is also generated concurrently with M1 during an interrupt acknowledge cycle to indicate that an interrupt response vector can be placed on the data bus.
M1
Machine Cycle One (output, active Low). M1, together with MREQ, indicates that the current machine cycle is the opcode fetch cycle of an instruction execution. M1 together with IORQ, indicates an interrupt acknowledge cycle.
MREQ
Memory Request (output, active Low, tristate). MREQ indicates that the address bus holds a valid address for a memory read of memory write operation.
NMI
Non-Maskable Interrupt (input, negative edge-triggered). NMI has a higher priority than INT. NMI is always recognized at the end of the current instruction, independent of the status of the interrupt enable flip-flop, and automatically forces the CPU to restart at location 0066H.
RD
Read (output, active Low, tristate). RD indicates that the CPU wants to read data from memory or an I/O device. The addressed I/O device or memory should use this signal to gate data onto the CPU data bus.
RESET
Reset (input, active Low). RESET initializes the CPU as follows: it resets the interrupt enable flip-flop, clears the PC and registers I and R, and sets the
interrupt status to Mode 0. During reset time, the address and data bus go to a high-impedance state, and all control output signals go to the inactive state. Notice that RESET must be active for a minimum of three full clock cycles before the reset operation is complete.
RFSH
Refresh (output, active Low). RFSH, together with MREQ indicates that the lower seven bits of the system’s address bus can be used as a refresh address to the system’s dynamic memories.
WAIT
WAIT (input, active Low). WAIT communicates to the CPU that the addressed memory or I/O devices are not ready for a data transfer. The CPU continues to enter a WAIT state as long as this signal is active. Extended WAIT periods can prevent the CPU from properly refreshing dynamic memory.
WR
Write (output, active Low, tristate). WR indicates that the CPU data bus holds valid data to be stored at the addressed memory or I/O location.
CLK
Clock (input). Single-phase MOS-level clock.
TIMING
Overview
The Z80 CPU executes instructions by stepping through a precise set of basic operations. These include:
•
Memory Read or Write•
I/O Device Read or Write•
Interrupt AcknowledgeAll instructions are series of basic operations. Each of these operations can take from three to six clock periods to complete or they can be lengthened to synchronize the CPU to the speed of external devices. The clock periods are referred to as T (time) cycles and the operations are referred to as M (machine) cycles. Figure 4 illustrates how a typical instruction is series of specific M and T cycles. Notice that this instruction consists of three machine cycles (M1, M2, and M3). The first machine cycle of any instruction is a fetch cycle which is four, five, or six T cycles long (unless lengthened by the WAIT signal, which is described in the next section). The fetch cycle (M1) is used to fetch the opcode of the next instruction to be executed. Subsequent machine cycles move data between the CPU and memory or I/O devices, and they may have anywhere from three to five T cycles (again, they may be lengthened by wait states to synchronize the external devices to the CPU). The following paragraphs describe the timing which occurs within any of the basic machine cycles.
During T2 and every subsequent Tw, the CPU samples the WAIT line with the falling edge of Clock. If the WAIT line is active at this time, another WAIT state is entered during the following cycle. Using this technique, the read can be lengthened to match the access time of any type of memory device.
Figure 4. Basic CPU Timing Example
Instruction Fetch
Figure 5 depicts the timing during an M1 (opcode fetch) cycle. The PC is placed on the address bus at the beginning of the M1 cycle. One half clock cycle later the MREQ signal goes active. At this time the address to the memory has had time to stabilize so that the falling edge of MREQ can be used directly as a chip enable clock to dynamic memories. The RD line also goes active to indicate that the memory read data should be enabled onto the CPU data bus. The CPU samples the data from the memory on the data bus with the rising edge of the clock of state T3 and this same edge is used by the CPU to turn off the RD and MREQ signals. Thus, the data has already been sampled by the CPU before the RD signal becomes inactive. Clock state T3 and T4 of a fetch cycle are used to refresh dynamic memories. The CPU uses this time to decode and execute the fetched instruction so that no other operation could be performed at this time.
During T3 and T4, the lower seven bits of the address bus contain a memory refresh address and the RFSH signal becomes active tindicating that a refresh read of all dynamic memories must be accomplished. An RD signal is not generated during refresh time to prevent data from different memory
CLK
T Cycle
Machine Cycle M1 (Opcode Fetch)
Instruction Cycle M2
(Memory Read) M3
(Memory Write)
T1 T2 T3 T1 T2 T3 T1 T2 T3
segments from being gated onto the data bus. The MREQ signal during refresh time should be used to perform a refresh read of all memory elements. The refresh signal can not be used by itself because the refresh address is only guaranteed to be stable during MREQ time.
Figure 5. Instruction Op Code Fetch
Memory Read Or Write
Figure 6 illustrates the timing of memory read or write cycles other than an Op Code fetch cycle. These cycles are generally three clock periods long unless wait states are requested by the memory through the WAIT signal.
The MREQ signal and the RD signal are used the same as in the fetch cycle.
In a memory write cycle, the MREQ also becomes active when the address bus is stable so that it can be used directly as a chip enable for dynamic memories. The WR line is active when data on the data bus is stable so that
PC Refresh Address
T1 T2 T3 T4 T1
M1 Cycle
CLK
D7 — D0 A15 — A0 MREQ
RD WAIT M1
RFSH
IN
it can be used directly as a R/W pulse to virtually any type of semiconductor memory. Furthermore, the WR signal goes inactive one-half T state before the address and data bus contents are changed so that the overlap
requirements for almost any type of semiconductor memory type is met.
Figure 6. Memory Read or Write Cycle
Input or Output Cycles
Figure 7 illustrates an I/O read or I/O write operation. During I/O operations a single wait state is automatically inserted. The reason is that during I/O operations, the time from when the IORQ signal goes active until the CPU must sample the WAIT line is very short. Without this extra state, sufficient time does not exist for an I/O port to decode its address and activate the WAIT line if a wait is required. Also, without this wait state, it is difficult to design MOS I/O devices that can operate at full CPU speed. During this wait state time, the WAIT request signal is sampled.
During a read I/O operation, the RD line is used to enable the addressed port onto the data bus just as in the case of a memory read. For I/O write operations, the WR line is used as a clock to the I/O port.
CLK
D7 — D0 A15 — A0 MREQ RD
WAIT WR
Memory Address Memory Address
T2 T3 T1 T2 T3
In
Memory Read Cycle Memory Write Cycle
Data Out
Figure 7. Input or Output Cycles
Bus Request/Acknowledge Cycle
Figure 8 illustrates the timing for a Bus Request/Acknowledge cycle. The BUSREQ signal is sampled by the CPU with the rising edge of the last clock period of any machine cycle. If the BUSREQ signal is active, the CPU sets its address, data, and tristate control signals to the high-impedance state with the rising edge of the next clock pulse. At that time, any external device can control the buses to transfer data between memory and I/O devices. (This operation is generally known as Direct Memory Access [DMA] using cycle stealing.) The maximum time for the CPU to respond to a bus request is the length of a machine cycle and the external controller can maintain control of the bus for as many clock cycles as is required. If very long DMA cycles are used, and dynamic memories are used, the external controller also performs the refresh function. This situation only occurs if very large blocks of data
Out
T1 T2 TW* T3 T1
Write Cycle Read Cycle Port Address
CLK
D7 — D0 A15 — A0 IORQ RD
WAIT
WR D7 — D0
*Automatically inserted WAIT state
In
are transferred under DMA control. During a bus request cycle, the CPU cannot be interrupted by either an NMI or an INT signal.
Figure 8. Bus Request/Acknowledge Cycle
Interrupt Request/Acknowledge Cycle
Figure 9 illustrates the timing associated with an interrupt cycle. The CPU samples the interrupt signal (INT) with the rising edge of the last clock at the end of any instruction. The signal is not accepted if the internal CPU software controlled interrupt enable flip-flop is not set or if the BUSREQ signal is active. When the signal is accepted, a special M1 cycle is generated. During this special M1 cycle, the IORQ signal becomes active (instead of the normal MREQ) to indicate that the interrupting device can place an 8-bit vector on the data bus. Two wait states are automatically added to this cycle. These states are added so that a ripple priority interrupt scheme can be easily implemented. The two wait states allow sufficient time for the ripple signals to stabilize and identify which
I/O device must insert the response vector. Refer to Chapter 6 for details on how the interrupt response vector is utilized by the CPU.
Sample Sample
Floating
Last T State TX TX TX T1
Any M Cycle Bus Available Status
CLK
D7 — D0 A15 — A0 BUSREQ
MREQ, RD BUSACK
WR. IORQ, RFSH
Figure 9. Interrupt Request/Acknowledge Cycle
Non-Maskable Interrupt Response
Figure 10 illustrates the request/acknowledge cycle for the non-maskable interrupt. This signal is sampled at the same time as the interrupt line, but this line takes priority over the normal interrupt and it can not be disabled under software control. Its usual function is to provide immediate response to important signals such as an impending power failure. The CPU response to a non-maskable interrupt is similar to a normal memory read operation.
The only difference is that the content of the data bus is ignored while the processor automatically stores the PC in the external stack and jumps to location 0066H. The service routine for the non-maskable interrupt must begin at this location if this interrupt is used.
In
Refresh PC
Last M Cycle of Instruction M1
CLK
D7 — D0 A15 — A0 INT
MREQ
RD WAIT
T1 T2 TW* TW* T3
M1
IORQ
Last T State
Figure 10. Non-Maskable Interrupt Request Operation
HALT Exit
Whenever a software HALT instruction is executed, the CPU executes NOPs until an interrupt is received (either a non-maskable or a maskable interrupt while the interrupt flip-flop is enabled). The two interrupt lines are sampled with the rising clock edge during each T4 state as depicted in Figure 11. If a non-maskable interrupt has been received or a maskable interrupt has been received and the interrupt enable flip-flop is set, then the HALT state is exited on the next rising clock edge. The following cycle is an interrupt acknowledge cycle corresponding to the type of interrupt that was received. If both are received at this time, then the non-maskable one is acknowledged since it has highest priority. The purpose of executing NOP instructions while in the HALT state is to keep the memory refresh signals active. Each cycle in the HALT state is a normal M1 (fetch) cycle except that the data received from the memory is ignored and a NOP instruction is forced internally to the CPU. The HALT acknowledge signal is active during this time indicating that the processor is in the HALT state.
CLK
A15 — A0 NMI
MREQ RD RFSH
T1 T2 T3
M1
Refresh M1
Last M Cycle Last T State
PC
T1 T4
Figure 11. HALT Exit
Power-Down Acknowledge Cycle
When the clock input to the CMOS Z80 CPU is stopped at either a High or Low level, the CMOS Z80 CPU stops its operation and maintains all registers and control signals. However, ICC2 (standby supply current) is guaranteed only when the system clock is stopped at a Low level during T4 of the machine cycle following the execution of the HALT instruction. The timing diagram for the power-down function, when implemented with the HALT instruction, is shown in Figure 12.
Figure 12. Power-Down Acknowledge
CLK
RD or HALT
T1 T2 T3
M1 T1 T4
NMI
HALT Instruction is repeated during this Memory Cycle
T4 T2
M1
CLK
HALT
T1 T2 T3 T1 T4
M1
T4 T2 T3
Power-Down Release Cycle
The system clock must be supplied to the CMOS Z80 CPU to release the power-down state. When the system clock is supplied to the CLK input, the CMOS Z80 CPU restarts operations from the point at which the power- down state was implemented. The timing diagrams for the release from power-down mode are featured in Figure 13 , 14 and 15.
When the HALT instruction is executed to enter the power-down state, the CMOS Z80 CPU also enters the HALT state. An interrupt signal (either NMI or ANT) or a RESET signal must be applied to the CPU after the system clock is supplied in order to release the power-down state.
Figure 13. Power-Down Release Cycle No. 1
Figure 14. Power-Down Release Cycle No. 2
CLK
HALT
T1 T2 T3 T1
M1
T4
NMI
CLK
HALT
T1 T2 T3
M1
T4
RESET
Figure 15. Power-Down Release Cycle No. 3
CLK
HALT
T1 T2 T3
M1
T4
INT
T1 T2 TWA TWA
INTERRUPT RESPONSE Overview
An interrupt allows peripheral devices to suspend CPU operation and force the CPU to start a peripheral service routine. This service routine usually involves the exchange of data, status, or control information between the CPU and the peripheral. When the service routine is completed, the CPU returns to the operation from which it was interrupted.
Interrupt Enable/Disable
The Z80 CPU has two interrupt inputs, a software maskable interrupt (INT) and a non-maskable interrupt (NMI). The non-maskable interrupt cannot be disabled by the programmer and is accepted whenever a peripheral device requests it. This interrupt is generally reserved for very important functions that can be enabled or disabled selectively by the programmer. This routine allows the programmer to disable the interrupt during periods when his program has timing constraints that do not allow interrupt. In the Z80 CPU, there is an interrupt enable flip-flop (IFF) that is set or reset by the
programmer using the Enable Interrupt (EI) and Disable Interrupt (DI) instructions. When the IFF is reset, an interrupt cannot be accepted by the CPU.
The two enable flip-flops are IFF1 and IFF2.
The state of IFF1 is used to inhibit interrupts while IFF2 is used as a temporary storage location for IFF1.
IFF1 IFF2
Disables interrupts from being accepted
Temporary storage location for IFF1
A CPU reset forces both the IFF1 and IFF2 to the reset state, which disables interrupts. Interrupts can be enabled at any time by an EI instruction from the programmer. When an EI instruction is executed, any pending interrupt request is not accepted until after the instruction following EI is executed.
This single instruction delay is necessary when the next instruction is a return instruction. Interrupts are not allowed until a return is completed. The EI instruction sets both IFF1 and IFF2 to the enable state. When the CPU accepts a maskable interrupt, both IFF1 and IFF2 are automatically reset, inhibiting further interrupts until the programmer issues a new El
instruction. Note that for all of the previous cases, IFF1 and IFF2 are always equal.
The purpose of IFF2 is to save the status of IFF1 when a non-maskable interrupt occurs. When a non-maskable interrupt is accepted, IFF1 resets to prevent further interrupts until reenabled by the programmer. Thus, after a non-maskable interrupt is accepted, maskable interrupts are disabled but the previous state of IFF1 has been saved so that the complete state of the CPU just prior to the non-maskable interrupt can be restored at any time. When a LoadRegisterAwithRegisterI (LDA, I) instruction or a Load RegisterAwithRegisterR (LDA, R) instruction is executed, the state of IFF2 is copied to the parity flag where it can be tested or stored.
A second method of restoring the status of IFF1 is through the execution of a ReturnFromNon-MaskableInterrupt (RETN) instruction. This instruction indicates that the non-maskable interrupt service routine is complete and the contents of IFF2 are now copied back into IFF1 so that the status of IFF1 just prior to the acceptance of the non-maskable interrupt is restored automatically.
Table 1 is a summary of the effect of different instructions on the two enable flip-flops.
Table 1. Interrupt Enable/Disable, Flip-Flops
Action IFF1 IFF2 Comments
CPU Reset 0 0 Maskable Interrupt, INT Disabled
CPU Response
Non-Maskable
The CPU always accepts a non-maskable interrupt. When this occurs, the CPU ignores the next instruction that it fetches and instead performs a restart to location 0066H. The CPU functions as if it had recycled a restart instruction, but to a location other than one of the eight software restart locations. A restart is merely a call to a specific address in page 0 of memory.
The CPU can be programmed to respond to the maskable interrupt in any one of three possible modes.
Mode 0
This mode is similar to the 8080A interrupt response mode. With this mode, the interrupting device can place any instruction on the data bus and the CPU executes it. Thus, the interrupting device provides the next instruction to be executed. Often this is a restart instruction because the interrupting device only need supply a single byte instruction. Alternatively, any other DI Instruction Execution 0 0 Maskable INT Disabled
EI Instruction Execution 1 1 Maskable, INT Enabled LD A,I Instruction Execution * * IFF2 ® Parity Flag LD A,R instruction Execution * * IFF2 ® Parity Flag
Accept NMI 0 * MaskableInterrupt
RETN Instruction Execution IFF2 * IFF2 ®indicates completion of non- maskable interrupt service routine.
Table 1. Interrupt Enable/Disable, Flip-Flops
Action IFF1 IFF2 Comments
instruction such as a 3-byte call to any location in memory could be executed.
The number of clock cycles necessary to execute this instruction is two more than the normal number for the instruction. This occurs because the CPU automatically adds two wait states to an Interrupt response cycle to allow sufficient time to implement an external daisy-chain for priority control. Figure 9 and Figure 10 illustrate the detailed timing for an interrupt response. After the application of RESET, the CPU automatically enters interrupt Mode 0.
Mode 1
When this mode is selected by the programmer, the CPU responds to an interrupt by executing a restart to location 0038H. Thus, the response is identical to that for a non-maskable interrupt except that the call location is 0038H instead of 0066H. The number of cycles required to complete the restart instruction is two more than normal due to the two added wait states.
Mode 2
This mode is the most powerful interrupt response mode. With a single 8-bit byte from the user, an indirect call can be made to any memory location.
In this mode, the programmer maintains a table of 16-bit starting addresses for every interrupt service routine. This table may be located anywhere in memory. When an interrupt is accepted, a 16-bit pointer must be formed to obtain the desired interrupt service routine starting address from the table.
The upper eight bits of this pointer is formed from the contents of the I register. The I register must be loaded with the applicable value by the programmer, such as LDI, A. A CPU reset clears the I register so that it is initialized to zero. The lower eight bits of the pointer must be supplied by the interrupting device. Only seven bits are required from the interrupting device because the least-significant bit must be a zero. This is required
because the pointer is used to get two adjacent bytes to form a complete 16- bit service routine starting address and the addresses must always start in even locations.
Figure 16. Mode 2 Interrupt Response Mode
The first byte in the table is the least-significant (low order portion of the address). The programmer must complete this table with the correct addresses before any interrupts are accepted.
The programmer can change this table by storing it in Read/Write Memory, which also allows individual peripherals to be serviced by different service routines.
When the interrupting device supplies the lower portion of the pointer, the CPU automatically pushes the program counter onto the stack, obtains the starting address from the table, and performs a jump to this address. This mode of response requires 19 clock periods to complete (seven to fetch the lower eight bits from the interrupting device, six to save the program counter, and six to obtain the jump address).
The Z80 peripheral devices include a daisy-chain priority interrupt structure that automatically supplies the programmed vector to the CPU during interrupt acknowledge. Refer to the Z80 CPU Peripherals User Manual for more complete information.
Starting Address Pointed to by:
I Register
Contents Seven Bits From Peripheral 0 Low Order
High Order Interrupt
Service Routine Starting Address Table
Hardware and Software Implementation Examples
HARDWARE
Minimum System
This chapter is an introduction to implementing systems that use the Z80 CPU. Figure 1 illustrates a simple Z80 system.
Any Z80 system must include the following elements:
•
5V Power Supply•
Oscillator•
Memory Devices•
I/O Circuits•
CPUFigure 1. Minimum Z80 Computer System
Because the Z80 CPU requires only a single 5V power supply, most small systems can be implemented using only this single supply.
The external memory can be any mixture of standard RAM, ROM, or PROM. In Figure 1, a single 8K bit ROM (1 Kbytes) comprises the entire memory system. The Z80 internal register configuration contains sufficient Read/Write storage, requiring no external RAM memory.
I/O circuits allow computer systems to interface with the external devices.
In Figure 1, the output is an 8-bit control vector and the input is an 8-bit status word. The input data can be gated to the data bus using any standard three-state driver while the output data can be latched with any type of stan- dard TTL latch. A Z80 PIO serves as the I/O circuit. This single circuit attaches to the data bus as indicated and provides the required 16 bits of TTL compatible I/O. (Refer to the Z80 CPU Peripherals User’s Manual for details on the operation of this circuit.) This powerful computer is built with only three LSI circuits, a simple oscillator, and a single 5V power supply.
RESET
+5V Z80
CPU
M1 IORQ Data Bus RD MREQ
A9–A0 +5V
DataOUT GND Address
IN +5V Power Supply
CLK
A0 A1 M1
IORQ CE RD
Output Data OSC
CLK
Input Data C/D B/A Z80-PIO
Port A Port B CE1
CE2 8K BitROM
Adding RAM
Most computer systems require some external Read/Write memory for data storage and stack implementation. Figure 2 illustrates how 256 bytes of static memory are added to the previous example in Figure 1. The memory space is assumed to be organized as follows:
In this diagram the address space is described in hexadecimal notation.
Address bit A10 separates the ROM space from the RAM space, allowing this address to be used for the chip select function. For larger amounts of external ROM or RAM, a simple TTL decoder is required to form the chip selects.
Figure 2. ROM and RAM Implementation
1 Kbyte ROM
Address:
0000H 03FFH 0400H 04FFFH 256 Bytes RAM
CE1
CE2 ROM 1K x 8 MREQ • RD
A10
A7–A0
D7–D0
WR RD
R/W OD
CE2 A10 A7–A0
D3–D0 CE1
WR RD
R/W MRQ OD
Data Bus
D7–D4 Address Bus
A7–A0
RAM 256 x 4
RAM 256 x 4
A10 MRQ
CE2 CE1
Memory Speed Control
Slow memories can reduce costs for many applications. The WAIT line on the CPU allows the Z80 to operate with any speed memory. Memory access time requirements, which are covered in Chapter A3, are most severe during the M1 cycle instruction fetch. All other memory access cycles complete in an additional one half clock cycle. Hence, it is sometimes appropriate to add one wait state to the M1 cycle so slower memories can be used. Figure 3 is an example of a simple circuit that accomplishes this objective. This circuit can be changed to add a single wait state to any memory access as indicated in Figure 4.
Figure 3. Adding One Wait State to an M1 Cycle
+5V D C
Q
R Q S
7474
+5V D C
Q
R Q S
7474 +5V
M1 CLK
WAIT
CLK
M1 WAIT
M1
T1 T2 TW T3 T4
Figure 4. Adding One Wait State to Any Memory Cycle
Interfacing Dynamic Memories
Each individual dynamic RAM has it’s own specifications that require minor modifications to the examples given here. ZiLOG Application Notes are available describing how the Z80 CPU is interfaced with most popular dynamic RAM.
Figure 5 illustrates the logic necessary to interface 8 Kbytes of dynamic RAM using 18-pin 4K dynamic memories. This logic assumes that the RAMs are the only memory in the system so that A12 is used to select between the two pages of memory. During refresh time, all memories in the system must be read. The CPU provides the correct refresh address on lines A0 through A6. When adding more memory to the system, it is necessary to replace only the two gates that operate on A12 with a decoder that oper- ates on all required address bits. Address buffers and data bus buffers are generally required for larger systems.
+5V D C
Q
R Q S
7474
+5V D
C Q
R Q S 7474
+5V
MREQ CLK
+5V
7400 WAIT
WAIT MREQ CLK
T1 T2 TW
Figure 5. Interfacing Dynamic RAMs
WR
R/W
R/W
CE
CE 4K x 8 RAM Array
Page 0 (0000 to 0FFFF) 4K x 8 RAM Array
Data Bus
Page 1 (1000 to 1FFFF) D7–D0
A11–A0 RFSH MREQ
A12
SOFTWARE IMPLEMENTATION EXAMPLES Overview of Software Features
The Z80 instruction set provides the user with a large number of operations to control the Z80 CPU. The main alternate and index registers can hold arithmetic and logical operations, form memory addresses, or act as fast- access storage for frequently used data.
Information can be moved directly from register to register, from memory to memory, from memory to registers, or from registers to memory. In addi- tion, register contents and register/memory contents can be exchanged without using temporary storage. In particular, the contents of main and alternate registers can be completely exchanged by executing only two instructions, EX and EXX. This register exchange procedure can be used to separate the set of working registers from different logical procedures or to expand the set of available registers in a single procedure.
Storage and retrieval of data between pairs of registers and memory can be controlled on a last-in first-out basis through PUSH and POP instructions that utilize a special STACK POINTER register (SP). This stack register is available both to manipulate data and to automatically store and retrieve addresses for subroutine linkage. When a subroutine is called, for example, the address following the CALL instruction is placed on the top of the push- down stack pointed to by SP. When a subroutine returns to the calling routine, the address on the top of the stack is used to set the program counter for the address of the next instruction. The stack pointer is adjusted automatically to reflect the current top stack position during PUSH, POP, CALL, and RET instructions. This stack mechanism allows pushdown data stacks and subroutine calls to be nested to any practical depth because the stack area can potentially be as large as memory space.
The sequence of instruction execution can be controlled by six different flags (carry, zero, sign, parity/overflow, add/subtract, half-carry), which reflect the results of arithmetic, logical, shift, and compare instructions.
After the execution of an instruction that sets a flag, that flag can be used to control a conditional jump or return instruction. These instructions provide logical control following the manipulation of single bit, 8-bit byte, or 18-bit data quantities.
A full set of logical operations, including AND, OR, XOR (exclusive-OR), CPL (NOR), and NEG (two’s complement) are available for Boolean opera- tions between the accumulator and all other 8-bit registers, memory loca- tions, or immediate operands.
In addition, a full set of arithmetic and logical shifts in both directions are available which operate on the contents of all 8-bit primary registers or directly on any memory location. The carry flag can be included or set by these shift instructions to provide both the testing of shift results and to link register/register or register/memory shift operations.
Examples of Specific Z80 Instructions
Example One:
When a 737-byte data string in memory location DATA must be moved to location BUFFER, the operation is programmed as follows:
LD HL, DATA ;START ADDRESS OF DATA STRING LD DE, BUFFER;START ADDRESS OF TARGET BUFFER LD BC, 737 ;LENGTH OF DATA STRING
LDIR ;MOVE STRING - TRANSFER MEMORY POINTED
;TO BY HL INTO MEMORY LOCATION POINTED
;TO BY DE INCREMENT HL AND DE,
;DECREMENT BC PROCESS UNTIL BC = 0.
Eleven bytes are required for this operation and each byte of data is moved in 21 clock cycles.
