We are on the edge of a revolution in the way We are on the edge of a revolution in the way

(1)

System Design Paradigms System Design Paradigms

Alberto Sangiovanni Vincentelli Alberto Sangiovanni Vincentelli The Edgar L. and Harold H.

The Edgar L. and Harold H. Buttner Buttner Chair of Chair of Electr Electr. Eng. and Comp. Science. Eng. and Comp. Science University of California at Berkeley

University of California at Berkeley

Co-Founder, Chief Technology Advisor and Board Member Co-Founder, Chief Technology Advisor and Board Member

Cadence Design System Cadence Design System Founder and Scientific Director Founder and Scientific Director PARADES (Cadence, Magneti-Marelli, ST) PARADES (Cadence, Magneti-Marelli, ST)

PARADES

Electronics and the Car Electronics and the Car

•More than 30% of the cost of a car is now in Electronics

•90% of all innovations will be based on electronic systems

(2)

June 9, 2000 3

Outline Outline

We are on the edge of a revolution in the way We are on the edge of a revolution in the way

electronics systems are designed.

◆◆

Electronic Systems Electronic Systems

◆◆

Platform-based Design Platform-based Design

◆◆

Embedded Software Embedded Software

Chips Everywhere!

CMOS Camera

Source: Dr. K. Pister, UC Berkeley

Chips that Fly?

(3)

June 9, 2000 5

Computing Revolution: Devices in the

Computing Revolution: Devices in the eXtreme eXtreme

Evolution

Information Appliances:

Scaled down desktops, e.g., CarPC, PdaPC, etc.

Evolved Desktops Servers:

Scaled-up Desktops,

Revolution

Information Appliances:

Many computers per person, MEMs, CCDs, LCDs, connectivity

Servers: Integrated with comms infrastructure;

Lots of computing in small footprint

Display

Keyboard Disk Mem

µ^Proc PC Evolution

Display Display

Camera

SmartSensors

Camera

Smart Spaces

Computing Revolution WAN

Server, Mem, Disk Information

Utility

BANG!

Display

Mem

Disk µ^Proc

The Distributed Approach to Information Processing The Distributed Approach to Information Processing

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June 9, 2000 7

Productivity Gap Productivity Gap

How are we going to solve the challenge of How are we going to solve the challenge of Design?

Design?

◆◆Design ScienceDesign Science

◆◆Collaboration!Collaboration!

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June 9, 2000 10

Challenges Challenges

Fact Fact

◆

◆ Total NumberTotal Number of Design of Design Starts will Starts will decrease decrease

◆

◆ Complexity perComplexity per Design Start is Design Start is going up going up

Shift to Shift to

◆

◆ Reuse StrategyReuse Strategy

◆

◆ Higher Level ofHigher Level of Abstractions Abstractions

◆

◆ Software !!!Software !!!

Challenge: Design Flow Predictability Challenge: Design Flow Predictability

nd

Design Time

% Errors found

Objective Objective

▲

▲Find bugs and criticalFind bugs and critical bottlenecks at the earliest bottlenecks at the earliest possible time

possible time

▲

▲Avoid error propagationAvoid error propagation

▲

▲Shorter time to marketShorter time to market

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June 9, 2000 12

Challenge: Productivity Challenge: Productivity

System Definition

& Partitioning

HW Development

Driver SW Dev Application

SW Dev Wait on Prototype

37% 20% 31% 12%

System Specification &

Design

HW & SW Design & Debug

Prototype Debug System Test Integrate

HW/SW

Derivative Designs

Software Configurable 3x - 5x

Derivative

Designs 100%-150%

HW/SW Co-Development

25%

Manufacturing Cost and Design Cost Manufacturing Cost and Design Cost

◆

◆Manufacturing costs skyrocketingManufacturing costs skyrocketing

▲▲Mask set cost alone predicted to be $1.5M to $10MMask set cost alone predicted to be $1.5M to $10M

◆

◆Design cost increasing exponentially with size of designDesign cost increasing exponentially with size of design 10% Decrease in ASIC starts for 1999 w.r.t. 1998.

10% Decrease in ASIC starts for 1999 w.r.t. 1998.

Must re-consider how design is carried out: re-use is Must re-consider how design is carried out: re-use is

main concern at all levels:

Platform-based Design

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June 9, 2000 14

Integration Platforms…

… the next step in the Evolution of Design Reuse

◆

◆ In TDD, Reuse in ASIC design is of In TDD, Reuse in ASIC design is of Cell-level LibrariesCell-level Libraries

◆◆ In BBD, Reuse in hierarchical design is of In BBD, Reuse in hierarchical design is of major IP Blocksmajor IP Blocks (e.g., digital blocks (e.g., digital blocks built out of standard cells)

built out of standard cells)

◆◆ In SOC, Reuse is of In SOC, Reuse is of Collections of IP blocksCollections of IP blocks organized into HW-SW organized into HW-SW architectures: also known as

architectures: also known as Integration PlatformsIntegration Platforms

ASIC Complex ASIC

with a few IP’s

Plug and Play System-On-Chip

Logic ^MPEG

SRAM

ROM Data Cache

Serial Interface

uP Core

ATM ROM SRAM

ROM

Soft I/F IP

mainstream

Timing Driven Design (TDD)

Block Based Design (BBD)

Platform-Based SOC Design Logic

Logic

ROM uP Core

Platform-based Design Platform-based Design

◆◆Build upon tools, methods and abstractionsBuild upon tools, methods and abstractions

“We rest on the shoulders of the past. We are midgets on the

“We rest on the shoulders of the past. We are midgets on the shoulders of giants”, Francis Bacon,

shoulders of giants”, Francis Bacon, Novum OrganumNovum Organum

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June 9, 2000 16

Platform-based Design Platform-based Design

◆◆Abstractions are layers upon layersAbstractions are layers upon layers

Platform-based Design Platform-based Design

◆◆The mapping between layers are the pillars of the platformThe mapping between layers are the pillars of the platform

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June 9, 2000 18

Platform-based Design Platform-based Design

◆

◆The mapping between layers are the pillars of the platformThe mapping between layers are the pillars of the platform

Platform-based Design Platform-based Design

A platform is the combination of abstraction layers and A platform is the combination of abstraction layers and (manual, partially or fully automated) methods for the (manual, partially or fully automated) methods for the mapping

mapping

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June 9, 2000 20

Hardware Platforms Hardware Platforms

Hardware Platform

Hardware Platform: not only a fully specified SoC but : not only a fully specified SoC but aa family of architectures that share some common feature family of architectures that share some common feature::

A Hardware Platform is a family of architectures that satisfy A Hardware Platform is a family of architectures that satisfy a set of architectural constraints imposed to allow the re- a set of architectural constraints imposed to allow the re- use of hardware and software components.

use of hardware and software components.

◆

◆The stronger the constraints the more component re-useThe stronger the constraints the more component re-use butbut

◆

◆stronger constraints imply fewer architectures to choosestronger constraints imply fewer architectures to choose from!

from!

Architecture Family: PC platform Architecture Family: PC platform

◆◆PC hardware platform most successful application ofPC hardware platform most successful application of platform concept for re-use

platform concept for re-use

▲

▲x86 ISA (makes it possible to re-use OS and software applicationsx86 ISA (makes it possible to re-use OS and software applications at binary level)

at binary level)

▲▲fully specified set of busses (ISA, USB, PCI)fully specified set of busses (ISA, USB, PCI)

▲▲fully specified set of I/O devicesfully specified set of I/O devices

◆

◆Too rigid (and expensive) for embedded systemToo rigid (and expensive) for embedded system applications!!!

applications!!!

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June 9, 2000 22

Application-Specific SOC Integration Platforms Application-Specific SOC Integration Platforms

Application-Specific IP*

Foundation IP*

Foundry-Specific Pre-Qualification

Scaleable HW-SW Architectures:

Processors On-Chip Buses Test, Power, IO,Clock

RTOS’s SW Architecture

System Level Design and Verification

Environment:

HW and SW Rapid Prototyping capability

System Level Design and Verification

Environment:

HW and SW Rapid Prototyping capability IP

HW: Digital, AMS Hard, Firm, Soft SW: Source, Object

IP HW: Digital, AMS

Hard, Firm, Soft SW: Source, Object

Fixed Hardware Kernel

Reconfigurable Hardware Region (FPGA, LPGA, …) Variable Region

Digital Wireless Platform Digital Wireless Platform

A D Analog RF

Timing recovery

phone book

Java VM

ARQ

Keypad, Display

Control

Filters^AdaptiveAntenna Algorith ms Equalizers MUD Accelerators

(bit level)

analog digital

DSP core uC core (ARM)

Logic

Dedicated Logic and Memory

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June 9, 2000 24

Building a Platform Instance Building a Platform Instance

•

Peripheral^M/S

Processor MEMC

Periph Processor Periph

Peripheral ^M

M/S ^M Peripheral^M/S ^M/SPeripheral

Peripheral^M/S ^M/SPeripheral ^M ^M Peripheral^M/S ^M/SPeripheral

DMA Gate M

M/S M DMA GateM/S

Crossover Bridge^M/S M/S

Bridge Bridge

Peripheral^M/S ^M/SPeripheral^M/S ^M/SPeripheral^M/S ^M/SPeripheral

•

Bridge Tunnel Bridge

Tunnel

DTL DTL DTL DTL

MEMC MEMC

•

Peripheral^M/S

Processor MEMC

Peripheral ^M

DMA Gate M

M/S M DMA GateM/S

Bridge Bridge

•

Tunnel

DTL DTL DTL DTL

MEMC MEMC

•

Peripheral^M/S

Processor MEMC

Peripheral ^M

DMA Gate M

M/S M DMA GateM/S

Bridge Bridge

•

Tunnel

DTL DTL DTL DTL

MEMC MEMC

•

Peripheral^M/S

Processor MEMC

Peripheral ^M

Peripheral^M/S ^M/SPeripheral ^M ^M/SPeripheral

DMA Gate M

M/S M DMA GateM/S

Bridge Bridge

Peripheral^M/S ^M/SPeripheral^M/S ^M/SPeripheral

•

MEMC MEMC

•

Peripheral^M/S

Processor MEMC

Peripheral ^M

Peripheral^M/S ^M/SPeripheral ^M ^M/SPeripheral

DMA Gate M

M/S M DMA GateM/S

Bridge Bridge

Peripheral^M/S ^M/SPeripheral^M/S ^M/SPeripheral

•

MEMC MEMC

Peripheral ^M M/S

Peripheral M M/S

Peripheral^M/S M

Peripheral^M/S Peripheral^M/S

Peripheral M/S

Put it all together De-configure: Remove unwanted components Extend: Add in prototyped (FPGA) components

Platforms Platforms

Application Space Application Instance

System Design Space Exploration Specification

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June 9, 2000 26

Hardware Platforms Not Enough!

◆

◆Hardware platform has to be “extended” upwards to beHardware platform has to be “extended” upwards to be really effective in time-to-market

really effective in time-to-market

◆◆Interface to the application software is APIInterface to the application software is API

◆◆Software layer performs abstraction:Software layer performs abstraction:

▲

▲Programmable cores and memory subsystem with (RT)OSProgrammable cores and memory subsystem with (RT)OS

▲▲I/O subsystem via Device DriversI/O subsystem via Device Drivers

▲▲Microsoft Windows OS and API is an example!Microsoft Windows OS and API is an example!

◆

◆In the end; if we solve the HW design productivity and failIn the end; if we solve the HW design productivity and fail to address the SW productivity we have accomplished to address the SW productivity we have accomplished little.

little.

◆

◆System design productivity is the objective.System design productivity is the objective.

Why the Software Productivity Concern??

HW Effort

SW Effort

(14)

June 9, 2000 28

Software Platforms Software Platforms

Output Devices Input devices

Hardware Platform

I O

Hardware Software

network Software Platform

Application Software

Platform API

Software Platform

RTOS

BIOS Device Drivers

Network Communication

Compilers

Platforms Platforms

Platform Design-Space Exploration Platform Specification

Application Space Application Instance

System Platform

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June 9, 2000 30

Output Devices Input devices

Hardware Platform

I O

Hardware

network

DUAL-CORE

RTOS

BIOS Device Drivers

DUAL-CORE

Architectural Space (Performance)

Application Space (Features)

Platform Definition Platform Definition

Platform Instance Application Instances

System Platform (no ISA)

Platform Design Space Exploration Platform Specification

Platform API

Software Platform

Hardware Platform

I O

Hardware

network HITACHI

RTOS

BIOS Device Drivers

HITACHI

RTOS

BIOS Device Drivers

Hardware Platform

I O

Hardware

network ST10

RTOS

BIOS Device Drivers

ST10 Application Software

Application Software

How is a platform chosen?

◆◆Needs extensive analysis to optimize among competingNeeds extensive analysis to optimize among competing criteria

criteria

◆◆Performance vs. cost vs. re-use (time-to-market) vs.Performance vs. cost vs. re-use (time-to-market) vs.

flexibility flexibility

◆◆Millions of parts are needed to be profitable!Millions of parts are needed to be profitable!

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June 9, 2000 33

System Design: High Leverage Paradigms System Design: High Leverage Paradigms

◆◆Orthogonalization of concerns: view designs alongOrthogonalization of concerns: view designs along axes that can be dealt with independently

axes that can be dealt with independently

▲▲Timing and functionalityTiming and functionality

▲▲Function and ArchitectureFunction and Architecture

▲▲ComputationComputation and and

Communication Communication

Separate Behavior from Micro-architecture Separate Behavior from Micro-architecture

Front Front End End 11

Transport Transport Decode Decode 22

Rate Rate Buffer Buffer 12 12

Sensor Sensor Synch Synch Control Control 4 4

Video Video Decode Decode 66

User/Sys User/Sys Control Control 3 3 Mem Mem 13 13

Frame Frame Buffer Buffer 7 7

Video Video Output Output 88

◆

◆System BehaviorSystem Behavior

▲▲Functional Specification ofFunctional Specification of System.

System.

▲▲No notion of hardware orNo notion of hardware or software!

software!

◆◆Implementation ArchitectureImplementation Architecture

▲▲Hardware and SoftwareHardware and Software

▲

▲Optimized ComputerOptimized Computer

DSP RAM DSP RAM External

External I/O I/O

DSP DSP Processor Processor

Processor BusProcessor Bus

Control Control Processor Processor MPEG

MPEG

Peripheral Peripheral

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June 9, 2000 36

IP-Based Design of Implementation IP-Based Design of Implementation

System System RAM RAM DSPDSP Processor Processor

Processor Bus Processor Bus

Control Control Processor Processor MPEGMPEG

Peripheral Peripheral Audio Audio Decode Decode

Which DSP Processor? C50?

Can DSP be done on Micro-controller?

Which Bus? PI?

AMBA?

Dedicated Bus for DSP?

Which Micro-controller?

ARM? HC11?

Do I need a dedicated Audio Decoder?

Can decode be done on Micro-controller?

How fast will my User Interface Software run? How Much can I fit on my Micro-controller?

Can I Buy an MPEG2 Processor?

Which One?

Map Between Behavior from Architecture Map Between Behavior from Architecture

Front Front End End 11

Transport Transport Decode Decode 22

Sensor Sensor Synch Synch Control Control 4 4

Video Video Decode Decode 66

User/Sys User/Sys Control Control 3 3 Mem Mem 13 13

Frame Frame Buffer Buffer 7 7

Video Video Output Output 88

Transport Decode Implemented as Software Task Running

on Microcontroller

DSP DSP Processor Processor

Processor BusProcessor Bus

Control Control Processor Processor MPEG

MPEG

Peripheral Peripheral

Communication Over Bus

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June 9, 2000 39

IP Block Authoring

Synthesis / Place & Route etc.

Two Basic Questions … Two Basic Questions … Question I - IP Authoring Question I - IP Authoring

How to design a system block?

▲▲Starting from the system levelStarting from the system level

▲

▲With a consistent test-benchWith a consistent test-bench

▲

▲Getting from the abstract, un-timedGetting from the abstract, un-timed system model to the clocked HW or system model to the clocked HW or SW implementation model SW implementation model Example

Example

◆

◆ Rake ReceiverRake Receiver

▲

▲Which are the optimal algorithms?Which are the optimal algorithms?

▲

▲How does it work fixed point?How does it work fixed point?

▲▲How is it best implemented?How is it best implemented?

▲

▲Does the implementation work asDoes the implementation work as specified in the system level specified in the system level Implementation Level Verification

Block Implementation Iterative Refinement Executable System Level Block Level Specification

IP Block Definition Embedded System Requirements

Two Basic Questions … Two Basic Questions … Question II – IP Integration Question II – IP Integration

How to integrate system blocks?

▲

▲Starting from the system levelStarting from the system level

▲

▲With a consistent test-benchWith a consistent test-bench

▲

▲Getting from the abstract, un-timedGetting from the abstract, un-timed system model to the clocked HW or system model to the clocked HW or SW implementation model SW implementation model

▲▲Communication between blocksCommunication between blocks

▲▲Addressing Platform Based designAddressing Platform Based design Example

Example

◆

◆ 3G Cell phone3G Cell phone

▲

▲Which are the optimal algorithms?Which are the optimal algorithms?

▲

▲Do they work together functionally?Do they work together functionally? _Hardware _Software Communication Refinement Communication Integration Performance Analysis and

Platform Configuration System Integration Platform

Function

Platform Architecture

IP Block System Integration

Embedded System Requirements

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June 9, 2000 41

The new approach The new approach

◆

◆Not the typical stepwise top-down refinement: we rest onNot the typical stepwise top-down refinement: we rest on platforms!

platforms!

◆◆Explicit mapping of applications onto architectureExplicit mapping of applications onto architecture components

components

◆◆The higher the level of abstraction, the faster is the designThe higher the level of abstraction, the faster is the design timetime

Functional IP Integration Functional IP Integration

Untimed Algorithm Integration

SPW, C++, C, SDL, Matlab

Does the functionally

integrated design work?

Executable Functional Specification

◆◆ Question: How does the functional integrated design work?Question: How does the functional integrated design work?

◆

◆ VCC allowsVCC allows

▲

▲to importto import functional IP from different sources functional IP from different sources

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June 9, 2000 44

Functional IP Integration Functional IP Integration

Visualization Functional Integration and Simulation

Untimed Algorithm Integration

SPW, C++, C, SDL, Matlab

FSM IP Authoring

Architectural IP Integration Architectural IP Integration

◆

◆ Question: What does the system architecture look like?Question: What does the system architecture look like?

◆

◆ VCC allowsVCC allows

▲

▲to model architectural IPto model architectural IP at the system level at the system level

▼

▼CPU, DSP, RTOS, Bus, Memory and dedicated HW/SWCPU, DSP, RTOS, Bus, Memory and dedicated HW/SW

▲

▲to integrateto integrate the the architectural modelsarchitectural models defining the platform defining the platform Architecture

Performance

PerformanceUntimed

Algorithm Integration

SPW, C++, C, SDL, Matlab

Executable Functional Specification CPU, DSP

Bus, Memory, RTOS, HW, SW

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June 9, 2000 46

Architectural Integration

Architectural IP Integration Architectural IP Integration

Architecture Performance

PerformanceUntimed

SPW, C++, C, SDL, Matlab

Executable Functional Specification CPU, DSP

Bus, Memory, RTOS, HW, SW

API for architectural components

New Research Plan: Logical Infrastructure for New Research Plan: Logical Infrastructure for System Level Design and Verification

System Level Design and Verification

◆

◆Models of computation: new theory that will make itModels of computation: new theory that will make it possible to link different models of computation possible to link different models of computation

◆◆Platform definition with rigorous formalism about levels ofPlatform definition with rigorous formalism about levels of abstraction and mapping

abstraction and mapping

◆◆Three basic components of the frameworkThree basic components of the framework

▲▲Proof managerProof manager

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June 9, 2000 48

System Design: High Leverage Paradigms System Design: High Leverage Paradigms

◆◆Orthogonalization of concerns: view designs alongOrthogonalization of concerns: view designs along axes that can be dealt with independently

axes that can be dealt with independently

▲▲Timing and functionalityTiming and functionality

▲▲Function and ArchitectureFunction and Architecture

▲▲ComputationComputation and and

Communication Communication

Key Problem: Ad Hoc Integration Key Problem: Ad Hoc Integration

◆◆ Bus structures inadequate forBus structures inadequate for global SOC quality of service global SOC quality of service needs

needs

◆

◆ Excessive interdependencyExcessive interdependency between blocks

between blocks

◆◆ Incomplete information for front-Incomplete information for front- end modeling

end modeling Conventional SOC

Custom Interfaces

Bridge

DMA CPU DSP

Mem Ctrl.

MPEG

C I O O

System Bus

Peripheral Bus

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June 9, 2000 50

DSP MPEG CPU

C MEM I O

Sonics Integration Architecture (SonicsIA Sonics Integration Architecture (SonicsIA

^™^™

) ) Features

Features

SiliconBackplane Agent^™

Open Core Protocol^™(OCP)

SiliconBackplane^™ (patented)

MultiChip Backplane^™

• Provides critical decoupling

(latency, bandwidth, frequency, address map, data width, protocol, control flow, etc.)

• Configures specifically to application

• Highly scalable bandwidth

• Fully observable and controllable

{

DMA

Bottom Line: Component Reuse Bottom Line: Component Reuse

◆

◆The Challenge Is Not in the IP Itself, but is in theThe Challenge Is Not in the IP Itself, but is in the Component Integration Protocols

Component Integration Protocols

▲

▲It’s not just a “standard bus” problemIt’s not just a “standard bus” problem

▲▲This is true for hardware, software, and so/This is true for hardware, software, and so/rdwarerdware components

components

◆

◆Design Validation Remains the Key Bottleneck andDesign Validation Remains the Key Bottleneck and

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June 9, 2000 52

Communication-based Design Communication-based Design

MacroShells (the Protocol Interface) Communication Channels

MicroShells (the IP Requirements) P1

P2

P3

P4

P5

P6

P7 Pearls (the IP Processes)

∞ C

APP: Write, Read ( port, vector of «ANY» data-type )

Function (zero-delay)

P

COSY Communication Refinement COSY Communication Refinement

SYS: set channel parameters to Tradeoff Speed versus Memory Size

P C

Function mapped to HW or SW (delay)

◆Abstract from the concerns of HW or SW implementation ( multi-target VC )

P C

VCI: «ANY BUS» Write, Read (address, data chunk)

◆ Abstract from the concerns of a particular bus ( bus-independent VC )

P C

PHY: Physical-Bus protocol, e.g.

PIBUS

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June 9, 2000 54 Does the

refined design work?

Communication Refinement

Abstract Token Abstract Token

Refined Integrated

Design

Clocked

Performance

CPU, DSP Bus, Memory, RTOS, HW, SW

Are performance &

partitioning sufficient?

Executable Performance Specification

Untimed

SPW, C++, C, SDL, Matlab

Communication Refinement Communication Refinement

from Tokens to Signals from Tokens to Signals

MPEG Video Decoder I/F

Timers MPEG Audio Decoder

Graphics Engine

uC

On-Chip Ram D-Cache

I-Cache

Abstract Token

Abstract Token Communication Refinement

Key Technology Key Technology

Communication Refinement Communication Refinement

Communication Refinement Flow To Implementation

Mapping System Behavior

System Architecture

Performance Simulation Behavior Simulation

2 1

3

4

Refinement from abstract tokens to articulated signals Refinement from abstract tokens to articulated signals Value

Value

▲

▲Design and Design and simulatesimulate at the level of at the level of abstraction at which designers abstraction at which designers think (e.g. ATM cell, GSM frame) think (e.g. ATM cell, GSM frame)

▲

▲hide implementation details of thehide implementation details of the communication until it is required communication until it is required (but simulate it’s overhead!) (but simulate it’s overhead!)

▲

▲refine from abstract token levelrefine from abstract token level

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June 9, 2000 56

Refined Integrated

Design Communication Pattern

Communication Synthesis Communication Synthesis

MPEG Video Decoder

MPEG Audio Decoder

Bus/Cache Control

uC CPU I/Os Drivers

Bus I/F Drivers

Software Tasks

Does the refined design

work?

Communication Refinement

Abstract Token Abstract Token

Clocked

Performance

CPU, DSP Bus, Memory, RTOS, HW, SW

Are performance &

partitioning sufficient?

Executable Performance Specification

Untimed

SPW, C++, C, SDL, Matlab

Communication Pattern Synthesis

VCC Model VCC Model to RTOS Protocol Component

Bus Slave to VCC Model Component VCC Model RTOS

RTOS to CPU Protocol Component

Communication Refinement Flow To Implementation

Mapping System Behavior

System Architecture

Performance Simulation Behavior Simulation

2 1

3

4

Key Technology Key Technology

Communication Interface Synthesis Communication Interface Synthesis

Synthesize communication pattern through architecture Synthesize communication pattern through architecture Value

Value

▲

▲Choose from comprehensive set ofChoose from comprehensive set of communication pattern

communication pattern

▲▲Pattern for HW-SWPattern for HW-SW, , SW-HWSW-HW, , HW-HWHW-HW and SW-SWand SW-SW communication communication available

available

▲▲move function between HW and SWmove function between HW and SW boundaries and

boundaries and re-synthesizere-synthesize the the communication interface

communication interface

▲

▲customize platform communicationcustomize platform communication environment through JAVA scripts environment through JAVA scripts

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June 9, 2000 58

Outline Outline

We are on the edge of a revolution in the way We are on the edge of a revolution in the way

electronics systems are designed.

◆◆

Electronic Systems for the car Electronic Systems for the car

◆◆

Platform-based Design Platform-based Design

◆◆

Embedded Software Embedded Software

◆

◆In the end; if we solve the HW design productivity and failIn the end; if we solve the HW design productivity and fail to address the SW productivity we have accomplished to address the SW productivity we have accomplished little.

little.

◆

◆System design productivity is the objective.System design productivity is the objective.

Why the Software Productivity Concern??

HW Effort

SW Effort