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Design and Fabrication of an RF Power

LDMOSFET on SOI

by

James G. Fiorenza

B.S. Rensselaer Polytechnic Institute (1994)

M.S. Rensselaer Polytechnic Institute (1996)

Submitted to the Department of Electrical Engineering and Computer

Science

in partial fulfillment of the requirements for the degree of

Doctor of Philosophy in Electrical Engineering

at the

MASSACHUSETTS INSTITUTE OF TECHNOLOGY

September 2002

©

Massachusetts Institute of Technology 2002. All rights reserved.

A uthor ...

...

Departmen'of Electrical Engineering and Uomputer Science

September 4, 2002

Certified by...

Jesus A. del Alamo

Professor

Twesis Supervisor

Accepted by ...

Arthur C. Smith

Chairman, Department Committee on Graduate Students

ARKEai

,

MASSACHUSETTS INSTITUTE OF TECHNOLOGY

NOV 1

8 2002

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Design and Fabrication of an RF Power LDMOSFET on SOI

by

James G. Fiorenza

Submitted to the Department of Electrical Engineering and Computer Science on September 4, 2002, in partial fulfillment of the

requirements for the degree of

Doctor of Philosophy in Electrical Engineering

Abstract

This thesis studied thin-film Silicon-on-Insulator (SOI) LDMOSFET technology for RF power amplifier applications. To conduct this study, two generations of SOI RF power devices for portable wireless systems were designed and fabricated. Bulk silicon LDMOSFETs were also made and used as a bench-mark for comparison with the SOI LDMOSFETs. A metal/polysilicon damascene gate process was developed to reduce the gate resistance and achieve high RF power gain. The advantages and disadvantages of SOI for RF power applications were analyzed using these devices.

This research showed that the primary advantage of SOI in RF power applica-tions was the reduction of RF substrate loss due to the presence of the buried oxide.

SOI was shown to reduce both drain substrate loss and pad substrate loss. Both

contributed to an improvement in the device's power efficiency. An improvement of

5 percentage points of efficiency was demonstrated relative to bulk LDMOSFETs at 1.9 GHz. The SOI devices achieved excellent performance: over 62 % PAE at 1.9

GHz with 200 mW of output power at a Vdd of 3.6 V.

The two main disadvantages of SOI in RF power applications were reduced break-down voltage and increased self-heating effects, but this research showed that they do not limit the device performance. Adequate on-state breakdown voltage was achieved through the use of an under-source body contact. Self-heating did not affect amplifier performance even with 500 mW of output power from a single power cell.

High-resistivity (2000 Q-cm) bulk silicon and SOI substrates were explored in an effort to achieve additional reductions in substrate loss in RF power LDMOSFETs. High-resistivity bulk silicon reduced drain substrate loss and significantly increased efficiency relative to bulk silicon. High-resistivity SOI did not significantly reduce drain substrate loss or increase efficiency over standard SOI. The reason for this was the presence of an inversion layer at the buried oxide/handle wafer interface. This inversion layer shunted RF drain current to ground, muting the benefit of high-resistivity SOI.

Thesis Supervisor: Jesu's A. del Alamo Title: Professor

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Acknowledgments

I met many extraordinary people during my time at MIT. I will never forget their contributions to my work and their impact on my life.

It was a privilege to work with Prof. Jesu's A. del Alamo. His enthusiasm for research and dedication to education was a constant source of inspiration. I thank him most of all for his absolute insistence on excellence. He is a man who sets high goals and leads by example. I am also grateful for the opportunity to work with Prof. Dimitri A. Antoniadis. I appreciate his simple advice, straight forward approach, and constant focus on what is most important. I thank Prof. Judy L. Hoyt for her contributions as a reader and for the discussions of my work.

I have made many friends at MTL, and I thank them for keeping life interesting. Thanks to Samuel Mertens, Niamh Waldron, Andy Fan, Joyce Wu, Joerg Scholvin, Isaac Lauer, Fletch Freeman, John Kymissis, Andy Ritenour, and Matthew Varghese. I also want to thank some of the old-timers who helped me get started at MIT, including Roxann Blanchard, Mark Somerville, Mark Armstrong, Andy Wei, and Keith Jackson. I was also fortunate to have met a few visiting scientists and post-docs. I thank Joerg Appenzeller, Joachim Knoch, Duheon Song, and Tetsuya Suemitsu. I learned a lot from each of them. I also thank Andy Fan, John Fiorenza, Don Hitko, Joerg Scholvin, Tassannee Payakapan, Jihye Whang, Tim Savas, John Kymissis, and Andrew Chen for directly contributing to my research.

I have many fond memories of my time with friends from the MTL. We played some sports: soccer, softball, hockey, and had an occasional football game between the Device Dorks and the Circuit Geeks. We spent some time sitting in the lounge, eating truck food and arguing about politics. And we did some work: staying up for a night in the ICL listening to '80s music and trying desperately to finish photo, or struggling with the CMP machine while praying that it doesn't turn my wafers into sand.

This thesis would not have been possible without the work of the staff of the MTL. I thank most of all Paul Tierney, Dan Adams, Bernard Alamariu, and Joe Walsh.

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They were great to work with and each contributed significantly to the success of this thesis.

I thank the SRC and DARPA for funding this work. I also acknowledge

con-tributions from Cabot Microelectronics and Rodel which enabled the metal CMP work, and from IBM, M/A-COM, ACCO, and ST-Microelectronics for allowing me to access their load-pull equipment. I thank Gordon Ma and Keith Jenkins for their suggestions as SRC mentors. I am grateful to Susan Sweeny, Chuck Webster, Dave Wandrei, and Dan Gleason for their help with the load-pull measurements.

I thank Kim Tresch for her support, encouragement, and friendship, and for always

believing me when I said I was almost done. I thank her father, Dick Tresch, for reading my thesis.

I am grateful for the support of my family. Thanks to the The Kids; Paul, Jen, Mat, Nick, Monica, and John; and to The Parents, Ann and Bob Fiorenza, to whom

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1 Introduction

1.1 RF Power Amplifiers in Wireless Communication Systems

1.2 Bulk Silicon LDMOSFETs for RF Power Amplifiers . . .

1.3

1.4

RF LDMOSFET on SOI . . . . Thesis Goals . . . .

2 Design of an RF LDMOSFET on Thin-Film SOI

2.1 Introduction

2.2 RF Power Amplifier Figures-of-Merit . . .

2.2.1 Gain, Efficiency, and Output Power 2.2.2 Linearity . . . .

2.2.3 Robustness . . . . 2.2.4 RF Power Measurements . . . .

2.2.5 Using RF Power Characteristics in.

2.3 DC Device Design . . . . 2.3.1 Gate Oxide Specification . . . .

2.3.2 Body Doping Design . . . .

2.3.3 LDD Design . . . . 2.3.4 On-State Breakdown . . . . 2.4 Designing for RF power . . . . 2.4.1 Modeling RF Power Performance . 2.4.2

2.4.3

Device Design

The Effect of Gate Resistance on RF Power Performance The Effect of Substrate Loss on RF Power Performance .

Contents

25 . . . . 25 28 31 35 37 37 38 38 40 41 41 43 43 47 48 57 61 66 66 70 74

. . . .

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2.5 Conclusion . . . .

3 First Generation LDMOSFET Fabrication Process and Electrical Characterization

3.1 Introduction . . . .

3.2 Fabrication Process and Layout . . . .

3.2.1 Fabrication Process . . . . 3.2.2 Layout . . . . 3.3 Electrical Characterization . . . . 3.3.1 DC Characteristics . . . . 3.3.2 Drain Capacitance . . . . 3.3.3 S-parameters . . . . 3.3.4 Load-Pull Measurements . . . . 3.4 Conclusion . . . .. 4 Second Generation LDMOSFET Fabrication Process

Characterization

4.1 Introduction . . . ..

4.2 Fabrication Process . . . . 4.2.1 Process Flow . . . . 4.2.2 Metal/Polysilicon Damascene Gate Process . . . 4.3 Electrical Characterization . . . . 4.3.1 Introduction . . . . 4.3.2 Metal/Polysilicon Damascene Gate Results . . .

and Electrical 107 107 108 108 110 116 116 116

4.3.3 Characterization of LDMOSFETs on High Resistivity Substrates119 4.4 4.5 Best Results . . . . Conclusion . . . . 126 128 5 Conclusion 129

5.1 Design of an RF Power LDMOSFET . . . . 129 5.2 Thin-Film SOI for RF Power. . . . . 130 79 81 81 81 81 85 88 88 94 95 96 104

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5.3 Summary Conclusion . . . . 131

A Comparison of the Under Source Body Contact to the Striped Body Contact 133 B A simple model of an RF PA 137 B .1 Introduction . . . . 137

B.2 Solution Derivation in Amplifier Linear Region . . . . 140

B.3 Solution Derivation in Compression . . . . 143

B.4 Adding the Effect of Drain Substrate Loss . . . . 145

C First Generation SOI LDMOSFET Process 149

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List of Figures

1-1 Diagram of a cellular telephone system. The distance between the handset and base station can be large. A high power signal is required to create a link. . . . 26

1-2 Block diagram of a cellular handset. The RF power amplifier consumes a large portion of the total transceiver power. . . . . 27

1-3 Block diagram of an RF PA. It has only a few components: input and output matching networks, input and output bias networks, and a semiconductor transis-tor. . . . . 2 7

1-4 Picture of an RF LDMOSFET from Motorola [1]. The features include a laterally diffused body, lightly doped drain, p+ sinker, and a low resistance gate. . . . . 29

1-5 PAE of bulk silicon LDMOSFET PAs in the literature. Dotted lines separate the

results at different frequencies. The frequency of operation has increased from about 1 GHz to 5 GHz over time, and the PAE at each frequency has also increased. 30

1-6 Schematic cross-section of an RF LDMOSFET on thin-film SOI. . . . . 31

1-7 PAE of bulk silicon LDMOSFETs and SOI MOSFETs in the literature. SOI

MOS-FETs have achieved high PAE. . . . . 33

1-8 PAE of bulk silicon LDMOSFETs and SOI MOSFETs in the literature as a function

of their output power. Previous SOI devices have been made with only low power levels. The SOI LDMOSFETs in this work have high PAE and power levels greater than 500 m W . . . . 34

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2-1 Typical characteristics of an RF power amplifier. Results are from on-wafer load-pull measurements of a W9 = 36 x 90 pm power cell. Vdd = 3.6 V, bias, = 10

mA/mm, frequency = 1.9 GHz. Input and output matching were set for maximum PA E . . . . . 39 2-2 Typical linearity characteristics of an RF power amplifier. Results are from

on-wafer load-pull measurements of a W9 = 36 x 90 prm power cell. Vdd = 3.6 V,

Ibias = 10 mA/mm, frequency = 1.9 GHz. ACPR measurements were done using

the 3GPP standard with a channel spacing of 5 MHz and an adjacent channel bandwidth and a reference bandwidth of 3.84 MHz. Input and output matching were set to maximize PAE and minimize ACPR. . . . . 40 2-3 Depiction of a load-pull system used for measurement of the RF power

character-istics of a transistor. It consists of all of the components of an RF power amplifier other than the transistor. . . . . 42 2-4 Schematic cross-section of an RF LDMOSFET on thin-film SOI. Important

dimen-sions are labeled. . . . .. . 44

2-5 Closer view of the cross-section of an RF LDMOSFET on thin-film SOI. . . . . 44

2-6 Depiction of the five basic steps in an LDMOSFET fabrication process. .... 45

2-7 Simulated three dimensional plot of the doping in an SOI LDMOSFET. The im-portant features of the LDMOSFET are the n+ source/drain doping, the p-type laterally-diffused body, and the n- LDD region. The gate was at the surface of the silicon (y = 0) and extended from x = 0 to x = 0.6 pm. . . . . 49 2-8 Simulated horizontal cross-section of SOI LDMOSFET doping beneath the source,

drain, and gate at the surface of the silicon. The body is doped with boron, the source/drains with arsenic, and the LDD with phosphorous. . . . . 49 2-9 Simulation of the doping beneath the source. The implants were designed to create

a p-type region above the buried oxide and beneath the n+ source. The p-type link region creates an under-source body contact (USBC). . . . . 50

2-10 Simulation of the doping beneath the drain. The implants were designed so that the silicon remains n-type above the buried oxide on the drain side. . . . . 50

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2-11 Simulation of a comparison of the body doping for a one hour body doping anneal time and a twelve hour body doping anneal time. The simulated temperature of the anneal was 1000 "C. A lower anneal time produces a more narrow body doping profile. . . . . 5 1

2-12 Simulation of the horizontal electric field in the SOI LDMOSFET channel for one hour and twelve hour body doping anneal times. The shorter anneal time results in a higher electric field near the source in saturation. The drain voltage in the simulation was 3.6 V. . . . . 52

2-13 Simulated comparison of the subthreshold characteristics of an SOI LDMOSFET

with a one hour body doping anneal and with a twelve hour body doping anneal. The device with a shorter body doping anneal has a lower threshold voltage. . . 52

2-14 Simulated comparison of the transconductance of an SOI LDMOSFET with a one hour body doping anneal time and with a twelve hour body doping anneal time. The device with a shorter body doping anneal time has a higher transconductance because it has a higher horizontal electric field near the source. . . . . 53

2-15 Simulated comparison of the output conductance of an SOI LDMOSFET with a

one hour body doping anneal time and with a twelve hour body doping anneal time. The device with a shorter body doping anneal time has higher output conductance because it has higher DIBL. . . . . 53

2-16 The simulated threshold voltage and DIBL for different body anneal times. A

shorter anneal time yielded an SOI LDMOSFET with a lower threshold voltage and higher DIBL. . . . . 55

2-17 The simulated transconductance and output conductance for different body anneal

times. A shorter anneal time yields an SOI LDMOSFET with a higher transcon-ductance and a higher output contranscon-ductance. The drain voltage was 3.6 V. The transconductance was the maximum value. The output conductance was extracted at a drain current of 50 mA/mm. . . . . 55

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2-18 The simulated ft and intrinsic voltage gain for different body anneal times. A

shorter anneal time yields a device with a higher ft because of the higher transcon-ductance. A shorter anneal time yields a device with a lower intrinsic gain because the increase in transconductance is counter-acted by a drop in the output conduc-tance. The drain voltage in the simulation was 3.6 V. The ft that is plotted is the maximum simulated value at that drain voltage. The intrinsic voltage gain was extracted at 50 mA/mm. . . . .

56

2-19 The simulated source and body resistance for different body anneal times. Neither

are influenced greatly by the body doping anneal time. . . . .

56

2-20 The simulated on-resistance and off-state breakdown voltage for different body anneal times. The on-resistance increased moderately for long anneal times because the p-type body doping counter-dopes the n-type LDD doping. The on-resistance was extracted for a gate voltage of 15 V and a drain voltage of 0.1 V. . . . . .

57

2-21 Simulated electric field in an SOI LDMOSFET at the surface of the silicon under the gate and in the LDD region. The drain voltage was 15 V and the gate voltage was 0 V. The peak of the electric field causes off-state breakdown and occurs at the drain edge of the gate. The peak electric field can be reduced by using a low dose LDD implant. . . . . 58

2-22 Simulation of the off-state breakdown voltage for different LDD length and dose. The off-state breakdown voltage increases for a low LDD dose and a long LDD. .

59

2-23 Simulation of the resistance of the LDD region for different LDD lengths and doses.

Decreasing the LDD dose and increasing the LDD length has a penalty: the LDD resistance increases, which increases the on-resistance. . . . . 60

2-24 Simulated electric field contours of an SOI LDMOSFET with a drain voltage of 15 V and a gate voltage of 0 V. The peak electric field occurs near the surface of the silicon and is therefore not affected by the presence of the SOI buried oxide. . .

60

2-25 Illustration of the currents involved with on-state breakdown in an SOI

LDMOS-FET. The body resistance plays a critical role in on-state breakdown. . . . . . 61 2-26 Circuit diagram depicting the mechanism of on-state breakdown. . . . . 62

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2-27 Illustration of the two types of body contacts that have been used with thin-film SOI

LDMOSFETs: the under-source body contact (a), and the striped body contact

(b). The under-source body contact was implemented in this work. . . . .

64

2-28 Simulation of the drain current versus the drain voltage for different levels of body

contact resistance. The kink occurred for high values of the body contact resistance. The on-state breakdown voltage was also reduced for high values of body contact resistance. The gate voltage was 3.5 V. . . . .

65

2-29 Simplified model of an RF power amplifier. The RF power device is modeled by

only Rg,Cg,, Gm, and GP. An exact solution of this circuit is derived in Appendix B . . . . . 6 7

2-30 Calculated RF power characteristics of a class-B PA. Vdd= 3.6 V, frequency = 2

GHz. The characteristics qualitatively match measured data (compare to Fig. 2-1).

68

2-31 Calculated RF power characteristics as a function of the output matching

resis-tance, Rm. The choice of Rm affects the gain, output efficiency, output power and

PAE. A low Rm gives high output power, but low gain and efficiency. A high Rm

gives low output power, but high gain. Vdd = 3.6 V, frequency = 2 GHz. . . . . 69 2-32 RF LDMOSFET power cell. Many gate, source, and drain fingers are connected

together to produce high output power. Interconnect metal and metal pads are an unavoidable parasitic component of the cell layout. . . . . 71 2-33 Complete RF power LDMOSFET layout for high power applications. Many RF

power cells are connected together if a single cell does not produce sufficient output pow er. . . . . 71

2-34 Maximum PAE for different gate resistance levels. High gate resistance reduces the maximum PAE. Vdd= 3.6 V, frequency = 2 GHz. . . . . 72 2-35 Maximum gain and output efficiency for different gate resistance levels. High gate

resistances reduced gain, but not output efficiency. Vdd= 3.6 V, frequency = 2 GHz. ... ... ... 73

2-36 RF interconnect model showing mechanism of RF substrate loss on silicon. The

model consists of three elements: Cseries, Csub, and Rsub. RF power is consumed in R8ub when an RF signal is applied to the metal. . . . .

75

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2-37 Depiction of the translation of a physical substrate loss model to a parallel model.

The parallel model is useful because the power consumed by the substrate is directly proportional to the conductance, G,. . . . .

75

2-38 Calculation of RF substrate loss as a function of substrate resistance. RF substrate

loss can be minimized by making the substrate resistance very high or very low.

GP was calculated from the estimated drain substrate network circuit of a W9 =

36 x 90 pm SOI LDMOSFET. . . . . 76

2-39 A schematic cross-section of an SOI LDMOSFET with a substrate network which

models two sources of RF substrate loss: drain substrate loss, and drain pad sub-strate loss. . . . .. . .

77

2-40 Maximum PAE for different levels of substrate loss at the output of the PA. PAE is significantly reduced by loss at the output of an RF power amplifier. Vdd = 3.6

V, frequency = 2 GHz. . . . . 78

2-41 Maximum gain and output efficiency for different substrate loss levels. Both gain and output efficiency are reduced by substrate loss at the output. . . . . 78

3-1 Depiction of the first generation SOI LDMOSFET process flow. The process was adapted from an NMOS process flow and was designed to be inserted into an SOI

CM OS process. . . . . 83 3-2 Cross-section of a first generation LDMOSFET on thin-film SOI. The drawn gate

length was 1 pm, drift length was 0.5 pm, silicon thickness was 200 nm and the buried oxide was 400nm. . . . . 84

3-3

Cross-section of a 1st generation LDMOSFET on bulk silicon. The fabrication

process of the bulk LDMOSFET was identical to the fabrication process of the SOI LDM OSFET. . . . .. 84 3-4 Layout of a two-fingered LDMOSFET. Drawn gate length is 1 pm, drift length is

0.5 pm and finger length is 20 pm . . . . 85 3-5 Layout of a two-fingered LDMOSFET showing pads designed for 100 Pm pitch

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3-6 Layout of a 10 fingered LDMOSFET power cell with pads designed for co-planar probes. The layout of a power cell with more than two fingers requires that the gate crosses the source. In the first generation LDMOSFETs this was enabled by

a polysilicon underpass. . . . . 87 3-7 Output characteristics of an LDMOSFET on thin-film SOI and bulk silicon. The

characteristics are similar, but there are some differences. The most significant difference is that the LDMOSFET on SOI has a lower on-state breakdown voltage. Device width was W9 = 20x40 pm and the gate voltage is stepped between 0 and 3.5 V in 0.5 V steps. . . . . 89

3-8

Transfer characteristics of a bulk silicon and SOI LDMOSFET. Device size was W9

= 20x40 pm and Vd, is 3.6 V. . . . . 90

3-9 On-resistance of LDMOSFETs on thin film SOI and bulk silicon. Device size was

W9 = 20x40 pm and VdS = 0.05 V . . . . 91

3-10 A picture of a bulk LDMOSFET during soft breakdown. Light emission occurred

at the intersection between the LOCOS edge and the edge of the gate near the drain. Neither soft breakdown nor light emission occurred in the LDMOSFETs on

SOI. Device size was W9 = 2x40 pum, Vgs = 0 V, and Vd8 = 18 V . . . . 92 3-11 A picture of a bulk LDMOSFET during soft breakdown. The intensity of the light

emission increased with increasing drain voltage. Device size was W9 = 2x40 pm,

Vgs = 0 V, and Vds = 23.5V . . . . 93

3-12 Comparison of the drain capacitance of an LDMOSFET on SOI and an LDMOS-FET on bulk silicon. The capacitance on bulk silicon has the expected 1

behavior, but the capacitance on SOI flattens out at large drain voltage because the substrate inverts beneath the buried oxide. . . . . 94

3-13 Peak ft and fmax for an LDMOSFET on SOI and an LDMOSFET on bulk silicon at Vd, = 3.6 V. The device layout had two gate fingers. There was little difference

between these results on SOI and bulk silicon. The fmax rolled off with the finger length, indicating that the resistance of the polysilicon gate reduced the power gain. 95

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3-14 Load-Pull characteristics of LDMOSFETs on thin-film SOI and LDMOSFETs on bulk silicon. The performance of the two types of devices was similar, but the SOI LDMOSFETs have higher PAE. The size of the RF power cell was Wg = 20x40 pm and the device was biased for class-A operation. The matching networks were set for maximum PAE. . . . . 96 3-15 PAE as a function of bias current density of LDMOSFETs on thin-film SOI and

LDMOSFETs on bulk silicon. The PAE of the LDMOSFET on thin-film SOI was

consistently higher than the PAE of the LDMOSFET on bulk silicon. The size of the RF power cell was W9 = 10x100 pm. The matching networks were set for maximum PAE. . . . . 97

3-16 The intermodulation distortion of the LDMOSFET on thin-film SOI was identical

to the intermodulation distortion of the LDMOSFET on bulk silicon. . . . . . 97

3-17 Drain pad capacitance (Im(Y)) on SOI and bulk silicon. The pad capacitance is lower on bulk silicon than on SOI. . . . . 98 3-18 Drain pad conductance (Re(Y)) on SOI and bulk silicon. The pad conductance is

lower on SOI than on bulk silicon. . . . . 99

3-19 Lumped element model of the pads. This model is similar to the one in Chapter 2,

except that a series resistance was added which makes the model more accurate. 100 3-20 Cross section of the layers beneath the pads. The reason for the reduced

con-ductance of the pads on SOI can be seen in this picture. The isolation implant is stopped by the buried oxide, and does not dope the silicon beneath the buried oxide. This reduces the series capacitance and increases the substrate resistance relative to the pad on bulk silicon. . . . . 101 3-21 MEDICI simulation of the pads. The simulations showed a qualitative agreement

with the pad measurements. This plot also shows the important role that the isolation implant plays in increasing pad loss. . . . . 102

3-22 Load-Pull with the pad loss de-embedded. The pad loss accounted for a large

portion of the difference of the PAE between the LDMOSFET on SOI and the

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4-1 Illustration of the second generation fabrication process. The most significant en-hancement from the first generation process was the addition of a metal/polysilicon dam ascene gate. . . . . 109

4-2 Illustration of a CMP vernier that was used to monitor the degree of over-polishing in the oxide CMP process. . . . . 112

4-3 SEM of wafer surface showing aluminum line before cleaning. Many slurry particles

can be seen in the SEM. Post CMP wafer cleaning to remove the slurry particles is a critical part of a CMP process. . . . . 114

4-4 SEMs comparing aluminum lines with old and new cleaning processes. The old process included a long period of time in which the wafers soaked in water, resulting in gross aluminum corrosion. In the new cleaning process, the wafers were cleaned directly after CMP, which greatly improved results. . . . . 115

4-5 Sheet resistance of the metal/poly damascene gates, polysilicon, and W-silicide from a state-of-the-art LDMOSFET process [1]. The metal/poly damascene gate process achieved very low levels of gate resistance. . . . . 117

4-6 fmax of 2x100pim SOI LDMOSFETs and peak PAE (at 1.9 GHz) of 36 finger SOI

LDMOSFETs with metal/polysilicon damascene gates and with polysilicon gates. The LDMOSFETs with metal/polysilicon damascene gates had much higher RF gain and peak PAE, especially for long finger lengths. . . . . 118

4-7 Maximum PAE (at 1.9 GHz and 3 GHz) for LDMOSFETs on four different sub-strates. The use of a high resistivity bulk silicon wafer lead to a significant increase of the PAE, but the use of a high resistivity SOI wafer did not result in an increase of the PA E. . . . . 120

4-8 Small-signal model used to understand substrate loss issues. The model includes networks which represent the gate pad, drain, and drain pad. . . . . 120

4-9 Typical fit of the model to the device s-parameters. 2 x 100 pum device on SOI wafer. Vd,=3.6 V, Vgs set for maximum g,. Data is the noisy line and the model is the sm ooth line. . . . . 121

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4-10 Conductance (Gp) of drain and drain pad at 2 and 3 GHz. The LDMOSFET on a high resistivity bulk silicon wafer had significantly lower drain conductance than the LDMOSFET on a standard bulk silicon wafer, but the LDMOSFET on a high resistivity SOI wafer did not have greatly lower drain conductance than the

LDMOSFET on a standard SOI wafer. . . . . 122

4-11 Picture of an LDMOSFET showing surface inversion layer shorting out the high resistivity substrate. Inversion at the surface prevents high resistivity SOI from reducing the conductance or increasing the PAE. . . . . 123

4-12 Capacitance of drain/substrate test structure as a function of the substrate voltage. The capacitance curve demonstrated that the surface of the wafer was inverted during of the measurement of the PAE. . . . . 124

4-13 Peak PAE and capacitance as a function of the substrate voltage. The PAE was highest when the SOI wafer surface was depleted, and was reduced when the surface of the wafer was inverted or accumulated. Freq. = 3 GHz, HRSOI, gate oxide thickness of the device was 20 nm. Vdd = 3.6 V. . . . . 125

4-14 Power sweep of best devices at 3.6 and 6 V. Freq. = 1.9 GHz, HRSOI wafer, gate oxide thickness was 20 nm, bias set for class-AB operation, matching networks set to maximize PAE. . . . . 126

4-15 Best results at 1.9 GHz, 3 GHz, and 4 GHz. A PAE of 63 % was achieved at 1.9 GHz. High PAE was achieved even for long finger lengths, and at 3 and 4 GHz. Vdd = 3.6 V, HRSOI wafer, gate oxide thickness was 20 nm, bias set for class-AB operation, matching networks set to maximize PAE. . . . . 127

A-1 Illustration of the under-source body contact and the striped body contact. . . . 134

A-2 View from the top of the striped body contact. . . . . 135

B-1 Diagram of an RF power amplifier. . . . . 138

B-2 Simplified model of a MOSFET as the starting point of a PA model. . . . . 138

B-3 PA model after the addition of the bias network. . . . . 139

B-4 PA model after the addition of the input matching network and source, and the output matching network and the load. . . . . 140

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B-5 The final simplified model of the PA. . . . . 140

B-6

Output characteristics showing the limiting of the current swing by the on-resistance.

144

B-7

PA model with substrate model added. . . . . 146

B-8

PA model with parallel substrate model. . . . . 147 B-9 PA model with parallel substrate model with a matching inductor added. . . . 147 B-10 Final simplified PA model including output loss. . . . . 147

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List of Tables

3.1 Values of the lumped elements of the drain pad model on SOI and bulk silicon. The SOI pads had lower series capacitance and higher substrate resistance, both of which combine to reduce their conductance. The model values were determined

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Chapter 1

Introduction

1.1

RF Power Amplifiers in Wireless

Communica-tion Systems

Radio frequency power amplifiers are a critical component of nearly all wireless sys-tems. They are used in cellular handsets and cordless phones, cellular base stations, satellites, walkie-talkies, wireless LANs, and television transmitters. They are an im-portant part of almost any system that uses radio frequency electro-magnetic energy to transmit information through the air.

The cellular telephone handset is the most common use of radio-frequency power amplifiers (RF PA) and will therefore be used to demonstrate the role and impor-tance of the RF PA. In a cellular system, shown in Fig. 1-1, a handset is used to communicate with a base station, which is connected to the telephone system. The communication link between the handset and the base station is created by a narrow-band radio-frequency signal with a center frequency near 1 or 2 GHz. The signal emanating from the handset must be powerful enough so that it can be received cor-rectly by the base station. The distance between the handset and base station can be quite far, a mile or more, thereby requiring the handset to broadcast a signal of up to 4 watts. The RF PA is the component in the handset that generates this high-power, high frequency signal.

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Han et

Base Station

Figure 1-1: Diagram of a cellular telephone system. The distance between

the handset and base station can be large. A high power signal is required to create a link.

The block diagram of a typical cellular handset is shown in Fig. 1-2. The RF PA is the last amplifier before the antenna. The performance of the PA is critical to attaining a long battery lifetime. This is demonstrated in the figure, which shows the power consumption of the various blocks during transmission. The power consump-tion of the PA ranges from 200 mW to 3 W depending on the cellular standard and the distance to the base station. The PA accounts for a remarkably large portion of the total system power.

The basic circuit diagram of an RF PA using a MOSFET is shown in Fig. 1-3.

The function of the RF PA is to extract DC power from the drain power supply and efficiently transform it into RF power whose frequency, phase, and magnitude is controlled by the RF power source. The PA has only a few components: input and output matching networks, input and output bias networks, and a semiconductor transistor in common source configuration. In a wireless system the source is a driver amplifier, and the load is the filter or switch before the antenna. The bias networks supply DC current and voltage to the transistor. The matching networks allow power to be effectively coupled from the source into the transistor and from the transistor

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Receiver

Antenna

Down IF amp. Down LNA

Conv. (15 mW) Conv. (3 mW)r a (10 mW) (60 mW) Freq. Ali Processor Synth. (75 mW) Duplexer (50 - 300 mW) Up IF amp Up

Conv. (70 mW) Conv. Power

(10 MW) (40 mW) Amplifier

Transmitter (200 mW -3W)

Figure 1-2: Block diagram of a cellular handset. The RF power amplifier consumes a large portion of the total transceiver power.

into the load. A semiconductor transistor is the heart of the PA, the most important and expensive part. A modern RF PA can consist of a single amplifier or two to three

R,

V, 2 C\, 0 RL

- - - -a.

Source Bias Network Transistor Bias Network Load

Figure 1-3: Block diagram of an RF PA. It has only a few components:

input and output matching networks, input and output bias networks, and a semiconductor transistor.

amplifiers in cascade. Whatever the configuration, the last stage is the most critical to the amplifier's performance, and it is the subject of this thesis. Therefore the term RF power amplifier refers in this thesis only to the final stage in the transmitter.

The performance of a power amplifier is greatly limited by the characteristics of the underlying RF power transistor technology. RF power semiconductor devices have been developed that are designed specifically for RF power amplifier applications.

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1.2

Bulk Silicon LDMOSFETs for RF Power

Am-plifiers

A wide variety of semiconductor transistor technologies are used for RF power

appli-cations. These include Metal Oxide Semiconductor Field Effect Transistors (MOS-FETs) [1], Bipolar Junction Transistors (BJTs) [2] and Heterojuction Bipolar Tran-sistors (HBTs) [3] on silicon substrates; Metal-Semiconductor Field Effect TranTran-sistors (MESFETs) [4], High Electron Mobility Transistors (HEMTs) [5] and HBTs [6] on gallium arsenide (GaAs), and on indium phosphide (InP) [7], and HEMTs on gallium nitride (GaN) and MESFETs on silicon carbide SiC [8]. The choice of technology used for a particular application is dictated primarily by three criteria: cost, output power, and frequency.

The wireless handset has become the most important market for RF power am-plifiers over the last ten years. This application requires power levels of between 500 mW and 4 W in the frequency range of 800 MHz to 2 GHz. GaAs HBTs and sil-icon MOSFETs have emerged as the most suitable technologies for this power and frequency range. RF LDMOSFET (Lateral Double Diffused MOSFET) power ampli-fiers have been particularly successful for PAs in Global System Mobile (GSM), the most widespread cellular telephone standard.

The RF LDMOSFET [1, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23] was developed over the last 25 years for this and other applications. It is an NMOS device that has been specifically designed for RF PA applications, and it is also widely used in base-station applications. LDMOSFET development work took place mostly in companies, foremost being Hitachi and Motorola.

A picture of a state-of-the-art RF LDMOSFET designed for handsets by Motorola

is shown in Fig. 1-4 [1]. The device has several specialized features. It is fabricated on a wafer with a p- epitaxial layer on a p+ substrate. The p-type body doping is formed by implanting the source side of the gate and diffusing it laterally beneath the gate, which gives the LDMOSFET its name. A p+ sinker implant is also put into the source. The drain has an n-type lightly doped region. The gate of the device is made

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of metal, often molibdenym or W-silicide. The source metal is patterned to overlap

the gate.

P+ Enhancement P p

P+DSinker

P+ Substrate

Figure 1-4: Picture of an RE LDMOSFET from Motorola [1]. The features include a

laterally

diffused body, lightly doped drain, p+ sinker, and a low resistance gate.

Each feature of the device improves its performance in RE power applications.

The use of the p+ sinker to the p+ layer of the p-/p+ epitaxial wafer provides a

low resistance, low inductance ground through the back of the wafer. This enables

a high power gain at high frequencies and high on-state breakdown voltage. The

p-epitaxial layer decreases the drain-to-substrate capacitance, which increases efficiency.

Laterally diffused body doping is used for two reasons. First, it allows the drain

side of the gate to remain lightly doped. This permits a low dose n-type implant

into the drain, which is necessary for a high breakdown voltage. Second, lateral

doping increases the velocity of the carriers under the gate and reduces the output

conductance. Both of these increase power gain, as does the use of a metal gate.

The overlap of the gate by the source metal decreases the gate-to-drain capacitance,

which improves stability.

The performance of RE LDMOSFETs has improved since the first RE

LDMOS-FET power amplifier was announced at the International Electron Devices Meeting

(IEDM) in 1983 [9]. The published results are summarized in Fig. 1-5 [1, 9, 10, 11,

12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23]. There were few published results before

1995, but in the mid-1990s there was a sharp increase of interest in RE LDMOSFETs

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because of the spread of cellular telephones. The figure shows peak power added efficiency (PAE), the single most relevant figure-of-merit for RF power amplifers. Re-sults are shown for amplifiers with operation frequencies around 1 GHz, 2 GHz, and

5 GHz. The PAE is generally lower at higher frequencies. The amplifier operation

frequency increased over time, as did the PAE at each frequency. The development of higher frequency amplifiers was motivated by the evolution of applications. The

2 GHz amplifiers were developed for 2 GHz cellular phones, and the more recent 5 GHz amplifiers for wireless LAN applications.

80

0

S1 GHz 70- 0 0 2 GHz

60

-W, 8 / 5GHz C50- 4 8 0 A 40 - # 01 1 GHz -Bulk Si 0 o 2 GHz -Bulk Si A 5GHz-BulkSi 1994 1996 1998 2000 2002 Year

Figure 1-5: PAE of bulk silicon LDMOSFET PAs in the literature. Dotted

lines separate the results at different frequencies. The frequency of operation has increased from about 1 GHz to 5 GHz over time, and the PAE at each frequency has also increased.

The advancement of RF LDMOSFETs over the last 20 years was primarily enabled

by three design improvements: gate length scaling, gate resistance reduction, and

process and layout optimization. The gate lengths were scaled from about 1.2 Pm to

0.35 pm. The gate resistance was reduced by the use of tungsten silicide and metal

runners. The process and layout were optimized to reduce the pad loss and optimize the finger length and number of fingers.

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1.3

RF LDMOSFET on SOI

The focus of this thesis is Silicon-on-Insulator (SOI) MOSFET technology for RF

power applications that is compatible with SOI CMOS. Research on (SOI) MOSFETs

for RF power amplifier applications has been on-going since 1995. This work can be

categorized into three groups: partial SOI MOSFETs [24, 25], quasi-SOI MOSFETs

[26, 27], and thin film SOI MOSFETs [28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39,

40, 41, 42, 43]. The partial-SOI and quasi-SOI devices use complicated processes

that are far different from standard CMOS, and are not compatible with SOI CMOS

technology.

This thesis focuses on thin-film SOI because it can be integrated with SOI CMOS.

Thin-film SOI MOSFETs for RF power applications have been developed with

con-tributions from two sources: SOI CMOS, and high voltage low frequency SOI

MOS-FETs. SOI has advantages over bulk technology in both of these applications. SOI

RF power MOS research seeks to understand if SOI also provides advantages in RF

power applications. A picture of an RF LDMOSFET on thin film SOI is shown in

Fig. 1-6.

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There are many possible advantages of SOI for RF power amplifier applications. The most important is that the buried oxide layer reduces the drain-substrate capac-itance, which is necessary for attaining a high PAE at high frequencies [44]. Other advantages of SOI include improved radiation hardness, which is important in space applications, reduced junction leakage, which is important in high temperature appli-cations, and reduced cross-talk, which is important in integrated applications. SOI also allows for the use of high resistivity substrates, which improve the quality factor of on-chip inductors [45].

The potential advantages of SOI for RF power applications make it particularly interesting for integrated RF systems. The level of integration in wireless systems such as cellular telephones has rapidly increased. These systems contain fewer and fewer separate chips, and more functions are put onto each chip. Integration in the context of the RF power amplifer means two separate things: from the PA up and from the system down. The amplifer itself has evolved towards a higher level of integration.

Several stages, the matching networks, and even the digital control circuitry have been put on the same die. The PA has also been integrated with other parts of the system. The PA has been placed on a die with other sections of the transmitter or receiver. Ultimately it may be possible to integrate all of the components, even the

RF PA, onto a single chip. The advantages of SOI; high efficiency, good isolation,

high

Q

inductors, and the possibility of including SOI CMOS digital logic; make it

very interesting for integrated RF PA applications.

There are also disadvantages of using thin film SOI in an RF LDMOSFET. The

buried oxide layer prohibits the use of a p+ sinker for the source contact. The source must be contacted from the top of the die. Typically a wire bond is used, increasing the source inductance and reducing the power gain. Self-heating is also a concern in using SOI for RF power applications. The thermal resistance of oxide is about 100 times higher than silicon. This can cause self-heating effects, which decrease the gain, the efficiency and the reliability of the amplifier.

The performance of RF SOI MOSFETs is indicated in Fig. 1-7 [28, 29, 30, 31, 32,

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over the last seven years for 2

good with high PAE achieved

R0

70-,60

40

199

and 5 GHz applications. The results have been fairly at both frequencies.

1996 1998

Year 2000 2002

Figure 1-7: PAE of bulk silicon LDMOSFETs and SOI MOSFETs in the literature. SOI MOSFETs have achieved high PAE.

SOI RF LDMOSFETs have been developed mainly by university researchers,

whereas bulk silicon LDMOSFETs have been developed mainly by private indus-try. This is emphasized by Fig. 1-8, which shows the PAE vs the output power of bulk and SOI LDMOSFETs reported in the literature. SOI amplifiers have been made with only small power levels which are insufficient for many applications. The SOI LDMOSFETs that were demonstrated in this thesis had output power levels which were substantially higher than the output power levels of previous SOI LDMOSFETs. The PAE levels of the SOI LDMOSFETs in this thesis were also competitive with state-of-the-art industrial bulk silicon LDMOSFETs.

a a 1 GHz 2 GHz a / 0 a 2G0 -Buk 0 1 -0 01 A G 5 GHz - 0 - A 0o 8 0 -A ##a 1 GHz -Bulk Si .01

~

0 2 GHz -Bulk Si -. A 5 GHz -Bulk Si #- 1 1GHz -SOI 0 : 2 GHz -SOI -A 5 GHz -SOI

s

80. 4

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80

70F

,-60

-_

I0

wi

50I

401

301

0

0 + 0

00

0 + + + 0 + + 0

Bulk Silicon

Sol

SOI

This Work

0 0

200

400

0

+

2

GHz

-

2GHz-2

GHz

-600

Pout

(mW)

800

0

-1000

Figure 1-8: PAE of bulk silicon LDMOSFETs and SOI MOSFETs in the literature as a function

of their output power. Previous SOI devices have been made with only low power levels. The SOI LDMOSFETs in this work have high PAE and power levels greater than 500 mW.

-V

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-1.4

Thesis Goals

RF power amplifiers are a critical component of nearly all wireless systems. Bulk silicon RF LDMOSFETs are very successful in these applications. Thin-film SOI LDMOSFETs have many potential advantages over bulk silicon LDMOSFETs. Thin-film SOI is particularly well suited for integrated RF systems. This thesis studied the design, fabrication, and performance of an RF LDMOSFET on thin-film SOI designed for integrated RF power applications. The advantages and disadvantages of thin-film SOI for RF power applications were evaluated.

The goals of this work were as follows:

1. Development of a high performance RF LDMOSFET on thin-film SOI.

2. Exploration of the advantages and disadvantages of thin-film SOI in RF power applications.

3. Evaluation of the merit of thin-film SOI for RF PAs: Is it a good idea?

The thesis is organized as follows. Chapter 1 is the introduction. Chapter 2 describes the design of an RF LDMOSFET on SOI. Chapters 3 and 4 describe tech-nology development, fabrication and measurement of a first generation and second generation of SOI LDMOSFETs, and Chapter 5 draws conclusions about the merit of thin-film SOI in RF power applications.

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Chapter 2

Design of an RF LDMOSFET on

Thin-Film SOI

2.1

Introduction

This chapter describes how to design a thin-film SOI LDMOSFET for RF power am-plifier applications. There are many different parts of the device design including the gate stack design, channel doping design, and back-end metal and dielectric design.

All aspects of the design are discussed, but issues related to designing on thin-film

SOI are emphasized.

The chapter begins with an examination of the RF power amplifier in a modern wireless system. It identifies specific system-level figures-of-merit of the RF power amplifier that are affected by device design. The SOI LDMOSFET design is then discussed with this understanding.

The DC (low frequency) device design is discussed first. The basic DC behavior (for example the transconductance and breakdown voltage) is controlled by the in-trinsic device design (implants, gate length, and gate oxide thickness). The inin-trinsic device design was done using MEDICI and SUPREM simulations.

Next, optimization of the device design for RF power applications is discussed us-ing an analytical RF PA model. The focus of this section is on two important extrinsic parasitics, the gate resistance and the substrate loss. It is shown that minimizing their

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impact is critical to achieving high RF power performance.

2.2

RF Power Amplifier Figures-of-Merit

To understand how to design an SOI LDMOSFET for RF PA applications it is nec-essary to understand the performance characteristics of the RF PA. As described in Chapter 1, the function of an RF PA is to amplify an RF signal so that it can reach a distant receiver. There are five basic system-level characteristics of the PA: output power level, power gain, efficiency, linearity and electrical robustness. This section describes these characteristics only briefly. A good book on RF power amplifier design for wireless communications is [47].

2.2.1

Gain, Efficiency, and Output Power

Typical RF PA characteristics are displayed in Fig. 2-1, which shows an amplifier's output power, gain, and efficiency as a function of the available input power. The output power rises linearly with the input power at low power levels and then saturates to a constant value. The gain (transducer gain) is defined as:

G =

"'t

(2.1)

Pinav

where Pinav is the available power at the source and Pst is the power delivered to the load. The gain is constant for low power levels and then rolls off. The roll off of the gain is called compression, and is caused by clipping of the output signal by the device. Power amplifiers can be divided into two categories, linear and non-linear. Linear PAs operate with an output power below compression and non-linear PAs operate with an output power above compression.

The efficiency of the amplifier is a critical parameter. Two different figures-of-merit are commonly used: output efficiency (Ef f, t) and power-added efficiency

(PAE). Output efficiency is defined as:

Ef 0

f

t = Pout (2.2)

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30- Effout - 70 25 PAE -60 50 20 Gain o-40 15 a> -30 -C10 W Fa -20 0 Pout .2 5 10 _1 0 -2I-10 0 10 20 Pi (dBm)

Figure 2-1: Typical characteristics of an RF power amplifier. Results are from on-wafer load-pull measurements of a W9 = 36 x 90 um power cell. Vdd

= 3.6 V, Ibias = 10 mA/mm, frequency = 1.9 GHz. Input and output matching

were set for maximum PAE.

where PDC is the DC power that is extracted from system's DC power supply (the battery in a handset). PAE is defined as:

PAE = - Pin (2.3)

PDC

PAE combines both the gain and the efficiency of the amplifier into a single figure of merit. This is clear if Eq. 2.1 and Eq. 2.2 are used with Eq. 2.3 to give

PAE = Ef fout (1 - 1 (2.4)

GT

PAE and output efficiency are plotted in Fig. 2-1. They increase with the output power and are highest in compression. The maximum PAE of an amplifier is the single most meaningful figure-of-merit of PA performance. It is a rough indication of the quality of a device technology for RF PA applications.

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2.2.2

Linearity

RF PA linearity is required in many wireless systems. For a non-constant input signal amplitude, non-linearity in the amplifier causes spectral regrowth [48]. Spectral regrowth is the spread of the bandwidth of the output signal beyond the spectrum of the input signal. Power amplifier non-linearity is measured by recording the power in an adjacent channel relative to the power in the correct channel. The ratio of the in-channel power to the power in an adjacent channel is called the adjacent channel power ratio (ACPR). Results of a typical ACPR measurement are shown in Fig. 2-2. Non-linearity (and ACPR) is high when the device compresses. Linear PAs must operate below compression, and therefore have lower power efficiency. Non-linear power amplifiers, which can be used if the input signal has a constant amplitude, are operated in compression and usually have higher efficiency.

40 - 70 60 20 - PoutPA 0 a 0- 40(' 20 -ACPR30o 20 -40 -10 -600 -20 -0 0 10 20 Pi (dBm)

Figure 2-2: Typical linearity characteristics of an RF power amplifier. Results are from on-wafer load-pull measurements of a W9 = 36 x 90 pm power cell.

Vdd = 3.6 V, INs, = 10 mA/mm, frequency = 1.9 GHz. ACPR measurements

were done using the 3GPP standard with a channel spacing of 5 MHz and an adjacent channel bandwidth and a reference bandwidth of 3.84 MHz. Input and output matching were set to maximize PAE and minimize ACPR.

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2.2.3

Robustness

Electrical robustness of the amplifier is an important figure-of-merit. The robustness of the amplifier can be split into two related but different criteria: reliability and ruggedness.

Reliability is the ability of the amplifier to operate for a long time without signifi-cant changes in its characteristics. A standard test of amplifier reliability is to operate the amplifier under normal output power levels and matching conditions with a con-stant gate bias, and monitor the quiescent drain current. The magnitude of the quiescent drain current shift, caused by injection of hot carriers into the MOSFET's gate oxide, is an indication of the amplifier's long term reliability [1].

The ruggedness of an amplifier is its ability to withstand short periods of harsh operating conditions without sustaining damage. Harsh conditions occur when the impedance seen by the antenna of a system is much different from the impedance of free space. This may occur when, for example, a cellular handset antenna is put onto a metal plate like the hood of a car. RF power is reflected back into the antenna, through the matching network, and into drain of the MOSFET. This results in much higher than normal voltage levels at the drain. The ruggedness of an amplifier is evaluated by intentionally putting an impedance mismatch at the output of the amplifier and determining if the device is damaged. The mismatch produces a standing wave at the amplifier's output, and the degree of the mismatch is indicated by the voltage standing wave ratio (VSWR). Handset amplifiers can typically withstand 20:1 VSWR. Ruggedness is more important for handset amplifiers than for base-station amplifiers because the handset antenna has a less well controlled environment. Reliability is less important for a handset amplifier than for a base-station amplifier because of the relatively short life of a handset.

2.2.4

RF Power Measurements

The measurement of RF power characteristics is a critical part of the evaluation of an RF power technology. The focus of this thesis is on a transistor technology for

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RF power amplifier applications, but RF power characteristics are extracted from a complete RF PA. It is difficult, costly, and time consuming to build a complete RF PA. Additionally, the characteristics of an RF PA are determined not only by the transistor, but also by the other components of the system, such as the matching and bias networks.

An automated load-pull system solves these problems. It enables the measurement of the RF power characteristics of a transistor without requiring the construction of an amplifier. It also de-embeds the losses associated with the other elements in an RF PA, enabling an RF power transistor to be cleanly evaluated.

The schematic of a load-pull system is shown in Fig. 2-3. The system consists of all of the components of an RF PA other than the transistor. This includes the matching networks, bias networks, source, and a power sensor for the load. The load-pull system is connected to the transistor by using microwave probes for on-wafer measurements or RF cables for a packaged transistor. Each of the components of the system is adjustable and controlled by a computer. Load-pull systems made by ATN

Microwave Inc. and Maury Microwave Inc. were both used in this thesis to measure the RF power characteristics of the SOI LDMOSFETs.

Load - Pull System v V

R,

S _Drain H f

V, 5 ZR.r

Source Bias Network. Transistor Bias Network Load

Figure 2-3: Depiction of a load-pull system used for measurement of the RF power characteristics of a transistor. It consists of all of the components of an RF power amplifier other than the transistor.

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2.2.5

Using RF Power Characteristics in Device Design

The previous discussion described the basic RF power amplifier figures-of-merit. Ide-ally, an RF power device should be designed with all five of the RF PA characteristics in mind. It is difficult, however, to directly link the design of the device with the per-formance of an amplifier made with that device. Therefore, only three of the power amplifier figures-of-merit (gain, PAE and robustness) were directly used to guide the design. Robustness was simplified to a demand on the breakdown voltage. Linear-ity was not considered in the device design because it cannot be modeled accurately before a device is built.

2.3

DC Device Design

This section describes the design of the device to achieve the desired low frequency characteristics of the SOI LDMOSFET to meet the requirements of RF PA applica-tions. The DC characteristics of the SOI LDMOSFET are controlled by the device's gate length, gate oxide thickness, SOI wafer specification, and implant design. A cross section of an SOI LDMOSFET is shown in Fig. 2-4, and Fig. 2-5 shows important dimensions.

The basic fabrication steps of an LDMOS process are depicted in Fig. 2-6. The isolation and gate stack process is followed by the body doping process. The body doping is created by masking the source, implanting boron, and annealing. The boron implant is referred to as the body implant. The drift region is then doped by an n-implant, which is called the Lightly Doped Drain (LDD) implant. Phosphorous was used for the LDD implant. An n+ arsenic source/drain implant is masked to delineate the source and drain regions and to define the length of the drift region. The process is finished with back-end steps. Chapter 3 describes the process in more detail.

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Figure 2-4: Schematic cross-section of an RF LDMOSFET on thin-film Sol. Important dimen-sions are labeled.

Figure 2-5: Closer view of the cross-section of an RF LDMOSFET on thin-film SoI.

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Source Drain

j

Step 1: Isolation process and gate fabrication

n- implant

Step 3: LDD Implant

p-type implant

Step 2: Body doping process

n+ Implan

Step 4: n+ source/drain implant

Step 5: Back-End

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