IBM System/3 6 0 Time Sharing System PL/I Conlpiler

IBM System/3 6 0 Time Sharing System PL/I Conlpiler

File No. 8360-29 GY28-2051-0

Program Logic

This publication describes the internal logic of the IBM Systenv360 Time Sharing System PL/I Compiler.

Prograrr: Logic Manuals are intended for use by IBM customer €'ngineers involved in altering program design.

I t can be used to locate specific areas of the program, and i t ena,bles the reader to relate these areas to the corresponCling program listings. Program logic informa- tion is not necessary for program operation and use.

PREFACE

This publication provides customer engineers and other technical personnel with information describing the internal organization and logic of the TSS/360 PL/I compiler. The material is divided into four sections and nine appendixes.

Section 1 describes the overall organi- zation of the compiler and the relationship between the compiler and the time sharing system.

Section 2 contains a general description of each logical phase of the compiler, fol- lowed by descriptions of the physical phases contained within each logical phase.

Descriptions of the control modules and of the interfaces between the compiler and the time sharing system are also included.

Section 3 consists of flowcharts, tables and routine directories. The flowcharts show the relationship between the routines of each phase, while the tables and direc- tories list the routines and their

fUnctions.

Section 4 contains the layouts of tables used by the compiler, as well as formats of text and dictionary entries.

The appendixes contain supplementary material for references purposes.

First Edition (June, 1970)

This edition is current with Version 7, Modification 0, and remains in effect for all subsequent versions or modifications of IBM System/360 Time Sharing System unless otherwise indicated. Significant changes or additions to this publication will be provided in new editions or in Technical Newsletters.

PREREQUISITE PUBLICATIONS

Effective use of this manual requires know- ledge of the information contained in the following manuals:

IBM System/360 Time Sharing System:

Concepts and Facilities, Order No.

GC28-2003

PL/I Language Reference Manual, Order No. GC28-2045

System Logic Summary PLM, Order No.

GY28-2009

In addition, the following publications are recommended as supplemental reading:

IBM System/360 Time Sharing system:

PL/I Programmer's Guide, Order No.

GC28-2049

PL/I Subroutine Library PLM, Order No. GY28-2052

Dynamic Loader PLM, Order No.

GY28-2031

Before using this publication in connection with the operation of IBM systems. refer to the latest edition of IBM SystemV360 Time Sharing Sys- tem: Addendum, Order No. GC28-2043, for the editions of publications that are applicable and current.

Requests for copies of IBM publications should be made to your IBM representative or to the IBM branch office serving your locality.

A form is provided at the back of this publication for reader's com- ments. If the form has been removed, comments may be addressed to IBM corporation, Time Sharing System/360 Programming Publications, Depart- ment 643, Neighborhood Road, Kingston, New York. 12401

Page of GY28-2051-0, Issued September 30, 1971 by TNL GN28-3191

SECTION 1: IN'l'RODUCTION • • • • • • • • • • • • • Purpose of th,e compiler • • . • . • • • • • • • •

The compiler in the TSS/360 System Environment • • • • Organization of the compiler • • • •

SECTION 2: ME'rHOD OF OPERATION Logic of the compiler • • • • •

Compiler Interfaces With the System.

Program Language Controller (PLC) - CFBAA Object Data Set Converter (ODC) - CFBAB Name Processor - CFBAK

Compiler control • . • • • Preprocessing Phases

48-Character Set Preprocessor • Compile-Time Processor Logical Phase Compiler Logical Phases • . • • • • • • •

Read-In Logical Phase • • • • • • • • • Structure of the Read-In Logical Phase Dictionary Logical Phase

Pretranslator Logical Phase • Translator Logical Phase Aggregates Logical Phase Optimization Logical Phase Pseudo-CodE' Logical Phase • • Storage Allocation Logical Phase

Register Allocation Logical Phase • . . • • Final Assenlbly Logical Phase • • • •

Error Editor Logical Phase • • • •

Contents

1 1 1 2

• • • • 7 7

• • 11 11

• • 13

• 15

• • • • 16

• • • 17

· 17 18

• • 19

• • • • 19

• • 21

• • • • 22 30

• • 33

• • 35

• 37 39

• • 49

• 54

• • 55 57

• 58 59 SECTION 3: PROGRAM ORGANIZATION.

Control Phasf! Tables • • • • • • compile-Time Processor Tables

48-Character Set Preprocessor Table • • Read-In Phase Tables • • • •

Dictionary Phase Tables • • • PretranslatOJ: Phase Tables

• • • • • 68

Translator Phase Tables • Aggregates Phase Tables • • Optimizer Phase Tables PseudO-Code Phase Tables

Storage Alloeation Phase Tables . Register Allocation Phase Tables Final Assembly Phase Tables • • Error Editor Phase Tables • Flowchart Conventions • • •

SECTION 4: DATA AREA LAYOUTS • • • • • • • • Resident Tables • • • • • • • •

Organization of Keyword Tables • • • • • • Phase Dire.::tory • • • • • • • • • • • • • • • • •

• • • • 74

• 75

• 82

• .107 .118 .124

• .128

• .143

• .186

• • • 200

• .206 .219 .220

· • • • 361

• • • 361

• .361

• .362 Internal Fornats of Dictionary Entries • • • • • • • • • • • • .363 1. Dictionary Entry Code Bytes • • • • •

2. Dictionar~ Entries for Entry Points 3. code Bytes for Entry Dictionary Entries

4. Dictionary Entries for Data, Label, and Structure Items

5. Code Bytes for DATA, LABEL, and STRUCTURE Dictionary Entries • 6. Format of Variable Information • • • • • • 7. Other Dictionary Entries • • • • • • • •

8. Dimension Table • • • • • • • • 9. Dictionary Entries for Initial Values Internal Formats of Text • • • • • • • • 1. Text Code Byte after the Read-In Phase

• .363

• .365

• .369

• .369

• .312

• .375 .378

• .385

• .385

• .386 .387

Page of GY2B-20S1-0, Issued September 30, 1971 by TNL GN2B-3191

2. Text Formats After The Read-In Phase • • • • • • • • • • .390 3. Text Code Bytes on Entry to the Translator Phases • .396 4. Format of Triples • • • • • • • • • • • • • • • • • • 398 5. Text code Bytes in Pseudo-Code • • • • • • • • • • .401 6. Text Formats in Pseudo-Code • • • • • .401

7. Text Formats in Absolute Code • .404

8. Second File Statements, and the Formats of

Pseudo-Variables • • • • • • • • • • • • • • compiler Functions and -

• • • • • .405 9. Pseudo-Code Phase Temporary Result Descriptors (TMPD) • • • • • • 407 10. Library Calling Sequences • • • • • • • • • • • .409 APPENDIX A: TERMS AND ABBREVIATIONS • • • • • • • • • • • • • • • • .411 DescriptiOns of Terms and Abbreviations used in Text During a

compilation. • • • • • • • • • • • • • • • • • • • • 411 APPENDIX B: COMMUNICATIONS REGION

APPENDIX C: COMPILER OPTIONS TABLE

APPENDIX D: CODE PRODUCED FOR PROLOGUES AND EPILOGUES • Prologues and Epilogues •

DSA Optimization • • • •

APPENDIX E: DIAGNOSTIC MESSAGES • Appendix F: Compile-time processor

1. Internal Formats of Text • • • • • • • • • • 2. Communications Region Use • • . •

3. Compile-time Processor, Time Sharing System, and compiler Control Interfaces • • • • • • • • • • • •

.420

• .426

• • • .429

• .429

• • • • 433 . • • 435

• .443 .443 .447 .449

• • • • • 451 Appendix G: Table Handling Routines for K Phases

Description and Format of Macro Instructions • • • • • • .451 APPENDIX H: CONl'ROL ROUTINES AND TRANSFER VECTORS.

Transfer Vector Table • •

Compiler Control Routines • • • • • • APPENDIX I: PLC COMMUNICATIONS REGION APPENDIX J: ODC -- INPUT RECORD FORMAT Tables and DSECTS Used by ODC •

APPENDIX K: COMPILER OUTPUT MODULES • Index • • •

• • • 455 .455 .456 .464 .466

• .469

• • • • 470 .476

Tables

Table 1- Data Sets Used by PUI Compiler

· · · ^{· ·} · · · · ·

⁵

Table AA. Table AAL Module AA Routine/Subroutine Directory Module AA Compiler Resident Control Phase (Part 1 of 2)

· · ^· · · ·

^{59 60}

Table AB. Module AB Compiler control Initialization

· · · · · ·

⁶¹

Table ABl. Module Table AC. Table AD. Module AC Compiler Control Intermediate File Control t-:cedule AD Compiler Control Interphase Dumping AB Routine/Subroutine Directory

· · · · · ^{· ·} · · · ·

^{61 62} 62 Table ADL M,odule AD Routine/Subroutine Directory

· · · · ^·

⁶²

Table AE. M:odule AE compiler Control Clean-Up Phase 62 Table AP. Nodule AP Compiler Control Options

· · · · · · ^· ·

⁶²

Table AG. l'lodule AG Compiler Control Intermediate File Switching

· ·

⁶²

Table AK. ~lodule AK Compiler Control Closing Phase

· · ·

⁶³

Table AL. ~lodule AL Dictionary Phase (Part 1 of ^q)

·

⁶³

Table ALL ~lodule AL Routine/Subroutine Directory

·

⁶⁶

Table AM. Table AS. Nodule AM Compiler Control Phase Marking Phase AS Resident Phase for Compi le-t ime Processing

· · ·

⁶⁷ 68 Table AS1. Phase AS Routine/Subroutine Directory

· ·

⁶⁸

Table AV. Phase AV Macro Processing Initialization

· ^{· · · · ·} ·

⁶⁹

Table AV1. Phase AV Routine/Subroutine Directory

· · · · ·

⁶⁹

Table Table BCl. Phase BC Routine/Subroutine Directory BC. Phase BC Initial Scan and Translation

· · · · ^· ·

^{70 70}

Table BG. Table BGl. Phase Phase BG Final Scan and Replacement BG Routine/Subroutine Directory (Part 1 of 2)

· · · ^·

⁷¹ 71 Table BM. Phase BM Diagnostic Message Determination and Printing

· ·

⁷³

Table BM!. Phase BM Routine/Subroutine Directory

· ·

⁷³

Table B~. Phase BW Clean-up Phase

· · · · ^{· · ·}

⁷³

Table BX. Phase BX Q8-Character Set Preprocessor

· · ·

⁷⁴

Table CA. 140dule CA Read-In Common Block 1

· · · · ·

⁷⁵

Table CAL )lI!odule CA Routine/Subroutine Directory

· · ·

⁷⁵

Table CC. Table CCl. l"1odule CC Routine/Subroutine Directory J40dule CC Read-In Common Block 2

· · ^{· ·} · · · ·

^{76 76}

Table CEo I>!odules CE , CK, CN, and CR Read-In Keyword Block 76 Table CI. :?hase CI Read-In First Pass

· · · · ^· · ·

⁷⁷

Table CIL Phase CI Routine/Subroutine Directory

· · · · ·

⁷⁷

Table CL. :?hase CL Read-In Second Pass

· · · · · · · · ^· · · · ^{· · ·}

⁷⁸

Table CLl. '?hase CL Routine/Subroutine Directory

· · · · ·

⁷⁸

Table CO. Table COL Phase CO Routine/Subroutine Directory Phase CO Read-In Third Pass

· · · · · · · · · ^{· ·} · · ·

^{79 79}

Table CS. Table CS1. Phase CS Routine/Subroutine Directory Phase CS Read-In Fourth Pass

· · ^· · · ^· · ·

^{80 80}

Table CV. Table CVl. Phase CV Routine/Subroutine Directory Phase CV Read-In Fifth Pass

· · · · · · · · · · · ·

⁸¹ 81 Table ED. Table EDL Phase ED Routine/Subroutine Directory Table EG. Table EGl. Phase EG Routine/Subroutine Directory Table EI. Table Ell. Phase EI Routine/Subroutine Directory (Part 1 of 2) _{Table Table Table} ^Table Table EY1. Phase EY Routine/Subroutine Directory Table FA. Table FE. Table FI. Table ELL Phase EL Routine/Subroutine Directory (part 1 of 2) Table EPl. Phase EP Routine/Subroutine Directory Table Table FA1. Phase FA Routine/subroutine Directory (Part 1 of 2) Table FEL Phase FE Routine/Subroutine Directory Table FIL Phase FI Routine/Subroutine Directory E~l. _{EL. EP. ~.} ^{BY •} Phase ED, Initialization Phase EG Dictionary Initialization Phase EI Dictionary Declare Pass One _{Phase Phase} Phase EW Dictionary LIKE Phase EW Routine/Subroutine Directory ^Phase Phase FA Dictionary Context Phase FE Dictionary BCD to Dictionary Reference Phase FI Dictionary Checking _{EL EP} ^EY Dictionary Declare Pass Two Dictionary Entry III and Call Dictionary ALLOCATE

· · · · · · · · · · · · · · · · ^· · ^{· · · ·} · · · ^{· ·} · · ^{· · ·} · ^· · · · · · · · · · ^{· · · ·} · ^{· · · ·} · · · · · · · · · · · ^· · · · · · ^· · · · · · ^{· · ·} · · · · · · · · ^{· ·} · ^· · · ^· · · · ·

^{82 82 8Q 86 89 82 83 84 87 91 92 93 95 96 90 91 92 93 95 96}

Table Table FKl. Phase FK Routine/Subroutine Directory _Table Table FOl. Phase FO Routine/Subroutine Directory FK. _FO. Phase _Phase FK _FO Dictionary Attribute Dictionary ON

. . _· · · · · · · ^· · · · · · ^· · ^{· ·} · · · · · ·

^{97 98 98 97}

Table FQ. Table FQl. Phase FQ Routine/Subroutine Directory Phase FQ Dictionary Picture Processor

· · · · · · · · · · ^{· ·} · ^·

^{.100 99}

Table IT. Phase FT Dictionary Scan

. · · · · · · · · ·

^.101

Table FTl. Phase FT Routine/Subroutine Directory

·

^.102 Table IN. Phase FV Dictionary Second File Merge

· · · ·

^.103

Table FV1. Phase FV Routine/Subroutine Directory

· · · · ^·

^.104

Table FX. Phase FX Dictionary Attributes and Cross Reference

·

^.105 Table FXl. Phase FX Routine/Subroutine Directory

·

^.106 Table GA. Phase GA DCLCB Generation

· · ^· · ^· · · ^·

^.107

Table GAL Phase GA Routine/Subroutine Directory

· · · ^· · ·

^.107

Table GB. Phase GB Pretranslator I/O Modification

·

^.107 Table GB1. Phase GA Routine/Subroutine Directory

· ·

^.108

Table GK. Phase GK Pretranslator Parameter Matching 1 .109 Table GK1. Phase GK Routine/Subroutine Directory

· · · · ·

^.109

Table GO. Phase GO Preprocessor Parameter Matching 2

· · · · ·

^.110

Table GOL Phase GO Routine/Subroutine Directory .110 Table GP. Phase GP Pretranslator Parameter Matching 2

·

^.110 Table GP1. Phase GP Routine/Subroutine Directory

· · ·

^.111

Table GU. Phase GU Pretranslator Check List

· · ^{· ·} · · ^{· ·} · · ·

^.112

Table GU1. Phase GU Routine/Subroutine Directory

· ^· · ^· ·

^.113

Table HF. Phase HF Pretranslator Structure Assignment .114 Table HF1. Phase HF Routine/Subroutine Directory

·

^.115 Table Table HKl. Phase HK Routine/Subroutine Directory HR. Pretranslator Array Assignment

· · ^{· ·} · · · · · · · · ·

^{.116 .116} Table HP. Table HPl. Phase HP Routine/Subroutine Directory Phase HP Pretranslator iSub Defining

· ^· · · · · · · ·

^{.117 .117} Table IA. Phase IA Translator Stacker

· · · ^· · ·

^.118

Table IAt. Phase IA Routine/Subroutine Directory .118 Table IG. Table IGl. Phase IG Routine/Subroutine Directory Phase IG Translator Pre-Generic

· · · ^· ·

^{.119 .119} Table Table IL. IK. Phase Phase IL Translator Pre-Generic IK Translator Pre-Generic

· · · · · · · · ^{· · ·} · · ·

^{.120 .120} Table 1M. Table IMl. Phase 1M Routine/Subroutine Directory Phase 1M Translator Generic

· · · · ^{· · ·} · · ^·

^{.120 .121} Table IT. Phase IT Post-Generic Processor

· · · ·

^.122

Table ITl. Phase IT Routine/Subroutine Directory

· · · · ·

^.122

Table IX. Phase IX Pointer and Area Checking

· · ·

^.123

Table IX1. Phase IX Routine/Subroutine Directory

· · · · · · ·

^.123

Table JD. Table JOt. Phase JD Routine/Subroutine Directory Phase JD Constant Expression Evaluator

· · · · · ·

^{.123 .123} Table JI. Phase JI Aggregates Structure Processor

· · ·

^.124

Table Jlt. Routine/Subroutine Directory Table JK. Phase JK Aggregates Structure Processor

· · ^· · ^· · · · · ^{· ·}

.125 ^.124 Table JKl. Phase JK Routine/Subroutine Directory

· · · ·

^.126

Table JP. Phase JP Translator Defined Check

·

^.127 Table JPl. Phase JP Routine/Subroutine Directory

· · · · ·

^.127

Table KA. Phase KA Resident Control Module

· ^· · ^{· · ·} · · ·

^.128

Table KA1. Phase KA Routine/Subroutine Directory

· · · · · ·

^.128

Table RC. Phase KC DO-Loop Specification Scan

·

^.129 Table KCl. Phase KC Routine/Subroutine Directory

· · · · · · ·

^.129

Table KE. Phase KE Dictionary Scan and DO-Map Build .129 Table KEt. Phase KE Routine/Subroutine Directory

· · ·

^.130

Table KG. Phase KG DO-Examine Phase

· ^· · ^· · ^· · · · · ^{· ·}

^.130

Table KGl. Phase KG Routine/Subroutine Directory

· · · ^· ·

^.130

Table KJ. Phase KJ Subscript Table Build

· · ^· · · · · · ·

^.131

Table KJl. Phase KJ Routine/Subroutine Directory

· · ·

^.131

Table KN. Phase KN Subscript Optimization

·

^.132 Table KNt. Phase KN Routine/Subroutine Directory

· · · ·

^.132

Table KO. Phase KO subscript Optimization (Part 1 of 5) .133 Table KOl. Phase KO Routine/Subroutine Directory (Part 1 of 2)

· ·

^.137

Table KT. Phase KT PseudO-Code Scan

· ^· · ^{· ·} · · ^{· · ·} · · ·

^.139

Table KT1. Phase KT Routine/Subroutine Directory

· · · · ·

^.140

Table KU. Phase KU no-loop control and Merge Patches (Part 1 of 2) .141 Table KU1. Phase KU Routine/Subroutine Directory

· · · ·

^.142

Table LB. Table LBl. Phase Phase LB Pseudo-Code Initial LB Routine/Subroutine Directory

. · · · · · · ^· · · · · ·

^{.143 .143}

Table LD. _Table Table LG. _{Table LD1. LGi.} Phase LD Pseudo-Code Initial Phase LG Pseudo-Code DO Expansion _{Pbase Phase LG LD} Routine/Subroutine Directory Routine/Subroutine Directory

. · ^· · · · · · · · ·

^{.144 .145 .146 .144}

Table LS. Table LSl. Phase Phase LS Pseudo-Code Expression Evaluation LS Routine/Subroutine Directory

· · · ^· · · · ^· · ·

^{.147 .148}

Table LV. _{Table Table} Table LVl. Phase LV Routine/Subroutine Directory Table LXl. Phase _{LX. MA.} Phase LV Pseudo-Code String Utilities Phase LX Pseudo-Code String Handling _{Phase MA} LX Routine/subroutine Directory Pseudo-Code Translate and Verify Functions

· · · · · · · ^· · ^{· ·} · · · ·

^{.149 .150 .149} .152 ^.151

Table MAL Phase MA Routine/Subroutine Directory .153 Table ME. Phase MB Pseudo-Code Pseudo-Variables

· · · · · · ^·

^.154

Table MEL Phase ME Routine/Subroutine Directory

· · · ^· ·

^.155

Table Table MD. MDl. Phase MD Pseudo-Code In-Line Functions Phase MD Routine/Subroutine Directory

· · · · · · · · · · ^· · · ·

^{.156 .156}

Table ME. Phase ME Pseudo-Code In-Line Functions

· ·

^.156

Table MEL Phase ME Routine/Subroutine Directory (part 1 of 2) .157 Table MG. Phase MG Ps eudo-Code In-Line Functions 1

· · ^{· ·}

^.1.58

Table Table MI. M:;l. P::lase Phase MI Pseudo-Code In-Line Functions 2 MG Routine/Subroutine Directory (Part 1 of 2)

· · · ·

^{.161 .159}

Table MIL Phase MI Routine/Subroutine Directory .161 Table MK. Table MKl. Phase Phase MK MK Pseudo-Code In-Line Functions 3 Routine/Subroutine Directory

· ^· · · · ·

^{.162 .162}

Table Table _Table Table ML. MLL MM. MMl. Phase Phase Phase Phase ML MM ML MM Pseudo-Code Calls and Functions Routine/Subroutine Directory Pseudo-Code Calls and Functions Routine/Subroutine Directory

· · · · · · · · · · ^· · ^{· · · ·} · ·

^{.163 .163 .163 .164}

Table _Table MP. _MPl. Phase _Phase MP _MP Pseudo-Code BUY Reorder Routine/Subroutine Directory

· ^· · ^· · · · ^· · ·

^{.165 .165}

Table _Table Table NA. Table NAL Phase NA Routine/Subroutine Directory (part 1 of 2) _MSl. MS. Phase MS Pseudo-Code Subscripts _Phase Phase NA Pseudo-Code Branches, ON, Returns _MS Routine/Subroutine Directory

· · · · · · ·

^{.166 .161 .166} .161

Table NG. Phase NG Pseudo-Code Operating System Services

· · ·

^.169

Table NGl. Phase NG Routine/Subroutine Directory

· · · ^· · ^·

^.169

Table NJ. Phase NJ Pseudo-Code RECORD I/O (Part 1 of 3)

· ·

^.170

Table NJl. Phase NJ Routine/Subroutine Directory (Part 1 of 2)

· ·

^.1.13

Table NM. Table NMl. Phase NM Routine/Subroutine Directory Table NT. Table NTl. Phase _Table Table NUL Phase Table OB. Table OBl. Phase OB Routine/Subroutine Directory Table ODe Table OE. Table OEL Phase OE Routine/Subroutine Directory Table OG. Table OGl. Phase Table ODL Phase OD Routine/Subroutine Directory _NU. Phase NM Ps eudo-Code Executable I/O Phase NT Pseudo-Code Data and Format Phase NU Pseudo-Code Data and Format Lists Phase OD Pseudo-Code Assignment l)hase OE Pseudo-Code Assignment Phase OB Pseudo-Code Compiler Functions Phase OG Library Calling Sequences NT NU OG Routine/Subroutine Directory Routine/Subroutine Directory Routine/Subroutine Directory

· · · · · · · · · · · · · · · · · · · · · · · · · · ^{· · ·} · ^· · · · · · · · · ^· · · · · · · ·

^{.175 .176 .177 .178 .180 .181 .115 .116 .117 .119 .119 .180} .182 ^.179

Table OM. Table OMi. :?hase OM Routine/Subroutine Directory Phase OM In-line Data Conversions

·

^.183 .1.83 Table OPl. ;?hase OP Routine/Subroutine Directory Table OS. Phase OS Constant Conversions

· · ^· · · · · · ^· ·

^{.183 .184}

Table OSL Phase OS Routine/Subroutine Directory (Part 1 of 2)

· ·

^.184

Table PA. Table PAL Phase PA Routine/Subroutine Directory Phase PA DSAs in STATIC Storage

· ^{· · ·} · · ·

^{.186 .186}

Table PD. Table PDl. Phase PD Routine/Subroutine Directory Phase PD Storage Allocation Static 1

· ^· · · · · · · · ·

^{.187 .181}

Table PH. Table PHL Phase PH Routine/Subroutine Directory Phase PH Storage Allocation Static 2

· · · · · · · ·

^{.188 .188}

Table PL. Phase PL Storage Allocation Symbol Table and DEDs

·

^.189

Table PL1. Phase PL Routine/Subroutine Directory

· · ·

^.189

Table PP. Phase PP Storage Allocation Sort of AUTOMATIC Chain

· ·

^.190

Table PPl. Phase PP Routine/Subroutine Directory

· ^· · · ·

^.191

Table PT. Table PTl. Phase PT Routine/Subroutine Directory Table QF. Phase PT Storage Allocation AUTOMATIC Storage Phase QF Storage Allocation prologues

· · · · · ·

^{.192 .193 .194}

Table QFl. Phase QF Routine/Subroutine Directory

·

^.195

Table QJ • Phase QJ Storage Allocation Dynamic Storage .196 Table QJl. Phase QJ Routine/Subroutine Directory

· · · · ^·

^.197

Table QU. Table QUl. Phase QU Routine/Subroutine Directory Phase QU Alignment Processor

. · ^{· ·} · ^· · · · ·

^{.198 .198}

Table QX. Table QXl. Phase QX Routine/Subroutine Directory Phase QX Print Aggregate Length Table

· · · ^· · · · ·

^{.199 .199}

Table RA. Phase RA Register Allocation Addressability Analysis .200 Table RAL Phase RA Routine/Subroutine Directory

Table RD. Phase RD Use Determination of all EQUs

· · · · · ^·

Table RDL Phase RD Routine/Subroutine Directory Table RF. Phase RF Register Allocation Physical Registers

· ^{· · · · ·}

Table RFl. Phase RF Routine/Subroutine Directory (part 1 of 2) Table TF. Table TFL Phase TF Routine/Subroutine Directory Phase TF Final Assembly Pass 1

· · · ^· · · · · ·

Table TJ. Table TJl. Phase TJ Routine/Subroutine Directory Phase TJ Final Assembly optimization

· ·

Table TO. Phase TO Final Assembly External Symbol Dict.ionary Table TOL Phase TO Routine/Subroutine Directory

· · ^{· ·}

Table TT. Phase TT Final Assembly Pass 2

· · · · · ^· · ·

Table TTL Phase TT Routine/Subroutine Directory

· · · ·

Table UA. Phase UA Final Assembly Initial Values, Pass 1 Table UAL Phase UA Routine/Subroutine Directory

Table UD. Table UDL Phase UD Routine/Subroutine Directory Phase UD Final Assembly Pseudo-Code Static DSA's

· · ^· · ·

Table UE. Table UEL Phase UE Routine/Subroutine Directory Phase UE Final Assembly Initial Values, Pass 2

· ^·

Table UFo Phase UF Final Assembly Object Listing

·

Table UFL Phase UF Routine/Subroutine Directory Table XA. Phase ^XA Error Message Editor

· ^{· ·} · · ^·

Table XAL Phase XA Routine/Subroutine Directory Table 2. Communications Region (Part 1 of 2) Table 3. communications Region (Part 1 of 2)

Table 4. Communications Region. Bit Usage in ZFLAGS

Table 5. Communications Region. Bit Usage in CCCODE. (Part 1

Figures

1. PLC - Interface with TSS/360 • . • •

2. Compiler Organization and Control • • • • • • 3. Compiler Data Flow and Data Sets Used •

4. Compiler Logical Phases (Part 1 of 2)

5. Input and Output Data Sets • • • • • 6. Overall Flow of compiler

7. Input/Output Usage Table • • • • 8. Storage Map for the Read-In Phase • • • • 9. Dictionary Entries for an Internal Entry Point 10. Organization of Read-In Phase

11. organization of Keyword Table • • • • • • • . • • 12. Decision to Include a Second Offset Slot . • • • 13. Dimension Table. . • • • . . • • • • • • • •

·

^.201

· · ·

^.202

·

^.203

·

^.204 _.204

· · ·

^.206

· · ·

^.206

·

^.207

·

^.207

·

^.208

·

^.208

· · ·

^.209

·

^.210

· · ·

^.211

· ·

^.212

· ·

^.213

· · ·

^.213

·

^.214

·

^.215

· · ·

^.216

·

^.217

· · ·

^.219

·

^.219

·

^.420 _.422

.424 of 2) 425

· . . . 1 3

• • • • 4 5

• • • • 9 10 17

• 21

• • 23 .361

• .362

• .376 .385 Figure

Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Triple Figure Figure Figure Figure

14. Temporary Descriptions in Pseudo-Code -- Use of TMPD

Fields FS and F6 • • • • • • • • • • • • 410

15. The IEMAF Control Section. .426

16. Bit Identification Table • • • • 427

17. PL/I Defaults. . • • • • . • • • • • • • • 428 18. PLC Communications Region. • • • • 464

Page of GY28-2051-0, Issued September 3D, 1971 by TNL GN28-3191

Charts

,.r""""",,'_

Chart PLC. Program Language Controller (CFBAA)

· · · · · · · · ^{· ·}

^.221

Chart ODC. Object Data Set Converter (CFBAB)

· · · ^{· · ·} ·

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Chart NP. Chart AA. Name Processor (CFBAK) Control Phase Overall Logic Diagram (Modules AA through

. . . · · ^· · · · ^{· · · ·} ·

^.233

AM)

. .

"

. . . . ^{. .} . . . . . . . . _{· ·} · · · ^{· ·} ·

^.241

Chart 01. Compile-Time Processor Logical Phase Flowchart

· ^· ·

^.242

Chart AS. Phase AS Overall Logic Diagram

· · ^· · · · · ^·

^.243

Chart AV. Phase AV Overall Logic Diagram

· · · · · ·

^.244

Chart BC. Chart BG. Phase BC Overall Logic Diagram Phase BG Overall Logic Diagram

· · ^{· ·} ·

^{.245 .246}

Chart BM. Phase BM Overall Logic Diagram

· ·

^{0 .247}

Chart BW. Chart 02. Phase BW Overall Logic Diagram Read-In Logical Phase Flowchart

· · · · · · ^· · · ·

^{.248 .249}

Chart Chart CI. Chart CL. _Chart Chart CS. _Chart Chart 03. Chart EG. _Chart Chart EP. _{Chart Chart} Chart FA. Chart FT. _Chart Chart 04. Chart GA. Chart EI. Chart FE. Chart FI. Chart _{Chart Chart Chart} Chart GB. _Chart Chart GP. Chart GU. Chart HF. _Chart Chart Chart 05. Chart IA. Chart IG. Chart Chart IL. Chart 1M. Chart IT. Chart Chart JD. Chart 06. Chart JI. Chart JK. Chart JP. Chart 07. _Chart Chart RC. Chart KE. Chart KG. BX. _CO. CV. EW. _{EY • EL.} FK.

_ro.

_{FQ. FV. FX. GK. HK.} HP. _KA. IKo IX. Phase BX Overall Logic Diagram Phase CI overall Logic Diagram Phase CL Overall Logic Diagram _Phase Phase CV Overall Logic Diagram Phase EI Overall Logic Diagram Phase EL Overall Logie Diagram Phase EW Overall Logic Diagram Phase EY Overall Logic Diagram Phase CS Overall Logic Diagram Dictionary Logical Phase Flowchart Phase EG Overall Logic Diagram Phase EP Overall Logic Diagram Phase FA Overall Logic Diagram Phase FE Overall Logic Diagram Phase FI Overall Logic Diagram Phase FK Overall Logic Diagram Phase PO Overall Logic Diagram _Phase Phase FT Overall Logie Diagram Phase FV Overall Logic Diagram Phase FX Overall Logic Diagram Pretranslator Logical Phase Flowchart Phase GA Overall Logic Diagram Phase GB Overall Logic Diagram Phase GK Overall Logic Diagram Phase GP Overall Logic Diagram Phase GU Overall Logic Diagram Phase HF Overall Logic Diagram Phase HK Overall Logic Diagram Phase HP Overall Logic Diagram P'hase IA Overall Logic Diagram Phase IG Overall Logic Diagram l'hase IT Overall Logic Diagram 'J'ranslator Logical Phase Flowchart Phase IK Overall Logic Diagram Phase IL overa.ll Logic Diagram Phase 1M Overall Logic Diagram Phase IX Overall Logic Diagram Phase JD Overall Logic Diagram l~ggregates Phase JI Overall Logic Diagram Phase JR Overall Logic Diagram Phase JP Overall Logic Diagram Optimization Logical Phase Flowchart Phase KA Overall Logic Diagram Phase KC Overall Logic Diagram Phase KE Overall Logic Diagram Phase KG Overall Logic Diagram _{CO FQ} Overall Logic Diagram Overall Logic Diagram Logical Phase Flowchart

· · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · ^{· · · · · · · · · · · · · · ·} · · · · · · ^{· · ·} · · · · · · · ^{· · ·} · · · · · · ^{· · ·} · · · ·

⁰

· · · · · · · · ^{· · ·} · · · · · · · · · · · · · ^{· · ·} ·

⁰

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⁰

^{· · · · · · ·} · · · · · · ^{· · · · ·} · · · ^{· ·} · · · · ^· · · · ^· · · · · · · · ^{· ·} · · ^{· · ·} · · · ·

^{.250 .251 .252 .253 .254 .255 .257 .258 .259 .260 .261 .256 .262 .263 .264 .265 .266 .267 .268 .269 .270 .271 .272 .273 .274 .280 .282 .283 .275 .276 .277 .278 .279 .281 .284 .285 .286 .287 .288 .289 .290 .291 .292 .293 .295 .296 .298 .294 .297}

Page of GY28-2051-0, Issued September 30, 1971 by TNL GN28-3191

Chart Chart KN. Chart KO. Chart KT. Chart KU. Chart 08. ^{1(J •} Phase KN Overall Logic Diagram Phase KO Overall Logic Diagram Phase KT Overall Logic Diagram Phase KU Overall Logic Diagram Pseudo-Code Logical Phase Flowchart Phase KJ Overall Logic Diagram

· · · · · · · · ^· · · · · · · ^{· · ·} · · ·

^{.300 .301 .302 .303 .299} .304

Chart LB. Phase LB Overall Logic Diagram

· · · · · · · ·

^.305

Chart LD. Phase LD Overall Logic Diagram

· ·

^.306

Chart LG. Phase LG Overall Logic Diagram

· ·

^.307

Chart LS. Phase LS Overall Logic Diagram

· · · · · ·

^.308

Chart LV. Phase LV Overall Logic Diagram

· · · · · ^·

^.309

Chart LX. Phase LX Overall Logic Diagram

· ^· · · ^{· · · · ·}

^.310

Chart MA. Phase MA Overall Logic Diagram

· · · ·

^.311

Chart MB. Phase MB Overall Logic Diagram

· ·

^.312

Chart MD. Phase MD Overall Logic Diagram

·

^.313

Chart ME. Phase ME Overall Logic Diagram

· ^{· · ·} · · ^{· ·} ·

^.314

Chart MG. Phase MG Overall Logic Diagram

· ·

^.315

Chart MI. Phase MI Overall Logic Diagram

· · · · · · ·

^.316

Chart MK. Phase MK Overall Logic Diagram

· · · · ^· ·

^.317

Chart ML. Phase ML Overall Logic Diagram

· · · · ·

^.318

Chart _Chart Chart MS. Chart NA. _MP. MM. Phase _Phase Phase MS Overall Logic Diagram Phase NA Overall Logic Diagram MM _MP Overall Logic Diagram Overall Logic Diagram

· · · ^· · · · · ^· · · · · · · · ^·

^{.319 .320 .321 .322}

Chart NG. Phase NG Overall Logic Diagram

· ^{· ·}

^.323

Chart NJ • Phase NJ Overall Logic Diagram

· · · · · ·

^.324

Chart NM. Phase NM Overall Logic Diagram

· · · · · ^{· · · ·}

^.326

Chart NT. Chart NU. Chart OB. Phase NT Overall Logic Diagram Phase NU Overall Logi c Diagram Phase OB Overall Logic Diagram

· · · · · · · · · · ^{· · · · ·} · · · ·

^{.327 .328 .329}

Chart OD. Chart OE. Phase OD Overall Logic Diagram Phase OE Overall Logic Diagram

· ^{· · · ·} · · · ·

^{.330 .331}

Chart OGo Phase OG Overall Logic Diagram ⁰

· · · · ^·

^.332

Chart OM. Phase OM Overall Logic Diagram

· · ·

^.333

Chart OP. Phase OP Overall Logic Diagram

· ^·

⁰

^·

^.334

Chart OS. Chart 09. Chart PA. Phase Os Overall Logic Diagram Phase PA Overall Logic Diagram Storage Allocation Logical Phase Flowchart

· · · · · · · · · ^· · ^· · · ^{· ·}

^{.335 .336 .337}

Chart PD. Chart PH. Phase PD Overall Logic Diagram Phase PH Overall Logic Diagram

· · · · · · ^{· ·}

^{.338 .339}

Chart PL. Chart PP. Phase PL Overall Logie Diagram Phase PP Overall Logic Diagram

· · · · ^{· · ·} · · ·

^{.340 .341}

Chart PT. Phase PT Overall Logic Diagram

· · · · · ·

^.342

Chart QF. chart QJ. Chart QU. Chart QX. Chart 10. Chart RA. Chart RD. Chart RF. Phase QF Overall Logic Diagram Phase QJ Overall Logic Diagram Phase QU overall Logic Diagram Phase QX Overall Logic Diagram Register Allocation Logical Phase Flowchart Phase RA Overall Logic Diagram Phase RD Overall Logic Diagram Phase RF Overall Logic Diagram

· · · · · · · · · · · · ^{· · · · · ·} · · · · · · · ^· · ^· · · · · · · · · · · · ^{· ·} · ^· ·

^{.343 .344 .345 .346 .347 .348 .349 .350}

Chart 11. Chart TF. Chart TJ. Chart TO. Chart Chart UA. Chart UD. TT. Phase TJ Overall Logic Diagram Final Assembly Logical Phase Flowchart Phase TF Overall Logic Diagram Phase TO Overall Logic Diagram Phase TT Overall Logic Diagram Phase UA Overall Logic Diagram Phase UD Overall Logic Diagram

· · · · · · · · · · · · · · · · · ^· · ^· · ^{· · · ·} · · · ^{· ·} · ^·

^{.351 .352 .353 .354 .355 .356 .357}

Chart UE. Chart UF. Chart XA. Phase UE Overall Logic Diagram Phase UF Overall Logic Diagram Phase XA Overall Logic Diagram

· · · · · · · · · · · · ·

^{.358 .359 .360}

Page of GY28-2051-0, Issued September 30, 1971 by TNL GN28-3191

PURPOSE OF THE COMPILER

The TSS/360 PLII compiler analyzes and pro- cesses source programs that are written in PL/I and translates them into object data sets. These object data sets contain code that is not suitable for execution by TSSI 360. Therefore an additional processor, the object data set converter (ODC), con- verts these object data sets to TSS/360- executable code.

Usual output from the compiler consists of a load data set and a l i s t data set, when these options have been specified by the user. A macro data set will also be produced when preprocessing is indicated

(see ·Preprocessing" in Section 2).

THE COMPILER IN THE TSS/360 SYSTEM ENV IRONMENT

The compiler consists of a series of logic- al phases that are under the supervision of compiler control routines; subroutines within these control routines provide what- ever services the compiler requires during compilation. communication between the compiler and TSS/360 is achieved through the program language controll(~r (PLC), which is the interface with the system.

PLC performs a series of func1:ions for the compiler at various stages of compilation and, finally, calls the obje~: data set converter (ODC) after compila1:ion, to con- vert the Object data set to TSS/360 code.

PLC -- Interface With the Sys'cem

When the PL/I compiler is invoked, control is transferred to PLC. This module acts as a communications area for useT-specified options, and controls the sequence of events during invocation of the PL/I compiler.

The PLII compiler, unlike the TSS/360 Assembler and FORTRAN compiler, cannot function until the source data set has been fully entered. Therefore, when compilation is called for, PLC searches for an input data set. If the named data set does not exist, PLC invokes the text editor to cre- ate the PLII source data set. When a

source data set exists, control passes back to PLC, which then calls the PL/I compiler.

Depending upon user options specified, invocation of the PLII compiler may cause PLC to act as interface for these

functions:

SECTION1: INTRODUCTION

• Creating a PLII source data set (via the text editor).

• Converting separately created PLII object data sets to TSS/360 code via ODC.

• Combining a list of PLII object data sets for conversion to TSS/360-

executable code.

• Performing multiple compilations within a single invocation of the PL/I

compiler.

• Changing implicit calls to explicit calls via the name processor.

.. Printing compiler-generated listings.

The program language controller (Figure 1) is a serially reentrant and sharable module containing recovery facilities used in case of interruptions. It can check, at any stage, the status of compilation; its recovery facilities permit compilation to proceed from the point of interruption or from the beginning.

PLC may be entered at five main entry points. Initial entry to PLC occurs when the PL/I compiler is invoked. Depending upon the options specified by the user, the text editor, compiler, ODC, and/or the name processor, may be called. PLC's additional entry points provide for entry to subrou- tines used to perform the specific func- tions for which PLC is responsible at various stages of compilation: entry from the text editor after creation of the

source data set, entry after compilation is completed to build the MERGEL5T, an entry point for handling data management func- tions, and entry to the language processor early-end routine.

ODC -- Conversion of Object Code

The TSS/360 PL/I compiler produces code that is similar to 05/360 code. To trans- form the load data set, which is output from the compiler, into TSS/360 code, the object data set converter (ODC) resolves constants and reformats the module.

PLC invokes ODC after completion of the compilations specified with a given invoca- tion of the PL/I compiler. ODC is called only once within an invocation, and then only if a merge list (MERGELST) or a merge data set (MERGEDS) has been specified in the options, or if the PL/I compiler has

Page of GY28-20Sl-0, Issued September 30, 1971 by TNL GN28-3191

,..---..,

IPVl invocationl

L--r--..J

PROGRAM LANGUAGE CONTROLLER

r---,

f Serial I - ~ Reentrant I L _ _ R,::o.::.e2:, _ _

J

TEXT EDITOR (Bui Id Source)

Pl/I COMPILER

OBJECT DATA SET CONVERTER

NAME PROCESSOR (Optional)

1"---,

_ -I Print Lisiting I

I Data Set I L _ _ _ _ _ _ _ .J

,..---,

L ___ .!?~,:.S~S __ ---l

I

SOURCE.XXX

MAC.XXX(O) (Optional) lIST.XXX(O)

LOAD .XXX(O)

I JOBLlB(XXX)

I

I TRANSFER DATA SET

I (Optional)

I I I I

I L __________ .J

Figure 1. PLC - interface with TSS/360 created a merge list to accommodate a series of compilations. Input to ODC con- sists of the PL/I-compiled object data sets in card-image format (see Appendix J).

Output consists of the executable program.

ODC stores all of the TSS/360-executable programs from one invocation of the PL/I compiler as separate members in one job library, resolving standard QCONs (pseudo registers) and passing others to the dynam- ic loader. In addition, ODC packs CSECTs as specified by the default value PLIPACK.

Name Processor -- Conversion of Implicit Calls to Explicit Calls

The name processor is an optionally invoked routine that helps the user transform

implicit calls to explicit calls. To do this, the name processor transforms exter- nal name references in the PMD of a module to new, unique names. In addition, for the new names to be connected with the subrou- tines that have the old names, the name processor optionally constructs or updates a line data set that is called a transfer data set and that has this format:

0-7 8 9-16 17 18-24 25-27 28-35

line number X'OO'

new name blank PLICALL blank old name

The user must supply his own PLICALL macro to perform the explicit calling or

loading of the subroutines.

The name processor constructs or updates the transfer data set only if:

the user has read/write access to the transfer data set, and

tpe default value of UPDTXFER is set to Y, and

the EXPLICIT operand of the PLI command specifies names to be padded.

The new name is derived from the old name by adding a pad character ('~', or a dif-

ferent character that the user specifies with the default value PADCHAR) to the left of the old name.

PLC invokes the name processor after return of control by ODC, if the PLI com- mand included an EXPLICIT or XFERDS operand. Input to the name processor includes the PL/I communications bucket

(CHBPLI) and a table of converted modules to be checked for name transformation

(CHBMGL) .

ORGANIZATION OF THE COMPILER

The PL/I compiler comprises 12 logical phases, each of which consists of several physical phases, all under the control of, and serviced by, the compiler control rou- tines. A compilation is initiated by load- ing the compiler control routines from SYS- LIB. The control routines then carry out their own initialization and perform these functions:

Act as the interface between the com- piler phases and TSS/360, controlling operations such as all input/output, storage allocation, program interrup- tions, and storage dumping.

Supervise the loading and linking of compiler phases in accordance with source program options.

Supervise all work space used by the compiler for information concerning the source program.

Provide a number of routines to assist in compiler debugging.

The entire PL/I compiler, including the control modules, is contained in six link- edited output modules (for contents of out- put modules, see Appendix K). When the user-specified compiler options are inter- preted, i t is determined which of these output modules is to be loaded. The addresses of the individual modules, in each of the loaded output modules, are then moved into a phase directory, and a request for the phases required is inserted in the status byte.

Data Sets Used by the PL/I Compiler

The source data set, which is input to the compiler, is given the name the user speci- fies, or SOURCE.XXX. The data. sets that constitute possible output fr<:>m the compi- ler are: a list data set, named

LIST.XXX(O); a load data set, named LOAD.

XXX{O); and a macro data set, named MAC.

XXX(O). Table 1 contains the corresponding ddnames for each of the data sets used by the compiler. (Generally, ddnames will be used throughout this publication to refer to data sets used by the compiler).

The source program that is to be com- piled appears as input to the compiler on the PLIINPUT data set. If one of the pre- processors is called prior to compilation, a macro data set is created with the ddname of PLIMAC. When preprocessing is com- pleted, PLIMAC replaces PLIINPUT as input to the compiler. The PLILIST data set is opened by PLC unless the user specifies that a separate listing is unnecessary, in which case the listing is placed on SYSOUT and no record of i t is retained in the sys- tem after printout. The PLIIOAD data set, containing compiler output, and the PLIMAC data set, containing intermediate text, are optional and are opened by centrol routines in the compiler. The PLIINPlT data set is always used by the compiler, and is opened by PLC.

The data sets used in the compilation, and the overall data flow as~ociated with a compilation, are illustrated in Figures 2 and 3.

Overview of Logical Phases

Control is passed between thE! phases of the compiler via the control rou1:ines. After each phase has been executed, a branch is executed to the control modu~.e, which

selects (from its phase directory) the next phase to be executed. The compiler phases and their corresponding funci:ions are shown in Figure ~.

Communication between the phases is implemented by the following:

1. The text string. At the start of the compilation, the text s"tring is input text that is converted by the compile- time processor, if necessary, into a string that is PL/I source text. The characters in this stri~g are trans- lated into a code that is internal to the compiler. The phas'::!s of the com- piler gradually process the text until i t is in the final form of the object

r - - - l

I PLiI Com pi ler

I

I I

I I

I I

I I

I I

I

I

I

I

I

I

I I

: I

I

I

I I

I I

I

I

I I

I I

I I

! !

I I

I I

I I

I I

I

I----~~~~~

I

I I

Object Data Set Converter

L _ _ _ _ _ _ _ _ _ _ _ _ _

.-1

~ ____ --____ ^--~·l

_"

__

_Module

O_b_ie_c_t~

'----_

....

Key

- - - - . . . CPU Control

- - - _ . ~ Read/Write Communication .. .. Input/Output under the Program

language Controller (PlC) and Campi ler Control Supervision

Figure 2. Compiler Organization and Control

data set, which consist of machine instructions. The text-code bytes used for the compiler and the formats of statements at different stages of the compilation are in Section 4, under "Internal Formats of Text."

The text is broken down into

blocks; each block has a symbolic name that is independent of the physical location of the block in storage.

Thus, the text blocks may be moved around in virtual storage under the supervision of the compiler control routines.

I

SOURCE option

Sour ce prog ram Ii sti ng PUll ST or SYSO UT

EXTREF option

External symbol dictionary

PLiLIST

I

XREF option

list of identifiers and statement numbers

PULIST or SYSOUT

Source Program (PLIINPUT)

ATR option

List of identifiers and their attributes PLiLlST

MACRO/CHAR48 option

I

LIST option

List of obiect code

PULIST or SYSOUT

for all

Camp i I e - Ti me Processor or 48-Character Set

Preprocessor (PUMAC)

I

LOAD/DECK options

ESD, TXT ,RLD, END and NAME (if OBJNM specifiedj

PLiLOAD

MACDCK option

PL/I source text PLiMAC

campi lations

SOURCE 2 option

List of campi ler Listing of options and input to diagnosti c campi Ie-time

messages processor

PULIST PULIST

Figure 3. Compiler Data Flow and Data Sets Used

2. The dictionary. The dictionary con- sists of blocks, each of which has a symbolic name. Part of the first dic- tionary block is used as a communica- tions region between phases (see Appendix B). The communications region contains such information as the addresses of the heads of chains

and the symbolic start of text. The remainder of the dictionary contains all information relating to identi- fiers appearing in the program, such as temporary storage areas required.

The format of all dictionary entries for the compiler are in Section 4, under "Internal Formats of Dictionary Entries."

page, of GY28-2051-0, Issued September 30. 1971 by TNL GN28-3191

Table 1. Data Sets Used by I'LII Compiler

r---T---r---T---, _{I I I}

Access

I I

I

DDNAME

I

DSNAME

I

Method

I

Comment

I

t---+---+---t---~

I

PLIINPUT or

t

SOURCE.XXX

I I

Source input to compiler -- user-supplied or

I I

user-supplied

I

or

I

VISAM

I

created by text editor before compilation is

I

I

$$$nnnn*

I

user-supplied

I I

initiated

I

r---t---t---t---~

I

PLILIST

I

LIST. XXX (0)

I

VSAM

I

List data set -- built unless user options

I

I I I I

indicate none is necessary

I

r---t---t---t---4

I

PLILOAD

I

LOAD. XXX (0)

I

VSAM

I

Load data set -- output from compiler and

I

I I I I

input to ODC

I

t---t---t---t---4

'I

PLIMAC

I

l<'AC.XXX(O)

I I

Intermediate source text -- created whenever

I

I I

or

I

VISAM

I

preprocessing is specified

I

I I

user-supp!i,:d

I I I

t---t---t---t---~

I

SYSULIB

I

USERLIB

I

VPAM/

I

Member of library used by macro-phase

I

I

or

I

or

I

VISAM

I

~INCLUDE verb

I

I

user-supplied

I

user-supplied

I I !

t---~---~---~---~

I

*Name is generated by the system to be unique. The first three characters are W$$$W

I

I

followed by a unique five-digit number.

I

L ______________________________________________________________________________________ .J

r---T---,

I

Logical Phase

I

Function

I

.---t---~

I

Compile-time Processor

I

Reads input text, executes any compile-time statements in

I 1 I

i t , modifies text as directed, and produces modified text

I

I I

fer further processing.

I

~---t---~

I

Read-In

I

Checks source-program syntax and removes from the test

I i I

string all superfluous characters, such as cemments and non-

I

I I

Significant blanks

I

.---t---~

I

Dictionary

I

ReIDoves all BCD identifiers and attribute declarations from

I I I

the source string and replaces them with symbolic references

i I I

to dictionary entries; entries contain all consistent

I I I

declared attributes and all the attributes specified in lan-

I I I

guage in default of source-program specifications; error

I I I

m€!ssages are generated for all inconsistent attributes

I

t---+---·---1

I Pretranslator 1 Pl:ocesses features of language that are more easily pro- I

I I

cessed in original PUI form than when original syntactic

I I I

form has been lost in later phases; carries out modifica-

I I I

t:.ons that include rearranging of order of certain I/O

I I I

s1:atements. creation of temporary variables for procedure

I I I

aJ:guments that are expressions. conversion of array and

I I I

si:ructure assignments to a series of DO-loops surrounding

I I I

scalar assignments. and removal of iSUB expressions

I

t---t--<---~

I

Translator

I

Converts original PUI syntactic form to internal syntactic

I I I

form ("triples W); triples consist of original source-program

I

! I

o:?erators and operands, rearranged so that operations speci-

i I I

fied in source string may be carried out in proper order

I

t---+---~

I

Aggregates

I

c:l.rries out all structure and array mapping, so that ele-

I I I

m'=nts are aligned on correct virtual storage boundaries;

I I I

when i t is not possible to map at compilation time (such as

I I I

when aggregates contain string lengths or array l:x>unds that

I I I

are specified by expressions) object code is produced to map

I I I

at object time: also checks that items defined on arrays and

I I

L. _______________________ ~

I

______________________________________________________________ structures can be mapped consistently J

I

Figure 4. Compiler Logical Phases (Part 1 of 2)