M6804 MCU Family Intmduclion and Features Hardware Description

® ^MOTOROLA

® ^MOTOROLA

M6804

MCUMANUAL

This information has been carefully checked and is believed to be entirely reliable. However, no responsibility is assumed for inaccuracies. Motorola reserves the right to make changes to any products herein to improve reliability, function or design. Motorola does not assume any liability arising out of the application or use of any product or circuit described herein. No license is conveyed under patent rights in any form. When this document contains information on a new product, specifications herein are subject to change without notice.

© MOTOROLA INC.,

"All Rights Reserved"

First Edition 1984 - Fll 0 Reprinted 1985 - DLE404/D

Printed in Great Britain by Eyre & Spottiswoode Ltd, 7500, 9/85

M6804 MCU Family Intmduclion and Features Hardware Description

Software Desaiption D

Development Tools D

SeIf-chedl: and Testing II

Application Ideas and Hints

Complementary ^Devices

Quality

Handling Precautions

Table of Contents

Page

SECTION 1 M6804 MCU Family Introduction and Features ^{1 -}

1 .1 Introduction 1 - 1

1.2 Family Features 1 - 3

1.3 Technologies for the M6804 Family 1 - 5

1.4 M6805 and M6804 Compatibility 1 - 7

1.5 M6804 and M68HC04 Compatibility 1 - 8

1.6 Summary List of Features 1 - 9

SECTION 2 HARDWARE DESCRIPTION 2-

2.1 Arch itectu re 2- ¹

2.2 Memory 2- 2

2.3 Stack 2- 3

2.4 Central Processing Unit 2- 4

2.5 Arithmetic Logic Unit 2- 4

2.6 Accumulator 2- 4

2.7 X and Y Indirect Registers 2- 4

2.8 Condition Codes, Flags 2- ⁴

2.9 Program Counter 2- ⁴

2.10 I/O Ports 2- ⁵

2.11 Buses on M6804 MCU 2- 7

2.12 Instruction Register 2- 7

2.13 Clock Generator Options, Timing 2- 7

2.14 Timer 2 -10

2.15 Interrupt 2 -11

2.16 Resets 2 - 12

2.17 Modes of Operation 2 - 15

^I

i

2.18 CRC-Cyclic Redundancy Check Circuit 2 - 15

SECTION 3 SOFTWARE DESCRIPTION 3-

3.1 ^3.2 Introduction M6804 Programming Model 3- 1 3- 1 I

3.3 Addressing Modes 3- 3

^:"\

3.4 Instruction Set 3- 8

3.5 Implied Instructions 3- 9

3.6 Move Immediate (MVI) Instruction 3 -10

3.7 Stop and Wait Instructions 3 - 10

3.8 Bit Manipulation Example 3 - 11

3.9 Programming Interrupts 3 -12

SECTION 4 DEVELOPMENT TOOLS 4-

4.1 Description 4- 1

4.2 Central Development Computers 4- 1

4.3 The HDS-200 Hardware Development Station 4- 3

4.4 Debugging with the HDS-200 4- 3

45 Single user VS Multi-User 4- 5

4.6 Ordering Information 4- 7

SECTION 5 SELF-CHECK AND TESTING 5-

51 Introduction 5- 1

5.2 Self-Check Mode 5- ²

5.3 ROM Verify Mode 5- 4

SECTION 6 APPLICATION IDEAS' AND HINTS 6-

61 Introduction 6- 1 .

6.2 Hardware Examples 6- 1

6.3 Software Examples 6- 8

6.4 MC68HC04 Design Considerations 6 - 15

SECTION 7 COMPLEMENTARY DEVICES 7-

71 Introduction 7- 1

7.2 Memones 7- 1

73 Display Drivers 7- ²

7.4 D/A Converters 7- 3

7.5 Remote Control 7- 3

76 PLL Frequency Synthesisers 7- 4

7.7 Telecom Circuits 7- 5

I SECTION 8 QUALITY 8-

81 Introduction 8- 1

8.2 Motorola's Quality Philosophy 8- 1

I ^8.3 Quality in Manufacturing 8- ²

8.4 Reliability Tests· Definition, Purposes and Procedures 8- 6

SECTION 9 HANDLING PRECAUTIONS 9- 1

M6804 MCU Family Introduction and Features

1.1 INTRODUCTION

MOTOROLA has evolved a large and comprehensive family of microprocessors from the original M6800 family through to the M68CXXl16-bit family (see figure 1-1). The introduction of the M6804 family marks another major milestone in the growth of our range.

4G 30 25 20 15 12.5 10 7.5

I

6.0 5.0 4.0

j

^{3.0 2.5}

2.0 1.5 1.2

1.0 fillOO ~----( fi80? os

0.75 0.6 0.5 0.4

75 76 77 78 15

Figure 1.1. Performance Summary Geneology of a Cohesive Microprocessor Family

Advanced Design

Prior to the introduction of the computer-based architecture of single chip microcomputers all 4-bit MCU's and most 8-bit MCU's were evolved from a calculator base. These calculator-based, control-orien- tated microprocessors have the disadvantage of using a split memory architecture containing separate data paths between the CPU and peripherals (memory, or I/O registers), which forces the inclusion of many special purpose instructions and results in an irregular architecture.

1-1

\

--

D

The advanced computer-based design of the M6004 family means that the devices contain a single data bus so that all I/O. program and data may be accessed with the same instruction, therefore, there are fewer instructions to remember. The actual number of unique instructions is increased by a variety of addressing modes which define how an instruction can access any data required for the operation.

Cost Versus Performance

Whilst the M6005 family provides the most cost effective solution for the mid-range control orientated microprocessor market. there are applications where the lower cost of a 4 bit MCU is required. By using ingenuity. MOTOROLA have managed to lower the cost without sacrificing performance. Some of the methods used in achieving this goal are:

• SMALL DIE SIZE - By processing the 8 bit variables serially we have reduced the number of con- nections and hence the die size below that of most 4 bit machines.

• SELF TEST - The extensive on-chip self test routine as pioneered on the 6805 family reduces test time and also helps customers by allowing easy incoming inspection without the large capital outlay of a LSI tester. A simple and inexpensive go/no go field test can also be performed.

• SOFlWARE COMPATIBILITY - Close similarity with 6f!iJJ/6005 software ensures that engineers familiar with programming on these machines can quickly adapt to programming 6804. It also means that only one development system is required for both low-end (6004) and midrange (6805) projects, with the ability to change from one processor to the other half way through a project with- out excessive delay.

These features allow us to offer you, for the first time, 8 bit processing at a 4 bit price.

MC6805P2 MC6804P2

Figure 1.2. Die Comparison of MC 6806P2 and MC 6804P2 (Same Scale)

1-2

1.2 FAMilY FEATURES 1.2.1 M6804 Architecture

One of the principle design objectives of the M6804 family was to reduce die size due to ItS effect on pro- duct cost Figure 1-2 illustrates the difference in size between the MC6804P2 and MC6805P2. Whilst the latter device reqUIres considerable die area for the ALU, I/O ports, and interconnection buses, the most signifir.Ant c:ontribut!o~ on the ~,,~C6804P2 COllieS hOITI ROrvi dliU RAivi.

This is a direct result of the novel architectural approach used in which the M6804 processes 8-blt var- Iables senally, one bit at a time. This inherently provides several major advantages In the quest to reduce die size'

1. Instruction data buses to RAM and I/O are 1-bit rather than 8-blt wide

2. The ALU reduces to a one bit adder with the register storage relegated to RAM locations In place of dedicated latches

3. The program counter is 12 bits long and incremented by another one bit adder

4. RAM is implemented as pseudo-static, i.e. it uses compact dynamic RAM cells refreshed dunng the serial processing cycle. In the CMOS version however static cells are used to allow a power-down mode to be implemented

5. Since the programmer's register set (accumulator, X and Y registers) is Implemented as RAM loca- tions, many Instructions need not be implemented as opcodes directly In the ALU but as implied instruc- tions. For example, the assembler, on recognizing BMI ( Branch if Minus), Inserts the code for BRSET 7,

$FF (Branch if bit 7 set location $FF) where location $FF corresponds to the accumulator.

All members of the M6805 HMOS and CMOS family are designed around a common core which con- sists of CPU, Timer, Oscillator, ROM (EPROM), Control section (for interrupt and reset), and a variable amount of I/O lines This versatile common core design philosophy has already provided many different M6805 family deVices In a very short time. The same successful approach has been taken In the deSign of the M6804 family

1.2.2 Instruction set

The instruction set used with M6804 family is specifically designed for byte-efficient program storage.

Byte efficiency enables a maximum amount of program function to be implemented within a finite amount of on-chip ROM Improved ROM efficiency allows the M6804 family to be used In applications where other processors might not perform the task in the available ROM space, or more features may be included in applications where ROM space is more than adequate In some cases the user might wish to include programs for more than one application In such cases the appropnate program could be selected by the power-up initialization program The ability to nest subroutines, the addition of true bit test and bit manipulation instructions, the multi-function instructions, and the versatile addreSSing modes, all contribute to byte efficiency

Superficial comparisons of the number of bytes per instruction for the M6804 family compared to other machines in this class may be very misleading. A simple M6804 instruction occupying 2 or 3 bytes accomplishes as much real programming work as several single byte instructions, or a subroutine, would accomplish in many other processors

The bit test and bit manipulation instructions permit the programmer to.

branch on bit set branch on bit clear set bit

clear bit

These instructions operate 0", any individual bit in the first 256 address spaces (page zero). As such, the bit m{lnipulations access I/O pins, RAM bits, and ROM bits.

1.2.3 Adressing Modes

One of the chief measures of the effectiveness of a computer architecture is its ability to access data. The M6804 has several major memory addressing modes. They include immediate, direct short direct regis- ter indirect bit-test-direct and bit-direct

1- 3

D

The register indirect addressing mode replaces the indexed addressing mode as it is known on the M6805 family It permits access to conversion tables and data tables located in the Data Space. The use of tables is an important tool in controller type applications In the Register Indirect addressing mode. the operand is at the address (in data space) pointed to by the contents of one of the indirect registers (X or Y).

Efficient addressing methods are coupled with instructions which manipulate memory without disturbing the program registers Thus. RAM may be used for the same functions that other processors use general purpose registers (increment. decrement. complement etcl The M6804 family members have a very versatile.. efficient. and easy-to-use I/O structure. All microcomputer 1j0 function registers are memory mapped into the first 10 processor addresses. Advantage is thus taken of the efficient addressing modes.

the many memory reference instructions. and the use of RAM (or I/O registers) as general purpose regis- ters.

XTAl EXTAl

T imer ... P ^{resca er} I ^Counter Timer

.'~

^{RESft ES T MOS IRQ}

Ti~,C."".' H ""m".'~ _(

Accumulator

f - -

^PBO

A * - -

PAO

2 Port 3

A 1/0 4 lines 5

-

^{Register Indirect} XP ^{Control CPU} Data Port

-

^{* - -}

-

^{r - Oir. B}

- - - _---

^Reg. Port Data ^{A Reg. Oir. r Hardware} Register ^Indirect _Stack VP ^CPU Reg. Reg.

^r--- - -

^~

2 Port 3 B 4 1/0

lines 5 6 PB7

6

---

^ALU

PA7

---

^Program _Counter

^I--

FLAGS Data Port ~

PC _~ Oir. C

1

Reg. Reg. ~

1 I I - -

PCO Port C 2 1/0 PC3 lines

I' x

Program ROM DATA RAM

SeHCheck x

ROM DATA ROM

Figure 1.3. Hardware Functional Blocks Common to All M6804 Family Members

1.2.4 Common Core of M6804 Family

Every M6804 family microcomputer contains hardware common to all versions. plus a combination of options unique to a particular version. Fig. 1-3 depicts the hardware functional blocks common to all M6804 family devices.

The Central Processor Unit (CPU) contains a 1-bit arithmetic logic unit. Program Counter. Stack. Accumu- lator. Indirect Registers. Instruction Decoders. and Control Logic. These elements resemble the M6800 family of microprocessors which constitute the M6805 and M6804 family heritage.

The M6804 family has on-chip RAM and ROM with varying sizes to suit different applications. The addressing modes and register-like memory operations use the RAM to the fullest extent possible.

Parallel I/O capability. with pins individually programmable as input or output are available on every unit.

Also included are an external interrupt input and the capability for multiple nesting of subroutines. fea- tures usually found only in much more powerful architectures.

1-4

A feature which generally simplifies software development and extends the capability of a microcompu- _ _ I,.

ter is an on-chip timer/ counter. The 6804's 8-bit counter and 7-bit prescaler can be programmed for a variety of functions. It can generate an interrupt at software selected intervals. It can be used as an event counter to generate an interrupt after some software selected number of external events. The timer/coun- ter can also be used for time keeping, generating pulses, and counting external events.

1,2.5 Enhanced Microcomputer Test Capabilit'j

As the complexity of VLSI (Very Large Scale Integration) rises, increasingly complex and costly test hard- ware is required. This is especially true of ROM-based microcomputers, which are supposed to be used in the low-end market. Here the cost of testing starts to considerably affect the end price of the device, as well as the cost of incoming inspection

The M6804 family has a very sophisticated self test capability built into the chip Placing the MCU in SELF-CHECK mode will cause execution of a functional test program stored in the program ROM which verifies correct operation of most of the hardware included on the chip Verification is achieved by means of signature analysis using an on-chip Cyclic Redundancy Check (CRC) circuit. This circuit contains a 16-bit shift register configured to perform the check using the cCln polynominai. Similarly, program ROM contents can be checked by placing the MCU in ROM VERIFY mode, which again uses the CRC circuitry

Use of this self test hardware during manufacture allows the M6804 family to be tested quickly and inex- pensively, with a high degree of confidence.

1.3 TECHNOLOGIES FOR THE M6804 FAMILY

One of the first options to be selected by the system designer is the choice between HMOS and HCMOS processor technologies.

1.3.1 HMOS Features

The NMOS (N-channel metal oxide on silicon) technology has been the mainstay of the M6800 family.

The current state of the continual shrinking of NMOS is referred to as HMOS (high density NMOS). The prime consideration when choosing a M6804 family member in HMOS technology is its lower price com- pared with HCMOS.

The HMOS inverter circuit. shown in Fig. 1 -4, illustrates the operating principles of HMOS 10gic.Two tran- sistors are series connected between ground Vss and VDD ; one is an active N-channel transistor and the

HMOS Inverter Circuit

VDD

Pull-Up Transistor

~----o Output

HCMOS Inverter Circuit

Input 0--""

VDD

J IJ Ac,'veP-Channel

Pull- Up Device

~outPut

~ctiV:

^N-Channel

Figure 1.4. HMOS and HCMOS Inverters

1 k

D

other is a turned-on pUlicup transistor. When a logic low is applied to the circuit input. the N-channel tran- sistor is reverse biased and represents a high impedance, compared to the pull-up transistor (which pro- vides the same function as a resistor). A load connected to the circuit outputcan be driven to a logic high through the pull-up transistor.

When a logic high is applied to the circuit input. the N-channel transistor is turned on and becomes a very low resistance to Vss causing the output to go low. In this situation, current will flow through the N- channel transistor from both the pull-up transistor and any load on the output.

Other logic circuits.constructed in HMOS technology use series and parallel combinations of the N-chan- nel transistors. However, they all rely on the same operating principle, that is, the active N-channel tran- sistor is used to sink current from the output. and a passive load transistor. which behaves similarly to a resistor, is used to source current to the output.

It is the current flowing through the pull-up load transistor, when the N-channel transistor is turned on, that accounts for most of the power consumed in an HMOS integrated circuit.

'1.3.2 HCMOS Features

The HCMOS inverter circuit. shown in Fig. 1-4, illustrates the operating principles of the HCMOS logic. In HCMOS the pull-up transistor is replaced with an active P-channel transistor. In this type of circuit. one transistor complements the other, i.e. when one is turned on the other is turned off. The characteristics of the P-channel transistor are such that a high signal input turns it off. conversely. a low signal input turns it on.

The active P-channel transistor sources current when the output is high (input low). and presents a high impedance when the output is low (input high). Thus, there is essentially no current flow within the inver- ter whenever the output is low. The overall result is extremely low power consumption because there is no power loss through the active pull-up transistor.

The switch point of the HCMOS inverter is approximately 50% of the supply voltage (Vaa) rather than being determined by the threshold of the N-channel transistor. Because of this, the operating voltage range of a HCMOS device is much wider than that of. a HMOS device. This permits a greater choice of supply voltages or allows the use of a less regulated power supply.

The properties of HCMOS (complementary metal oxide) technology are inceasingly attractive, in spite of a higher price. Some applications are simply not feasible with PMOS, NMOS or HMOS microcomputers, e.g. telephone sets powered from the telephone line where the povyer consumption is strictly limited by PTT regulations. In others HCMOS offers significant performance advantages, e.g.

• power consumptions ranging from 1/15 to 1/200 of the equivalent HMOS part;

• fully static operation;

• higher noise immunity ;

• greater tolerance of ambient temperature variations;

• wider operating voltage range;

• higher frequency of operation.

Another important feature of HCMOS is that the internal circuitry only dissipates power during switching transitions, which allows the addition of WAIT and STOP instructions. In WAIT mode, the only circuitry left running is the oscillator and timer, reducing power consumption by a significant factor. In STOP mode all circuitry is closed down and the device requires only a very small current in order to retain the RAM con-

ten~s.

Fig. 1.5 illustrates how the CMOS process has evolved in recent years to produce faster and smaller devices, so that today's HCMOS-l process can support switching speeds in excess of HMOS. Plans are already in hand to shrink both the HMOS and HCMOS process still further in the near future. The M6804 family will continue to benefit from these improvements in processing technology in order to provide a high performance, cost effective family of MCUs.

5-J.lm silicon-gate Cmos

POlyslllcon gate

Htgh-speed sllicon-g?lle CMOS

3-jJm hlgh·de;lsily sJlicon'gafe

HCMOS-~

Metal

"""~

Polysliicon --~

~~ p •

p n P n

I....

^{43jJm lIE I}

Figure 1.5. Development of CMOS Technology in the Last Decade

1.4 M6805 AND M6804 COMPATIBILITY

Where consistent with the design goal of small silicon Size, compatibility with the M6805 has been main- tained

• The M6805 type Index register has been replaced with 2 Indirect registers (X and Y) which are used to address datA space memory These registers are actually data space RAM and may be manipu- lated In a manner similar to any memory location In data space An Indirect register IS equivalent to an Index register where the offset IS always zero

• The M6805 has a stack pOinter, which can be read, and an accessible stack register. The M6804 uses a true LIFO stack to store the subroutine addresses, Thus no stack pointer IS needed

• The M6804 does not have a Condition Code register of the M6805 kind It has only two ConditIOn Code Flags - "Zero" and "Carry" There are two sets of these flags - one for normal operation and the second for Interrupt processing, When an interrupt occurs a context switch IS made from the program flags to the Interrupt flags (Interrupt mode), A RTI forces the context SWitch back to the pro- gram flags (program mode), While In either mode, only the flags for that mode are available, Further, the interrupt flags will not be cleared upon entertng interrupt mode, Instead, the tlags will be as they were at the eXit of the last Interrupt

• The M6805 family allows multiple levels of Interrupts which are limited only by the available stack depth The M6804 allows only one Interrupt to be queued

• While different vectors are prOVided for the timer interrupt, external Interrupt, software Interrupt In the M6805 family, only one interrupt vector IS provided in the M6804 family

• Bit manipulation instructions, so successful on M6805 machines, are maintained on M6804 as well BSET, BRSET, BCLR, BRCLR,

• From the Read-Modify-Wrtte instructions the M6804 has INC, DEC, BSET and BCLR,

1.7

o

• The M6804 family introduces Short-Direct type of instructions taking only 1 byte of Program ROM.

which are not available on the M6805. Using these instructions one byte can efficiently access fre- quently used RAM registers ($80. $81. $82. $83) The locations $80. $81. are the X and Y indirect registers respectively

• Another new type of Instruction has been introduced on M6804 family - Move Immediate to Mem- ory - « MVI» instruction. This instruction is not available on the M6805 and allows immediate data to be moved from program ROM to any data space register. without destroying the value in the accu- mulator.

• There is an incompatibility in the instruction time execution between the M6805 and M6804. Fig. 1.6 shows the operation timing comparison· between the M6805 and M6804 families.

OPERATION MC6804 MC6805 MC68HC04*

BRANCH 8.8 ~Sec 4 ~Sec 4.4 ~Sec

BIT TEST & BRANCH 22 ~Sec 10 ~Sec 11 ~Sec

ADD (Direct) 17.5 ~Sec 4 ~Sec 8.8 ~Sec

MACHINE CYCLE TIME 4.4 ~Sec 1 ~Sec 2.2 ~Sec

XTAL FREOUENCY 11 MHz 4 MHz 11 MHz'

• Assuming -:- 2 option

1.5 M6804 AND M68HC04 COMPATIBILITY

Although all members of the M6804 family are baSically the same. there are some differences between HMOS and HCMOS versions due to different logic implementations and different technologies. These are summarised below and discussed further in later chapters where appropriate

• The MC68HC04 features power saving STOP and WAIT instructions. which the MC6804 does not have.

• The MC6804 uses dynamic RAM cells while the MC68HC04 uses fully static low power RAM cells.

• The MC6804 maximum bus frequency is 2.75 MHz. compared with 5.5 MHz for the MC68HC04. i.e.

HCMOS is twice as fast

• The MC6804 oscillator frequency is limited to 4-11 MHz while the MC68HC04 operates from 0 to 11 MHz

• The MC68HC04 oscillator frequency is divisible by 1.2 or 4 as a photomask option. while the MC6804 only offers diVide by 4.

• The MC6804 can only generate a timer interrupt by hardwiring the timer pin to

iRQ

and operating the timer In output mode. The MC68HC04 is capable of generating a (maskable) timer interrupt Inter- nally. In either Input or output mode. See section 3.9 for further details.

• The MC68HC04 can perform pulse Width measurement using the timer pin as an input while the MC6804 cannot See section 2.14 for further details.

• The MC6804 offers different mask options from the MC68HC04 for the port output drive charac- teristics. See section 2.10.

• The MC6804 treats latched Interrupts In a different way from the MC68HC04. See section 2.15.

• The MC68HC04 features a power-up detect circuit on-chip. while the MC6804 needs an external delay on the RESET pin See section 2.16.

• In single chip and non·user modes the MC68HC04 allows both CRC registers to be used as normal RAM locations wi,lie the MC6804 does not See section 2.18.

1- 8

1.6 SUMMARY LIST OF FEATURES

The list below summarises the features of M6804 family members available. or In design. at the time of publication Further members will be added In due course.

FEATURES MC6804P2 MC6804J2 MC68704P2 MC68HC04P2 MC68HC04P3

._- - - - "

TECHNOLOGY HMOS HMOS HMOS HCMOS HCMOS

NUMBER OF PINS 28 20 28 28 28

RAM(bytes) 32 32 32 32 124

USER PROGRAM

ROM(bytes) 1024 1008 1024 1024 1689

EPROM USER DATA

ROM(bytes) 64 64 64 64 64

BIDIRECTIONAL

I/O LINES 20 12 20 20 20

HIGH CURRENT

SINK LINES 8 8 8 8 8

OTHER I/O

FEATURES Timer Timer Timer Timer Timer

EXTERNAL INTERRUPT

INPUTS 1 1 1 1 1

STOP and WAIT No No No Yes Yes

1- 9

Hardware Description

2.1 ARCHITECTURE

To save silicon area, the M6804 family IS Implemented as a serial machine To the user, however. It appears to be an 8-bit parallel processor Despite serial architecture, the execution speed compares qUite favorably with parallel Implementation This IS mainly due to the use of the most advanced HMOS and HCMOS technologies which enable high speed operation at low voltages and low power consumption

XBUS

Add ess and Read Access to the DATA SPACE r

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u u ^(II) ~ ~ U _lit

cr cr ^lSI Oa:~ _al ^{CIl CIl ~} Instruction

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c c

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Instruction

Decoder

lJ I,

y _BUS

State Machine Write Access to the DATA SPACE

Figure 2.1. Architecture of the M6804 Family of MCUs

Fig. 2.1 depicts the architecture of the M6804 family It is not of the Von-Neumann type In that it has separately addressed program memory, data memory and stack memory The data space contains RAM used for program variables, ROM used for constant values or tables, I/O ports, and the timer registers.

(Timer function will be discussed in a separate chapter). The program space contains only the executable code and immediate data used by instructions in the immediate addressing mode.

2 -1

q

b Y e

d e

m 16

64 -

32

124

1

-

DATA SPACE

DATA I/O REGISTER DATA 1/0 REGISTER DATA 1/0 REGISTER DIRECTION REG DIRECTION REG DIRECTION REG TIMER CONTROL REG.

CRC LOW BYTE CRC HIGH BYTE

Reserved ROM DATA SPACE ROM

future expansion all 1'.

POINTER REG POINTER REG

DATA SPACE RAM

unimplemented alil'.

- -

TIMER PRESCALER TIMER COUNT REG ACCUMULATOR

A B C A B C

X y V W

$00 SOl S02 S04 S05 S06 S09 SOA SOB

$10 _ _ .1F

. 2 0 - - S5F S 6 0 -S7F

S80 _ _ short-direct

$81 _ _ short-direct S82 _ _ short-direct

$83 _ _ short-direct S 8 4 - $FB

$FC SFD SFE

$FF

PROGRAM SPACE

_-

alia's

SELF-CHECK ROM

PROGRAM ROM

SELF-CHECK IRO VECTOR SELF-CHECK RESTART VECTOR

USER IRO VECTOR

USER RESTART VECTOR

STACK SPACE

Levell Level 2 Level 3 Level 4

$0""

$7FF S800

SFF7 SFF8, SFF9

$FFA, SFFB SFFC, SFFD SFFE, SFFF

NOTE RAM & ROM ADDRESSES CHANGE ACCORDING TO DEVICE TYPE

Figure 2.2, MC68HC04PJ Address Map - Other family members are similar except for ROM and RAM values,

The M6804 address map organization is depicted In Fig 2.2 where the diVision between the data space, program space and stack space IS distinguished.

The serial architecture of the 8-blt serial processor reqUires only a 1 bit arithmetiC logic unit (ALU), With address and data buses reduced to one line connections

The X index register in the M6800 or M6805 families has been replaced in the M6804 by two registers X and Y which are placed into the data space RAM, with no offset addressing possibility - Indirect RegiS- ters. Fig. 2.3 shows the registers available to the programmer.

The M6804 instructions execute In 2.4 or 5 machine cycles Each machine cycle reqUires 48 master clock cycles In the HMOS part which IS designed to operate with clock frequencies In the 4 to 11 MHz range.

The HCMOS part is deSigned to operate from 0 to 11 MHz clock frequencies, ie. it is fully static and a machine cycle may take 48, 24 or 12 clocks (see data sheet for confirmation) depending on a mask option. The HMOS design Incorporates dynamiC RAM as opposed to fully static very low power con- sumptIOn RAM in the HCMOS design.

2.2 MEMORY

The M6804 family MCUs operate in three different memory spaces. program space, data space, and stack space

2.2.1 Data Space RAM

The data space RAM consists of 8-bit wide registers whose number depends on the device type, eg. for 2-2

MSB LSB

I

^{b7 ACC blJ}

I

These registers

I

^b7 X REG POINTER ^blJ

I

are memory ,

,

mapped

I

^b7 Y REG POINTER ^blJ

I I

^b1 PROGRAM COUNTER blJ

I

normal flags -

~

interrupt flags _

~

Figure 2.3. Programming Model of the M6804 Family

the MC68HC04P3 there are 124 available at address locations $80 - $FB. For the HMOS versions the RAM IS dynamic and for the HCMOS versions the RAM is fully static

2.2.2 Data Space ROM

The data space ROM can be of variable length, It depends on the deVice type ThiS ROM contains con- stants, addresses, and tables that would be manipulated in data space A BCD to seven segment decode table would, for example, be located In thiS ROM

2.2.3 Program ROM

The program ROM contains user ROM of variable length, e.g the MC6804P2 has 1024 words of 8 bits each The ROM address inputs come from the PC The ROM provides operation codes as well as addresses and operands which may be fixed at assembly time

The ROM also Includes some additional bytes of self-check ROM reserved for Motorola usage

The user is requested to consult the appropriate data sheets for every M6804 family member In order to know the program ROM size and the self-check ROM size.

At the top of the program ROM space are placed all the vectors necessary for Restart and Interrupt operation See Fig. 2.2

2.3 STACK

The M6804 colltalnS a 4-level 12-blt Wide stack used 10 store return addresses dUring subroutine calls and interrupts It is Implemented In RAM separate from the data RAM, and IS not addressable, not readable and not wnteable. See Fig. 2.2

The stack RAM is In stack space which means that the address IS Inherent, that IS, It IS implied by calls and returns.

Whenever a subroutine call or Interrupt occurs, the contents of the PC are shifted into the top register of the stack. At the same time (same cycle) the top register is shifted to the next level down ThiS happens to all registers with the bottom register disappeanng from the stack Whenever a subroutine or Interrupt

2-3

•

11

return occurs. the top register IS shifted Into the PC and all lower registers are shifted up one level. Thus it operates as a true LIFO stack

The values of the accumulator and X,Y registers are not stored on the stack, and must be treated by software, In the subroutine or interrupt routine

2.4 CENTRAL PROCESSING UNIT

The CPU of the M6804 family is implemented Independently from the I/O or memory configuration. Con- sequently, It can be treated as an Independent central processor communicating with I/O and memory via Internal addresses, data, and control buses See Fig. 1.3

2.5 ARITHMETIC LOGIC UNIT

The Arithmetic LogiC Unit (ALU) is a one bit logic unit allowing two Inputs to be ADDED, SUBTRACTED, or ANDED. The Inputs (A. B) have connections to data space locations, Immediate operands, and the accumulator. Outputs from the ALU may be routed to the data space locations or accumulator.

2.6 ACCUMULATOR

The accumulator is an 8-blt general purpose register used in all arithmetic calculations, logical operations, and data manipulations The accumulator is implemented as the highest RAM location ($FF) in data space and thiS implies that several instructions exist which are not explicitly implemented The accumula- tor can be treated In the same way as any data space register. ThiS is a novelty not available on the M6805family

2.7 X AND Y INDIRECT REGISTERS

The X and Y Indirect Registers are In data space RAM locations with addresses $80 and $81, and may be manipulated in a manner similar to any memory location In data space An indirect register is equivalent to an Index register whose offset is always zero. They are used in the Register Indirect addressing mode, and can be accessed with the Direct Indirect Short Direct or Bit-Set/Clear addressing modes.

X and Y Indirect Registers are used as pOinters to other memory. locations In data space (e.g. for data conversion tables)

2.8 CONDITION CODES, FLAGS

Condition code Indicators are provided to indicate zero and carry results of an operation.

The Carry (C) bit is set on a carry or a borrow out of the ALU. It is cleared if the result of an arithmetic operation does not result In a carry or a borrow. The (C) bit is also set to the value of the bit tested in a bit test instruction, and participates in the rotate left instruction

The Zero (Z) bit is set if the result of the last arithmetic or logical operation was equal to zero, otherwise it is cleared

There are two sets of these condition codes, one for interrupt mode and the other for normal operation See Fig. 2.3. When an interrupt occurs while the machine IS in normal program execution mode, a con- text sWitch of the condition code flags is made to the interrupt set of condition codes which will be used by any instructions which test or affect condition codes, until a RTI (Return from Interrupt) is executed The normal mode condition code flags will be left as they were before the Interrupt occured. Every time a new Interrupt IS taken, the interrupt mode condition codes will be as they were at the end of the last inter- rupt

2.9 PROGRAM COUNTER

The Program Counter is a 12-bit register that contains the address of the next ROM word to be fetched (may be opcode, operand, or address of operand).

The contents of the PC are gated out in parallel to the ROM address inputs The PC may be changed in the following ways

2-4

a. To increment the PC its output is shifted through a 1-bit adder and back to the PC input

b. For an RTS or RTI operation. the contents of the top level of the stack RAM are shifted into the PC.

c. For a JUMP or JUMP to SUBROUTINE operation, the jump address is shifted into the PC.

d. For a BRANCH operation, the Branch Offset is shifted into the PC via a 1-bit adder. This adds the offset to the Pc. The sign extension of the offset is likewise added to the Pc.

e. Upon RESET or INTERRUPT the address of the corresponding vector is loaded into the pc. Fig.2.2 shows the address locations. This vector must contain a JMP instruction so that the PC is next loaded with the starting address of an appropriate service routine.

Data

Direction Register . -.... - - - . - - - , Bit

'"

~.g c:

~ u

Q) Q)

-c: c: c:

- 0 u

Latched Output

Data Bit

Data Direction

Regiatar Bit

1 1 0

Output Data

Bit 0 1 X

Input

Output To

State MCU

0 0

1 1

Hi-Z Pin

Figure 2.4. Typical I/O Port Circuitry. The Addresses of Data Direction Registers and I/O Ports are given in the relevant Address Map

2.10 I/O PORTS

The M6804 MCU contains memory mapped I/O ports. They consist of separately addressable Data Registers and Data Direction Registers (DDR), All pins are programmable as either inputs or outputs under software control of the corresponding Data Direction Register. Typical I/O port circuitry is shown in Fig, 2.4, The port I/O programming is accomplished by writing the corresponding bit in the DDR as a logiC one for output or a logic zero state for input On reset all the DDRs are initialized to a logic zero state to put the ports in 'the input mode, The port output registers are not initialized on reset but should be initialized before changing the DDR bits to avoid undefined levels,

In HMOS devices all I/O pins are LS TIL compatible as both inputs and outputs, In addition, one of two mask options may be selected for each port:

1, Internal pull up resistor for CMOS output compatibility, 2, Open Drain Output

HCMOS devices are LS TIL compatible as inputs, provided Vec = 5V

±

10%, Under this condi- tion they will also drive two LS TIL loads in outptlt mode. This is in addition to being fully CMOS compatible, The only mask option available is a pull down device, which can be selected on any number. of the I/O pins, and is particularly useful for keyboard encoding applications.

Fig, 2.5 shows typical port connections for the MC6804P2 MCU in the Input Mode or Output Mode,

I

Q t

SN74LS04 lTyplcali

PB7 19 PB6 18 PB5 17 PB4 16 PB3 15 PB2 14

-

PBl 13 PBO 12

-

PA7 PA6 25 PA5 24 PA4 23 PA3 22 PA2 PAl PAO

MC14069

SN74LS04 or MCl4069 ITYPlcali

PC3 PC2 PCl PCO (Typlcali

a) Input Mode

PA7 27 (CMOS Loads)

PA6 26 PA5 25

PA4 24 11 LSTTL Loadl

-

PA3 23 PA2 22 PAl 21 PAO 20

+ V

PC3 11 PC2 10 PCl 9

",-"'- PCO 8

b) Output

17 16 15

+ V PB7 PB6 PB5 PB4 PB3 PB2 PBl PBO

CMOS Inverter MC14049/MC14069

!TYPlcali

Figure 2.5. Typical Port Connections for the MC6804 P2 MCU

2-6

2.11 BUSES ON M6804 MCU

From Fig. 2.1. it is apparent that there are two buses on the M6804 MCU. the X-Bus and V-Bus. These two serial buses fulfill the following functions.

The X-Bus seNes for transfer of address and for the read access to the data space: while the V-Bus seNes only for the write access to the data space.

2.12 INSTRUCTION REGISTER

The Instruction Register is a set of latches connected between the ROM output and the Instruction Decoder input.

These latches hold the operation code for the current instruction. Loading the Instruction Register is thus an instruction «fetch

».

MC88HC04 orMC8I04 XTAL EXTAL

5 4

I D I

Crystal

MC8I04 XTAL

5 4

NC

I

MC88HC04 XTAL

5

I

External Resistor Capacitor

MC88HC04 or MC6804 XTAL EXTAL

5 4

Clock ^NC

Input

External Clock

Figure 2.6. Clock Generator Options of the M6804 Familv of MCU·s. All options are mask selectable. Note the difference between the External Resistor - Capacitor

options for the HMOS and HCMOS versions.

2.13 CLOCK GENERATOR OPTIONS. TIMING

All microprocessors require a generator which generates the internal clock frequency. The M6804 family has been designed to use either a crystal oscillator: an external resistor and capacitor: or an external clock. All these possibilities are depicted in Fig. 2.6. Clock generator options are mask selectable. There is a difference in use of the external resistor capacitor option between the HMOS and HCMOS versions.

Whichever clock generator is used the oscillator frequency is internally divided to produce the internal bus cycle clocks. 01 and 02. See Fig. 2.7. In the case of HMOS devices. the oscillator is divided by 4.

whilst for HCMOS it can be divided by 4.2 or 1 depending on a photomask option. The divisions by 2 and 1 are available on HCMOS in order t<!l save power when higher bus frequencies are required This is an

2-7

(a) Oscillator- ,.1-. 2 Timing

ose

111

.J

f12

1 .... __

^---.1

(b) A!l1-Sync Timing

SYNe~~ ______________________________ ~~

Figure 2.7. Clock Generator Timing Diagram

important benefit in low power applications. Note that it is bus frequency rather than oscillator frequency which limits the performance of HCMOS devices - it must not exceed 5.5 MHz. whatever the oscillator frequency.

The 01 clock is further divided by 12 to produce the machine cycle clock in both HMOS and HCMOS ver- sions. A machine cycle is the minimum time needed to execute any operation. i.e. increment the 12-bit program counter. Instructions require either two. four or five machine cycles to execute depending on their type This is shown in Fig. 2.8.

INSTRUCTION TIMING Branch if bit set or clear Short-direct instructions

Direct. Indirect. Immediate instructions Move immediate to memory

Jump and Jump to subroutine Roll accumulator

Complement accumulator. Bit set. Bit clear Short branch

Retum from interrupt Stop

Wait

5 cycles 4 cycles

2 cycles

Figure 2.8. M6804 Instructions and their Execution Times measured in Machine Cycles

2-8

TIMER P,n

Microcomputer Internal Bus

DATA TIMER Pin Sto",.

PrelC.lier TIMER

TOUT Clock Pin

a TIMER Pin Input Mode

1 Sync Output Mode (a) HMOS Timer

Microcomputer tnternal BUS

TOUT

DOUT

Sync:

TIMER STATUS

TIMER PIN TOUT DOUT TIMER MODE

INPUT 0 0 EVENT COUNTER

0 1 INPUT GATED MODE

OUTPUT ¹ 0

OUTPUT

1 1 (b) HCMOS Timer

Figure 2.9. M6804 TImer Block Diagrams. Note that HMOS Devices differ from HCMOS

2-9

~

,

r:tIi

~

11

Bit7 Bit6 BitS Bit4 Bit3 Bit2 Bit1 BitG

TMZ ETI* Tout Dout PSI PS2 PS1 PSG

*HCMOS only

Figure 2.10. Timer Status/ Control Register (TSCR)

2.14 TIMER

The timer section contains an 8-blt count register, 7-blt software programmable prescaler register, and a status/control register See Fig 2.9 and 2.10 Note that the timer logiC is slightly different for the HMOS and HCMOS family members

All the registers are placed In Data Space RAM under the follOWing locations.

Timer Count Register (TCR) - $FE

Timer Prescaler - $FD

Timer status/ control register (TSCR) - $09

The TCR, which may be loaded under program control, is decremented towards zero by a clock input (prescaler output). The prescaler IS used to extend the maximum Interval of the overall timer. The pres- caler tap IS selected by bits PSO-PS2 of the TSCR which control the actual divIsion of the prescaler within the range given by a 2ⁿscale factor, where « n» IS a value from 0 through 7, see Fig. 2.11

PS2 PS1 PS0

(1) (1) (1) Divide by 1 (1) (1) 1 Divide by 2 (1) 1 (1) Divide by 4

(1) 1 1 Divide by 8

(1) (1) Divide by 16 (1) 1 Divide by 32 1 (1) Divide by 64

1 Divide by 128

Figure 2.11. Timer Prescaler coding of the M6804 Timer.

The TCR and prescaler are decremented on rising clock edges

The timer pin can be selected as either an input or an output by clearing or setting the Tout bit of the TSCR, In the output mode, the content of the timer data output control bit (Dout) is copied to the timer pin each time the count register is decremented to zero, The internal clock frequency is used to decre- ment the prescaler. In the input mode, the timer pin is used as a clock input to decrement the prescaler.

The frequency of the external clock applied to the timer pin must be less than the machine cycle time (fosJ 48 for HMOS),

In HCMOS devices a second input mode exists in which the internal clock frequency is used to decre- ment the prescaler, but is gated by the timer pin so that counting is enabled only when the timer pin is high, This "input gated" mode is selected by setting Dout (bit 4) of the TSCR to one, and can be useful for pulse width measurement. It is not available on HMOS devices,

2 -10

In either the input or output mode. a status bit (TMZ) will be set in the TSCR indicating that the count register has decremented to zero. This bit will remain set until the TSCR is read under program control.

The prescaler/timer can be inhibited from counting by clearing the Prescaler Initialize bit (PSI) in the TSCR. This also sets the prescaler register to alll·s.

TMZ is normally set to logic one when the timer times out (TCR decrements to $00). However. it may be set at any time. by writing $00 to the TCR or by setting bit 7 of the TSCR. During Reset. the TCR and pres- caler are set to $FF, v',:hilc the TSCR is cleared to $00 and the Dout latch is forced to a iogic high.

The prescaler and TCR are implemented in data space RAM locations ($FD. $FE). therefore. they are both readable. and writable. A write to either will dominate over the TCR decremenHo-$OO function. i.e.

if a write and TCR decrement-to-$OO occur simultaneously. the write will take precedence. and the TMZ bit is not set until the next timer time out.

Care must also be used in reading or writing the TSCR to assure that a time out does not occur as the Instruction executes. thus risking the loss of the TMZ state, If TMZ attempts to go high (timer times out) as the TSCR is read or written. the previous low state of TMZ is restored at the completion of the instruc- tion

2.15 INTERRUPT

The M6804 family of MCUs can be interrupted by applying a logic low signal to the fR(} pin: a mask option selected at the time of manufacture determines whether the negative-going edge or the actual low level is sensed to Indicate an interrupt. See Fig. 2.12.

level- Sensitive Mask Option

o

Interrupt

Pin 2

o--...

---OlC IRQ

Gt----("'J

Interrupt Bit

External Interrupt Request

Power - On Reset t - - - External Reset

Interrupt Acknowledge

Figure 2.12. Interrupt Configuration

Please note the following difference between HMOS and HCMOS family members .

• HMOS devices are interrupted only by applying a logic low signal to the fR(} pin

• HCMOS devices are interrupted either by applying a logic low signal to the fR(} pin. or by a timer underflow if the ETI bit in the timer status/control register is set (Fig. 2.9).

2.15.1 Edge-Sensitive Option

When fR(} is pulled low. the internal interrupt request flip-flop is set. Prior to each instruction fetch. the interrupt request flip-flop is tested and. if its output is low. an interrupt sequence is initiated at the end of the current instruction (provided the interrupt mask is cleared). Fig. 2.13 contains a flow chart which illus- trates both the Reset and Interrupt sequences.

The interrupt sequence consists of one cycle during which the interrupt mode flags are selected. the PC is saved on the stack. the interrupt mask is set. the fR(} vector (single chip or non-user mode = $FFC/

$FFD. self-check mode = $FF8j$FF9) is loaded into the PC. and finally the interrupt request latch is cleared.

Unlike the M6805 the vector contents of the M6804 are not inherently decoded as an address to which program control (the PC) should Jump. but instead are decoded like any other ROM word. It is therefore

2 -11

D

essential that the M6804 vector specifies a JMP Instruction to the starting address of the interrupt service routine. This IS Illustrated In the programming examples in section 6.3

Note that If It IS required to save the values of the accumulator and X,Y registers thiS should be done by the Interrupt service routine, since they will not be stored on the stack

Internal processing of the Interrupt continues until the RTI Instruction IS processed During the RTI instruc- tIOn, the Interrupt mask IS cleared and the program mode flags are selected The next instruction of the program IS then fetched and executed.

Once an Interrupt has been detected and the Interrupt sequence started, the Interrupt request latch is cleared so that a second Interrupt may be detected even while the previous (first) one is being serviced However, even though the second Interrupt sets the interrupt request latch, it will not be serviced until completion of the first Interrupt service routine

At thiS pOint there IS another difference between HMOS and HCMOS family members

• HMOS devices will return control to the main program and execute one Instruction In normal mode before servicing the latched Interrupt

• HCMOS devices will service the latched Interrupt Immediately on completion of the first Interrupt service routine

Completion of an Interrupt service routine IS always accomplished uSing an RTI instruction to return to the main program. The Interrupt mask, which is not directly available to the programmer IS cleared dUring the last cycle of the RTllnstructlon

MaXimum interrupt response time IS SIX machine (tbyte ) cycles This includes five machine cycles for the longest Instruction to execute, plus one machine cycle for stacking the PC and sWitching flags from the Normal Operation flags to Interrupt flags Minimum response time IS one machine cycle for stacking the PC and sWitching flags.

2.15.2 Level-Sensitive Option

The actual operation of the level-sensitive and edge-sensitive options are Similar except that the level- senSitive option does not have an interrupt request latch. With no Interrupt request latch, the logiC level of the

fRa

pin IS checked for detection of the interrupt Unlike the edge-sensitive option there IS no way of latching an additional interrupt while a current Interrupt IS being serviced. Also In the Interrupt sequence, there is no need to clear the Interrupt request latch These differences are Illustrated In Fig 2.12 and Fig 213

2.16 RESETS

The M6804 family has two reset modes.

- Power-up reset function

- Active low external reset pin (RESET)

At power-up, a delay IS needed to allow the clock generator to stabilise before starting normal operation On HCMOS deVices a power-up detect circuit IS provided on-chip, and the timer IS used· to control the delay required for the oscillator to stabilise. On HMOS devices thiS delay must be provided externally Connecting a capaCitor and resistor to the RESET input typically provides sufficient delay See Fig 2.14.

There IS a Schmitt tngger at the pin to Improve its noise immunity

Dunng a reset cycle the Interrupt mask IS set to prevent any false or ghost Interrupts occunng, and the PC is loaded with the appropriate restart vector (single chip or non-user mode = $FFE/$FFF, self check mode = $FFA/$FFB)

As with the IRQ vector, it must contain a JMP instruction to a ROM address, which In thiS case should specify the start of the initialization routine. It is essential that the Interrupt mask is cleared at the end of the routine, which requires an RTI (not RTS) as the last instruction. This means the routine must start with a JSR in order to push a suitable PC value onto the stack for subsequent use by the RTI Instruction when returning to the main program. This is illustrated in Fig. 2.15 and later programming examples (section 6.3).

The RESET input pin IS used to reset the MCU to provide an orderly software start-up procedure When using the external reset mode, the pin must stay low for a minimum of 2 machines cycles after the oscil-

2 -12

O-DDRs l-Interrupt Mask

o -Interrupt Req latch (Edge Sensitive Option)

,FF-TCR ,OO-TSCR

$7F- Prescaler

Select Program

Mode Flags

PutsFFF on Address

Bus

Check Interrupt Request

latch Output

N

N

load Program Counter from Reset Vector location ,FFE/,FFF

Clear Interrupt

Mask

Select Program

Mode Flags

Check logic level of

IRQ Pin

N

y

load PC From iJIO

Vector ( ,FFC / $FFD)

Set Interrupt

Mask

Stack Program Counter (PC)

Select Interrupt

Mode Flags

Clear Interrupt Request

latch

A

Figure 2.13. Reset and Interrupt Processing Flowchart for the MC6804 (Refer to data sheet for the MC68HC04)

2-13

a

I)

5V VCC OV

RESET Pin

Internal Reset

Oscillator

J

^{+5V 4.7k}

Reset 28

... 1f.lf

I

Part of

I

_MC6804P2

"I

JMP 2 bytes

I ..

I

V-

"H- _I

Figure 2.14. Power-on reset delay for MC6804 (MC68HC04 has on-chip power-up detect circuit)

A-VECT JMP

-

· ·

^I

A-INIT Initialization

routine

RTI

I I I I

·

I I

JSR A-PMG JSR

2 bytes

·

I

·

PROGRAM FLOW AFTER RESET VECTOR FETCH

Reset vector

Figure 2.15. Flow Chart of the Initialization of Program after Reset or Power - up 2-14