CMOS TECHNOLOGY USING PLASMA NITRIDED OXIDE AS A GATE DIELECTRIC

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CMOS TECHNOLOGY USING PLASMA NITRIDED OXIDE AS A GATE DIELECTRIC

A. Straboni, M. Berenguer, B. Vuillermoz, P. Debenest, A. Verna, P. Dars

To cite this version:

A. Straboni, M. Berenguer, B. Vuillermoz, P. Debenest, A. Verna, et al.. CMOS TECHNOLOGY

USING PLASMA NITRIDED OXIDE AS A GATE DIELECTRIC. Journal de Physique Colloques,

1988, 49 (C4), pp.C4-421-C4-424. �10.1051/jphyscol:1988489�. �jpa-00227987�

CMOS TECHNOLOGY USING PLASMA NITRIDED OXIDE AS A GATE DIELECTRIC

A. STRABONI, M. BERENGUER, B. WILLERMOZ, P. DEBENEST, A. VERNA and P. DARS

Centre National dlEtudes des T t 5 1 ~ c o ~ u n i c a t i o n s , CNET Grenoble, Chemin du Vieux Chgne, BP 98, F-38243 Meylan Cedex, France

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Abstract

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1. INTRODUCTION

In MOS-IC technology, interest devoted to very thin films o f nitrided silicon dioxide is mainly due to their barrier properties (1). Furthermore, it has been reported that nitrided dielectrics show less wear-out and radiation sensitivity than silicon dioxide (2). Whatever the nitridation process, thermal or plasma, the key-point is t o obtain surface nitridation without degrading the initial SiO / Si electrical performance. In this paper, we report electrical characterization o f MI% structures and MOS test transistors o f SRAM devices using dielectrics prepared by direct plasma nitridation o f dry thermal Si02.

2. EXPERIMENTAL PROCEDURES

The ammonia plasma treatments were performed in the Unit o f Reactive Anodization for Nitridation and Oxidation of Semiconductors (U.R.A.N.O.S.) which is a multiwafer set-up compatible with IC production (3). The 13 MHz R.F. plasma i s created through external electrodes located away from the reaction region s o that no energetic particles could attain the wafers. Thermal oxides (from 1 0 t o 25 nm) pre ared at 950°C in dry 0 2 were nitrided from one to six hours at 950°C using NH3 at 3. 10- mbar (hPa) with an incident

S

power of 6 0 0 W. Some o f the nitrided samples were annealed in low pressure dry 0 2 at the nitridation temperature. Capacitors electrodes were defined using photolithography. Device testing was performed after a postmetallization anneal in N2/H2 at 450°C for 3 0 min. High frequency and quasi-static C(V) measurements o n structures prepared with aluminum and polysilicon as the gate material were used to determine the fixed charge Nf and interface trap densities Dit. The breakdown voltage of nitrided Si02 films were investigated by applying a fast ramp voltage (25 V/s). The breakdown voltag (Vbd) was defined as the gate voltage at which a current density o f 1 x A cm-' flows through the oxide. Each histogram is the result o f 85 measurements on the same wafer. Aging experiments based on transconductance degradation measurements were performed on NMOS transistors using 25 nm as grown and nitrided oxides as the gate insulator. Finally, SRAM devices including the plasma nitridation gate process were tested and their yields were compared t o control wafers using the same 2 p design rules CMOS technology.

3. RESULTS

Typical high frequency and quasistatic C(V) curves o f a capacitor with 1 5 nm thick oxide after 3 hours nitridation on P-type Silicon using N+ Polysilicon electrode is shown in Fig.

1. From the flat band shift as compared t o the control oxide, an increa in Nf (dNf) up to 2. 1011 is observed while the midgap Dit remains unaffected (2. 10" cm-'.ev-l). The

Article published online by EDP Sciences and available at http://dx.doi.org/10.1051/jphyscol:1988489

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Figure I. high frequency and quasistatic C(v) curves for a 3 hours nitrided 15 urn dielectric using a N ⁺ Polysilicon electrode on P - Si with S = 0.38 mm2.

5 5

-m Dit

0 2 4 6 8

Nitridation time (Hour)

Figure II. Fixed charge and interface trap creation during the nitridation of 15 n m oxides.

k i n e t i c s o f i n t e r f a c e t r a p and f i x e d c h a r g e b u i l d - u p a r e p l o t t e d i n F i g . 2 a s a f o n c t i o n o f t:he n i t r i d a t i o n t i m e . I t i n d i c a t e s t h e c o n t i n u o u s i n c o r p o r a t i o n o f p o s i t i v e c h a r g e s w i t h t h e t i m e , a n e f f e c t which h a s a l s o b e e n r e p o r t e d f o r p u r e t h e r m a l n i t r i d a t i o n . But i n c o n t r a s t w i t h t h e r m a l p r o c e s s e s , i n t e r f a c e t r a p l e v e l s a r e s c a l e d down a f t e r p l a s m a n i t r i d a t i o n . These r e s u l t s were c o n f i r m e d by p r e c i s e l y m e a s u r i n g t h e N i t d i s t r i b u t i o n u s i n g DLTS f o r 1 0 nm n i t r i d e d o x i d e on N a n d P s u b s t r a t e s . The d a t a on P t y p e s i l i c o n summarized i n t a b l e I show t h a t t h e a v e r a g e midgap D i t is r e d u c e d a f t e r 3 and 6 h o u r s below t h e i n i t i a l o x i d e

TABLE I. D i t ( e v - l . cm-2 )determined by D.L.T.S. TABLE II. Effeet of O2 post - nitridation anneal on for 10 nm oxides on P type Silicon. the VFB distribution (264 capautors/wafer)

c VFB, =mean value, a ( V F B ) = s t d dev.

Oxide Nitrided 15 nm Oxide 2 Hours 2H Nitrided

as grown 1 Hour 3 Hours 6 Hours as grown Nitrided + 02 .anneal

11-2 1

1

^lo9 1

2 . 4 1 . 0

l e v e l . T h i s low d e f e c t d e n s i t y c a n be e x p l a i n e d by t h e low n i t r o g e n i n c o r p o r a t i o n i n t h e b u l k and a t t h e i n t e r f a c e a l r e a d y r e p o r t e d f o r p l a s m a n i t r i d e d o x i d e s ( 1 ) . A low p r e s s u r e oxygen a n n e a l p e r f o r m e d j u s t a f t e r a 2 h o u r s n i t r i d a t i o n under t h e same p r e s s u r e a n d t e m p e r a t u r e c o n d i t i o n s was t e s t e d f o r a 1 5 nm o x i d e . A s shown i n t a b l e 11, t h e f i x e d c h a r g e s were m o s t l y e l i m i n a t e d . F u r t h e r m o r e , t h e Vfb d i s t r i b u t i o n o v e r t h e w a f e r was a l s o improved a f t e r t h i s 02 a n n e a l . S t a t i s t i c a l measurements o f t h e breakdown v o l t a g e Vbd i n F i g . I 1 1 r e v e a l t h a t n i t r i d a t i o n d o e s n o t i n d u c e d e f e c t i n t h e d i e l e c t r i c s and t h a t t h e breakdown

0 10 11 1 2 1 3 14 15 1 6 1 7 1 8 1 9 2 0

Voltage (V)

Figure HI. Histogams of Vbd for a 3H nimded as wmpared to the conaol oxide. bias (

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Figure IV shows the evolution o f the flat band voltage Vfb for the original oxide as compared to the nitrided oxide structures during a Fowler-Nordheim injection from the gate into the dielectrics. The curves show that the nitrided oxide presents less modification during the experiment than

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0 2 0 0 4 0 0 6 0 0

Time (s)

Js = .I mAIcm2 t o x = 15 nm

6H nitrided 2H nitrided

I I I

Fiyure IV. Change in flat band voltage during Fowler - Nordheim injection.

4

3'0

di

Figure V. Comparison of transconductance degradauosl (dGmIdGmg 46) between nitridcd (1 and 2) and non nitrided (3'and 4) transistors.

the thermal oxide. Similar results were obtained for the Dit measurements. Stress measurements were performed on NMOS transistors using 25 nm nitrided and standard oxides. Transconductance tests are reported on Fig. V for devices with channel lengths between 1 and 1.3 micron with the conditions indicated in table 111. In spite of the channel length sligthly shorter for the nitrided dielectrics, the transconductance degradation is reduced with respect to the non nitrided oxide.

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TABLE III. Voltage aging conditions, effective channel length and uansconductanw degradation (dCm %) for nitrided (1, 2) and non nitrided transistors (3, 4).

Transistors 1 2 3 4

Leff VG VD

d G m % L 3 . 7 3.3 6.8 6.9 (for 100H)

Based on the time dependent law A.tn (3), an extrapolation o f the transconductance degradation (dGm X) For a 100 hours stress gives the results indicated in table 111. This seems to indicate that aging reduction after plasma nitridation is related to the low interface trap density.

Plasma nitridation of the gate insulator was applied on 2 microns design rule CMOS technology including 6 0 SRAM (6 Transistors/point) memories and test transistors without any attempt to adjust. the VT shifts due to the fixed charges and without post nitridation anneal. A strong correlation has been noticed between higher fixed charge and lower circuit yields regions over the wafer. The yield reduction (average 15% with 31% for the best nitrided wafer versus 60% avg. for the non nitrided set of wafers) is only attributed to the VT shift as no other defect was detected in the other test devices

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4. CONCLUSION

Our study shows that the plasma nitridation of Si02 films used as dielectric gate insulators does not affect the electrical characteristics of the MIS structures. The reduction in interface trap density seems to be a characteristic of plasma nitridation which is also associated with lower trapping and better aging behaviour for N transistors.

The threshold voltage o f the transistors is shifted due to the presence of fixed charges which can be subst~~ntially reduced through a subsequent 0 2 anneal. Absence of other defects demonstrates the possible utilization of plasma nitridation processing in assembly lines.

ACKNOWLEDGMENTS

The authors wish to acknowledge A. Chantre for the DLTS experiments and G. Gimine and H.

Mingam for useful discussions.

REFERENCES

(1) P. Oebenest, K. Barla, A. Straboni and 8. Vuillermoz. European M.R.S.

Meeting

,

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(2) F. Terry and al., IEEE Elecron Dev. Lett. Vol EOL4, p 191, 1983.

(3) 0. Vuillermoz, A. Straboni and R. Pantel, Electrochem. Soc. Meet. ,Toronto, May 1985, Abstr. 248.

(4) E. Tadeka, N. Suzuki, IEEE Electron Dev. Letters, Vol EDL5,p50, 1984