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Characterization of TFETs made using a Low-Temperature process and innovative TFETs architectures for 3D integration

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Academic year: 2021

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Figure

Figure 1.2. Projection of on-chip electrical interconnect delays with technology scaling [6]
Figure  1.3.  Power  consumption  of  Intel’s  CPUs  in  history.  In  early  2000’s  the  limit  of  100  Watts  was already reached [7]
Figure  1.8.  Classification  of  beyond-CMOS  devices  based  on  the  structure/materials  (conventional  or  novel) and the computational variables charge (voltage, current), non-charge (spintronic, orbitronic) [13]
Figure 2.2. Energy band diagrams of a tunnel diode in forward bias; (a) at zero bias; (b) peak tunneling  current; (c) valley current; (d) diffusion current [4]
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