HAL Id: hal-00722642
https://hal.archives-ouvertes.fr/hal-00722642
Submitted on 2 Aug 2012
HAL is a multi-disciplinary open access archive for the deposit and dissemination of sci- entific research documents, whether they are pub- lished or not. The documents may come from teaching and research institutions in France or abroad, or from public or private research centers.
L’archive ouverte pluridisciplinaire HAL, est destinée au dépôt et à la diffusion de documents scientifiques de niveau recherche, publiés ou non, émanant des établissements d’enseignement et de recherche français ou étrangers, des laboratoires publics ou privés.
High-temperature operation MOS-IGBT power clamp for improved ESD protection in smart power technology
Houssam Arbess, David Trémouilles, Marise Bafleur
To cite this version:
Houssam Arbess, David Trémouilles, Marise Bafleur. High-temperature operation MOS-IGBT power clamp for improved ESD protection in smart power technology. Electrical Overstress/Electrostatic Discharge Symposium (EOS/ESD 2011), Sep 2011, ANAHEIM, United States. pp.1B.2-1B.8. �hal- 00722642�
High-temperature for improved ES
H. Arbe
1CNRS ; LAAS ;
2Université de Toulouse ; UPS
Abstract: We propose a new MOS-IGB robustness ESD protection with low temp diffusions in the drain with various N+/
thoroughly studied.
I. Introduction
Within the context of a sustainable de to face the challenges of fossil en transports are becoming more electric require new generations of power electronic circuits. In particular, with wide bandgap semiconductors such as the driving circuitry that is still realiz technologies, has to be placed as clos the power devices and should be abl high temperature (≥ 200°C). In additi temperature constraint, ESD requirem integrated circuit to the system are part for example, in automotive applicat contact according to the IEC 61000- often required. It has to be reminded standard requires tests both for u powered systems. For the latter testin temperature has to be taken into acco design window.
The challenge of high temperature op Silicon On Insulator (SOI) technolog provide a perfect electric insulation active device. Regarding ESD r proposed protection should provide current but also work at high te performance being as insensitive as p parameter.
In this paper, we propose a stud protection solution based on mixing M structures in the same device tha triggering to reach high ESD robustn sensitivity to temperature.
operation MOS-IGBT pow SD protection in smart pow
technology
ess1,2, D. Trémouilles1,2, M. Bafleur1,2
7 avenue du colonel Roche, F-31077 Toulouse, France S, INSA, INP, ISAE ; UT1, UTM, LAAS ; F-31077 Toulou BT power clamp for high-temperature operation providin perature sensitivity. It is achieved by inserting in the sa /P+ ratios whose impact on RON and holding current a
n
evelopment and nergy shortage, cally driven and
r devices and h the advent of
s GaN and SiC, zed with silicon e as possible to le to operate at ion to this high ments from the ticularly severe:
tions, 2-8kV in -4-2 standard is d that this ESD unpowered and ng, the effect of ount in the ESD eration requires gy since it will n between each robustness, the
a high failure emperature, its
possible to this dy of an ESD
MOS and IGBT at allows SCR
ness and a low
II. SOI smart pow and proposed ESD
The chosen technology is a technology TFSMART 1 prov Semiconductors. TFSMART 1 CMOS DMOS merged technol technology, the buried oxide thicknesses are 500 nm and Between each device, the width o is equal to 0.8 μm, then provid insulation between active device AC conditions. The process co part for 5V supply voltage, later lateral pnp-transistors, P-type DMOS devices with complete between wells and vertical oxid wafer/substrate for different su power devices are optimized ranges (25V, 45V, 65V and 80V resistance. Figure 1 presents a sc of the technology for the P-typ power MOS devices, P-LDMOS
Figure 1: Cross-section of P-LDMO TFSMART 1 techn
wer clamp wer SOI
use, France
ng a very compact high- ame LDMOS device P+
at high temperatures is
er technology D protection
a SOI smart power vided by Telefunken
is a 0.8μm Bipolar logy on SOI. In this and active silicon d 2μm, respectively.
of the trench isolation ding a perfect electric es under both DC and ontains 0.8μm CMOS
ral npn-transistors and and N-type lateral deep trench isolation de isolation to handle upply voltages. These for various voltage V) and minimized on- chematic cross-section pe and N-type lateral
and N-LDMOS.
OS and N-LDMOS of ology.
Regarding the N-LDMOS devices, TFSMART 1 library contains two types of structures. The first one is named SBC (source body short), since the source N-diffusion is shorted to the P-type body diffusion.
This short is implemented by inserting within the source N-diffusion a P+-body contact. The second one, called SBO (source body open), has a shallow trench isolation (STI) between the source and the body contact. This latter structure allows biasing the body at a different voltage from the source.
In this technology, the N-LDMOS 25V with increased gate-drain ballasting distance is used to provide a high-voltage ESD power clamp. It is composed of 11 identical cells that are formed of two 150µm-fingers with closed gate and a central drain diffusion, the body being connected to the source. The corresponding surface is 302 µm x 183 µm and it provides a 2 KV HBM robustness (Imax = 1.7 A TLP) according to TFSMART1 foundry data [2]. The performance of this MOS-based protection structure, namely its on-resistance, is very sensitive to the temperature [1]. Its on-resistance increases from 3.8Ω at 25°C to 6.3Ω at 125°C. If this temperature behavior is not taken into account, it could induce detrimental effects such as a lower failure current and even could lead to not provide the expected protection due to the failing of compliance with the ESD design window.
To compensate this effect, the size of the power clamp protection has to be increased.
To cope with these issues, we contemplated developing a new ESD protection. The basic concept we study in this paper consists in combining MOS and bipolar effects in order to compensate the detrimental effects of the temperature. To improve the ESD robustness, we also take advantage of the turn-on of the parasitic thyristor of the structure that will provide a very low on-resistance.
Figure 2: Mixed structure LDMOS-LIGBT with P+/N+ ratio equal
To do so, we combine within the structure of the N- LDMOS a lateral IGBT by implementing in the drain region both N+ and P+ diffusions with different ratios.
An illustration of such implementation is shown in Figure 2 where the N+/P+ ratio is equal to 1. The protection is triggered via its gate to allow protecting low voltage circuitry and an early triggering of the structure (MOS then IGBT) to compensate the intrinsic SCR slow response. Such MOS-thyristor combination was already proposed to improve the performance of power device structures [3]. Using an LIGBT was already proposed to implement an efficient ESD power clamp in an SOI smart power technology [4]. The authors demonstrated the improved performance compared to an NDRIFTMOS device. However, combining the three devices in a single device was not yet studied.
Figure 3: Equivalent electrical schematic of the mixed structure
LDMOS-LIGBT.
The main concept is to combine and merge in the same device an LDMOS, which will turn on as soon as its gate is activated, a lateral IGBT that should allow reducing the on-resistance of the full device thanks to minority carrier injection and a thyristor to provide a high-current capability, as shown by the electrical schematic of Figure 3.
To study the impact of the N+/P+ ratio on the ESD performance, we designed a test chip with various structures going from a N-LDMOS to a LIGBT and mixed structures called 2P1N, 1P1N and 1P2N with respective N+/P+ ratio of 0.5, 1 and 2. The structures are designed in such a way that the gate can be externally biased. They are based one of the elementary cells of the NLDMOS25V-based power clamp (figure 4). In this cell the central N+ drain is replaced by an alternance of N+ and P+ diffusions with different respective ratios.
Figure 4: Layout of the mixed structures wi contact levels.
III. Static characteriz V) of the proposed st
Figure 5 presents the DC character mixed structure 1P2N at room temper varying from 1V to 4V. It can be n device prematurely switches into th whatever the VGS. The measuremen limited at 0.1 A, it is difficult to be su enters the IGBT mode before the SCR
Figure 5: DC characteristics for the mixed st room temperature for VGS varying from
To solve this issue, we carried measurement using a curve tracer (F confirmed that the device does not IGBT mode between NLDMOS and SC We observed the same behaviour wha ratio. In this technology, the designed optimised, and as a result, the paras triggered as soon as the IGBT is activ VI, we propose design solutions to mixed structures to get an effective I before SCR turn-on.
0 40 80 120
0 5 10
Current (mA)
Voltage (V)
ithout metal and
zation (I- tructures
rization for the rature with VGS
noticed that the he SCR mode nt setup being ure if the device
one.
tructures 1P2N at m 1 V to 4 V.
out the same Figure 6). This
switch into the CR modes.
atever the N+/P+ IGBT is not yet sitic thyristor is vated. In section
optimise these IGBT operation
Figure 6: 1P2N structure characteristic room temperature for VGS = 0 and 1 V
3 V (bottom). Dotted lines in botto
IV. Experimental re temperatu
To assess the ESD behavior an proposed structures, TLP measu out at wafer level on a Celestr bench. A calibration is performe measurement to eliminate the ser wire connections. TLP pulses h and a rise time of 1 ns.
The first set of measurement of was performed with their gates ti Figure 7 summarizes the results including the NLDMOS and th the N-LDMOS, it can be notice voltage reaches the breakdown includes a ballast resistor into th snaps back and fails. This beh four different devices (Figure 7).
15 20
VGS = 1V VGS = 2V VGS = 3V VGS = 4V
0 3 5 8 10
0 10 20
Current (mA)
Voltage (V)
0 30 60 90
0 1 2 3
Current (mA)
Voltage (V
cs using a curve tracer at (top), and for VGS = 2 and om figure indicate IH.
esults at room ure
nd robustness of the urements were carried
ron TLP (50 Ω) test ed before starting the ries resistances due to have 100 ns duration
the various structures ied to ground.
for all mixed devices he LIGBT. Regarding ed that as soon as the n voltage, although it he drain, the structure havior is observed on
.
30 40 50
VGS =0V VGS = 1V
4 5 6
V)
VGS = 2V VGS =3V
Figure 7: TLP characteristics of mixed structur LIGBT with VGS=0V.
For the mixed structures including the be first noticed that the triggering v than the one of the N-LDMOS: arou compared to 52V. This reduction is insertion of P+ diffusions within the their presence leads to a punch-throug PNP device created with the N-Dr regions of the N-LDMOS (Figure 1).
four tested structures have a ve robustness (>5.5A) and could not be d the limitation of the TLP test bench exhibit a very strong snapback me parasitic thyristor is homogeneously tr expected, structures with a smaller N+ lower on-resistance.
With a silicon surface divided by 11 structure provides a much higher ESD the initial power clamp whose maximu is 1.7A.
The structures are also characterized a the gate bias VGS. As shown in Figure voltage of 2V, the triggering voltage lowered and adjusted to a low compatible with the ESD design win voltage circuitry by tuning the gate vo current behavior, above one ampere identical to the one observed with a However, when a gate voltage is proposed structures start to turn-o LDMOS, then as an IGBT and finally, voltage and current is reached, the p activated. However, the current resolu test bench does not allow differentiati LDMOS and the IGBT mode. It is lik the DC measured behavior, the struc the SCR mode as soon as the IGBT is
0 1 2 3 4 5 6
0 10 20 30 40
TLP current (A)
TLP voltage (V) IGBT
2P1N 1P1N 1P2N
NLDMOS
res, NLDMOS and
e LIGBT, it can voltage is lower und 37V to be s related to the e drain. Indeed gh effect in the rift and P-Well
. Moreover, the ery high ESD destroyed due to h. All structures eaning that the
riggered [5]. As
+/P+ ratio have a 1, the proposed robustness than um current level as a function of 8 for a gate bias e can be easily
voltage value ndow of a low oltage. The high e of current, is
grounded gate.
s applied, the on first as an , when a certain parasitic SCR is ution of the TLP ing between the kely that, given ctures switch to activated. It has
strongly depends on the N+/P+ ratio, the lower is the SCR trigge These measurements are not per so as subsequent temperature m carried out. However, we can n although having a much better o a high resistance behavior above IGBT device is not a full IGBT minimum-size N+ diffusion in th to avoid design rules check err this diffusion might induce a focalization in the associated N However the high series resist allows a ballasting effect as sho second snapback toward the SCR
Figure 8: TLP characteristics of mixed s VGS=2V (top: full curve; bottom: deta
V. High temperatu
There are few publications stud behavior of ESD protections However, with a strong demand
50 60
1P2N 1P1N 2P1N IGBT NLDMOS
0 1 2 3 4 5
0 2 4
TLP current (A)
TLP voltage
0.0 0.1 0.2 0.3
0 2 4
TLP current (A)
TLP voltage
ratio. The lower this ering voltage.
rformed up to failure, measurement could be notice that the IGBT, on-resistance, exhibits e 2.3 A. Actually this T, since it includes a he center of the drain rors. The presence of a temporary current NPN bipolar device.
tance of its collector own by the onset of a R mode.
structures and LIGBT with ail of triggering region).
ure behavior
dying the temperature structures [1] [6].
d for high temperature
6 8
e (V)
1P2N 1P1N 2P1N IGBT
4 6
(V)
1P2N 1P1N 2P1N IGBT
an increasing need for high ESD powered systems, it is of great intere account this parameter for the desig protection structures.
We performed TLP measurement at different temperatures 25°C, 50°C, 10 We report in Figure 9 the measu respective on-resistance (RON) of LIG structures 2P1N, 1P1N and 1P2N w N+/P+ ratio of 0.5, 1 and 2 for differen It can be noticed that the temperatu strongly impacted by the N+/P+ ratio.
LIGBT structure (N+/P+ ratio=0) v whereas the RON of the other structure N+/P+ ratio varies in average by 135%
and 200°C.
The main interests for ESD protec exhibiting a low dependence with tem the one hand, to guarantee that they fit window whatever the temperature con the other hand, to limit the silicon oversizing will not be required to c degradation of their performance with can be concluded from the results of Fi results will be obtained with structu possible to a full IGBT. The best trade will be defined by the capability of withstand latch-up testing.
Figure 9: Measured on-resistance of LIGBT an 2P1N, 1P1N and 1P2N with respective N+/P+
and 2 at 25°C, 100°C and 200°
VI. Structure optimi
As previously noticed, in the high curr parasitic SCR turns on in all structur beneficial for the on-resistance of the this preliminary study, we did not holding current of the structures to gua safety. However we have evaluated a support further study. Using 50Ω or 50
0 0.5 1 1.5 2 2.5 3 3.5
0 0.5 1 1.5
Ron (Ohms)
N+/P+ ratio
robustness of est to take into gn of the ESD wafer level at 0°C and 200°C.
urement of the GBT and mixed
with respective nt temperatures.
ure behavior is The RON of the varies by 75%
es with a higher
% between 25°C ction structures mperature are on
the ESD design nditions and on area since no compensate the temperature. As igure 9, the best ures as close as e-off to be found
the structure to
nd mixed structures + ratio of 0, 0.5, 1
°C.
ization
rent regime, the res that is very e structure. For t optimize the arantee latch-up a test method to 00Ω TLP testing
does not allow properly cha holding current of the SCR.
continuously the ESD current un is the most appropriate way to m holding current. TLP being a pu cannot offer such a continuous TLP could be one solution bu selected, HBM-IV measurement and straightforward to carry out
Table 1: Measured holding current of th wafer-level HBM at 25°C, 50°C, 100°
25°C 50°C
LIGBT 7.0 mA 6.7 mA 2P1N 7.0 mA 6.3 mA 1P1N 7.0 mA 6.5 mA 1P2N 7.2 mA 6.7 mA We used a wafer-level HBM tes allows acquiring I-V characteris waveform. The falling part of current and voltage wavefor straightforward way to determi current. Indeed, in the falling waveform, the SCR is trigge decreasing current. When the cur maintain the SCR operation ( voltage across the device starts (Figure 10).
Figure 10: : Current and voltage cha level HBM of the structure 1P1N at V
and zoomed curve (b
2 2.5
Ron 25°C Ron 100°C Ron 200°C
aracterizing the real Indeed, decreasing ntil the SCR turns off measure the real SCR ulsed measurement, it decrease. Multilevel ut the technique we , appears much easier [10].
e different structures using C and 150°C at VGS=0V.
100°C 150°C 5.3 mA 5.0 mA 4.7 mA 5.0 mA 5.7 mA 5.3 mA 5.0 mA 4.8 mA ster from Hanwa that
tics with a real HBM f the temporal HBM
rms is used in a ine the SCR holding g part of the HBM
red and conducts a rrent is insufficient to (holding current) the
s to increase rapidly
aracteristics under wafer VGS = 0V (full curve (top) bottom)).
The values of the holding current o structures are summarized in Table temperatures. As it can be notice structures, its value is too low to guara free operation [7]. The targeted IH va higher or equal to 100 mA. It is interes this value is not very sensitive t Interestingly, it is not dependent on This means that the main parameters holding current are the ones not im ratio, i.e. the bipolar current gains and resistance.
The holding current is defined by parameters and equation [8]:
€
IH =βp(βn +1)⋅INW +βn(βp+1)⋅ βnβp −1
Where βn and βp are the current gains NPN and PNP bipolar transistors and currents flowing into the N-well respectively.
To increase IH, as we cannot modify t of the two bipolar transistors, the clas reduce as much as possible the resista wells [9]. In the proposed structur optimizing the N+/P+ ratio in the drain and introducing P+ diffusions into diffusion to reduce the P-Well resista the well resistances, the best solutio maximize the N+/P+ ratio into the minimizing it into the source. To fin trade-off between high IH and low on performed 3D simulations. They sho the N+/P+ ratio in both source and drain finely controlling and increasing IH w the ESD performance. However IH have shown that its value is almost ind N+/P+ ratio into the drain meaning triggering is mainly controlled by the bipolar transistor. Therefore, the mos to increase IH consists in engineering that controls the parasitic NPN bipolar All the structures used in this first test type since the original LDMOS was im way. A first solution to optimize the IH SBC-type structures that allows signifi the P-Well resistance (base of the transistor). Using Sentaurus TCAD, w 3D structure to check the impact o current. The structure under study i NLDMOS 25 V. We could not access
of the proposed 1 for various ed, for all the
antee a latch-up alues should be sting to note that
to temperature.
the N+/P+ ratio.
that defines the mpacted by this
the p-well body the following
⋅IPW
(1) of the parasitic
INW and IPW the l and P-well, the current gain ssical way is to ances of the two re, this means on the one hand
the N+ source ance. Regarding on would be to
drain whereas nd out the best n-resistance, we ow that varying n regions allows whereas keeping
H measurements dependent of the
that the SCR e parasitic NPN
st efficient way the source side transistor.
circuit are SBO mplemented that
H value is to use icantly reducing e NPN bipolar
we simulated a on the holding is based on an accurate doping
simulation on the NLDMOS 25V according to TLP measurement results can only be considere compare the relative efficiency solutions.
To perform the 3D simulation stationary simulation to minim since a transient simulation requ In addition, since the simulations low current regime around the h there is no need to activate the te To limit the computing time, the an elementary cell of 3µm-w computed IH should be scaled structure. According to equatio proportional to the well resistan currents, and a scaling coefficie According to the way we compu in the range of 6 to 10.
Figure 12 shows the differenc SBO 3μm-wide devices at ro VGS= 3 V for a mixed structur from 5 mA for a SBO structure one.
As the IH current increase from sufficient, another interesting reducing the channel by locally r N+ source diffusion by a P+ diffu diffusion into the source which channel. We named this structu structure SBC (Figure 11) The result of the 3D simulation Figure 11 shows that IH increas SBC mixed structure to 12 m mixed structure SBC (Figure 1 simulation-scaling coefficient, th be in the range of 100 mA theref up specification.
Figure 11: Optimized mixed str
V, we did some fitting t, but the simulation ed as qualitative to y of different design ns, we use a quasi- mize computing time
ires about one month.
s are carried out in the holding current point, emperature equations.
simulated structure is width. Therefore, the
according to the real n (1) IH is inversely nces via IPW and INW ent can be computed.
ute it, its value can be e between SBC and om temperature and re 1P1N. IH increases e to 8 mA for a SBC m 5 to 8 mA is not solution consists in replacing a part of the usion, or inserting a P+ h does not reduce the
ure Optimized mixed n for the structure of ses from 8 mA for a mA for an optimized 2). According to the he resulting IH should fore meeting the latch
ructure SBC 1P1N.
Figure 12: TLP characteristics difference between SBC mixed structure and reduced channel mixed channel at room temperature
and at VGS = 3V
When applying a voltage to the gate, it can be noticed that the SBC structure exhibits the three modes of operation: LDMOS, LIGBT and finally SCR (Figure 13). It can be noticed that the triggering of the IGBT occurs at a higher drain voltage for the optimized structure.
Figure 13: Comparison of DC characteristics: SBC mixed structure and Optimized mixed structure (reduced channel) at
room temperature and at VGS = 7V.
By measurement, we also evidenced another original way to control the triggering of the SCR by taking advantage of the gate bias. We measured the impact of the gate voltage on the value of the holding current (see Figure 6). The results, summarized in Table 2, shows that increasing the gate voltage allows significantly rising the value of the holding current.
From the grounded gate configuration to a VGS of 3V, an increase factor of 4 to 5 is observed for the holding current.
Table 2: Impact of VGS voltage on the value of holding current for the different structures.
VGS (V) 0 1 2 3
IH (1P2N)
mA 6 6 17.5 24
IH (1P1N)
mA 5.5 6 17 23
IH (2P1N)
mA 4.5 5.2 17 23
IH (IGBT)
mA 5.5 7 18 23
We attribute the gate bias effect on the holding current to the transition from a SCR to an IGBT conduction- mode as schematically represented on Figure 14. This implies that the holding current of the hybrid structure would correspond to the saturation current of the IGBT. This is indeed what is observed. As can be seen from figures 5 and 6, the saturation current at VGS = 4 V is about 20 mA which actually corresponds to the holding current of the structure at the same VGS
(Table 2).
To explain this behavior, we think that IGBT operation prevails on SCR one because the MOS transistor in parallel with the IGBT somewhat short- circuits the NPN bipolar transistor that is part of the SCR. Indeed, the MOS transistor injects electrons in the device N-Well drift region thus enhancing recombination of the holes injected by the PNP bipolar transistor and decreasing its collector current and as a result, the base current of the NPN bipolar transistor. This phenomenon might also be helped by the NPN-transistor current gain roll-down at low current density leading to a full shut down of the NPN transistor and by consequence of the SCR operation.
Of course, as measurement demonstrates that the SCR holding current can be controlled by the gate bias, such solution requires proper and intelligent control of the gate potential to really take advantage of this phenomenon. Indeed during normal circuit operation, when latchup could occur, gate control would allow switching from SCR uncontrolled operation to an IGBT operation that can then be switched off by pulling the gate back to ground. For unpowered operation a quite standard triggering circuit offering long enough gate biasing will be sufficient.
0 1 2 3
0 5 10 15 20 25 30
Current (mA)
Voltage (V)
SBC mixed structure Optimized SBC mixed structure
MOS
MOS + IGBT
Threshold 0
4 8 12 16 20
0 10 20 30 40 50
Current (mA)
Voltage (V)
Mixed structure SBO Mixed structure SBC
Optimized mixed structure SBC
Figure 14 : Illustration of the transition from conduction mode at two different
VII. CONCLUSION
We proposed a new MOS-IGBT po high-temperature operation and im robustness. The basic concept is structure as an IGBT but to also allo SCR triggering. To do so, we combine N-LDMOS a lateral IGBT by im diffusions in the N+ drain region with ratios. The proposed structures provi robustness (> 5.5 A) with a ten times area compared to the initial LDMO clamp. Another beneficial effect of thi the performance of the ESD protection less sensitive to temperature. We pr design solutions to improve the immu of these structures by engineering the the one hand, and providing an additio the gate, on the other hand. These validated through comparative 3D silicon test vehicle including various i of these solutions was designed but w on time for the final version of this pap Acknowledgements
This work has been sponsored by Recherche pour l'Aéronautique (http://www.fnrae.org/) within the Fram collaborative project COTECH.
References
[1] T. J. Maloney, and S. Dabral, Novel C
m SCR to IGBT t VGS
ower clamp for mproved ESD
to trigger the ow its parasitic ed within a same mplementing P+
different N+/P+ de a high ESD s smaller silicon OS-based power
is design is that n becomes much oposed original unity to latch-up source side, on onal control via
solutions were simulations. A implementations was not available
per.
Fondation de et l'Espace mework of the
Clamp Circuits
Components, Packaging, An Technology—Part C, Vol. 19, N°. 3 [2] SMARTIS 1, Design SIS1_0.32_071005, Atmel Germany 2005, http:// www.telefunkensemi.co [3] H. Tranduc, P. Rossel, M. Gharb Charitat, Le transistor-thyris semiconducteur (T2 MOS), Rev. Ph 575-581 (1985)
[4] Gevinti, E.; Cerati, L.; Sambi Cecchetto, L.; Andreini, A.; Tazzo G.;Novel 190V LIGBT-based E 0.35μm Smart Power technology substrate, Electrical Overstress/Ele Symposium, 2008. EOS/ESD 2008.
[5] D. Pogany, D. Johnsson, S. Bych Rodin, M. Stecher, E. Gornik, Measuring Holding Voltage Relate Current Flow in Wide ESD Protect Multilevel TLP, IEEE Transact Devices, Vol. 58, N° 2, February 20 [6] S-L. Jang, J-K. Lin, Temper steady-state characteristics of SCR- circuits, Solid-State Electronics, 44, [7] IC Latch-Up Test, JEDEC Revision of JESD78B, December 2010.
[8] R.R. Troutman, Latchup in CM problem and the care, Kluwer, 1984 [9] M. Mergens, C. Russ, K. Verha Jozwiak and R. Mohn, High ho (HHI-SCR) for ESD protection and operation, Microelectronics Relia Issue 7, July 2003, Pages 993-1000.
[10] M. Scholz et al Calibrat Measurements for Quasi-Static a Analysis. EOS/ESD SYMPOSIUM,
nd Manufacturing , July 1996.
Manual, Release : y GmbH, October 7, om/
bi, J.L. Sanchez et G.
stor métal-oxyde- hys. Appl. (Paris) 20,
, M.; Dissegna, M.;
oli, A.; Meneghesso, ESD protection for
y realized on SOI ectrostatic Discharge
30th, 211 - 220 hikhin, K. Esmark, P.
and H. Gossner, ed to Homogeneous tion Structures Using
tions On Electron 11, 411-418.
ature-dependence of -type ESD protection
2000, 2139-2146 Standard JESD78C, 2008, SEPTEMBER MOS technology: the
.
aege, J. Armer, P. C.
lding current SCRs latch-up immune IC ability, Volume 43,
ed Wafer-Level HBM and Transient Device
(September 16, 2007)
