NEe CATALOG

1981 CATALOG NEe Microcomputers, Inc.

NEe

© 1981 NEe Microcomputers, Inc.

The information presented in this document is believed to be aCCUrate and reliable.

The information is subject to change without notice.

Printed in USA

ttiEC ^CONTENTS

FUNCTIONAL AND NUMERICAL INDEXES ROM ORDERING PROCEDURE

. NEC Microcomputers, Inc.

1981

Product Catalog

MEMORY SELECTION GUIDE AND ALTERNATE SOURCE GUIDE

RANDOM ACCESS MEMORIES

READ ONLY MEMORIES

MICROCOMPUTER SELECTION GUIDE AND ALTERNATE SOURCE GUIDE

SINGLE CHIP 4-BIT MICROCOMPUTERS

SINGLE CHIP 8-BIT MICROCOMPUTERS

M ICROPROC ESSORS

PERIPHERALS

BOARD PRODUCTS

REFERENCE SECTION Quality Assurance Chart Representatives & Distributors

II

II

II II

II

II

II

II

II

1m

III

NOTES

NEe Microcomputers, Inc. NEe

FUNCTIONAL INDEX

RANDOM ACCESS MEMORIES

Selection Guide. . . . . 8

Alternate Source Guide 9 Dynamic NMOS RAMs !,PD411 .. . 11

!,PD411A 19 !,PD416 . . . . 27

!,PD2118 . 37 !,PD4164 47 Static NMOS RAMs !,PD4104 . . . 53

!,PD2114l . . . 59

!,PD2147 65 !,PD2149 . . . 71

!,PD421 . . . . 77

!,PD2167 . 81 Static CMOS RAMs !,PD5101l 83 !'PD444/6514. . . .. 89

!,PD445l . . . . 93

!,PD446 . . . .. 99

!,PD447 . . . . . 105

PROGRAMMABLE READ ONLY MEMORIES Selection Guide. . . . 8

Alternate Source Guide . . 9

ROM Ordering Procedure . 111 Mask Programmable ROMs !,PD2308A . . . 113

!,PD2316E . . . 117

!,PD2332A/8 . . . . 121

!,PD2364 . . . 125

!'PD23128... 129

Field Programmable ROMs (Bipolar) !'PD406/426 133 !'PD409/429 . . . 137

(U.V. Erasable) !,PD2716 . . . 143

!'~V~ . . . 1G Bipolar Field Programmable logic Arrays !,PD450 . . . 151

SINGLE CHIP 4-BIT MICROCOMPUTERS Selection Guide. . . . 155

Microcomputer Alternate Source Guide . . . . 157

ROM Ordering Procedure 1.11 !,COM-4 . . . . . . 159

!,COM-43 . . . 169

!,PD546 . . . 173

!,PD553 . . . 175

!,PD557l . . . 177

!,PD650 . . . 179

~OMM . . . 1~

!,PD547 . . . 185

!,PD5471 . . . 187

!,PD552 . . . 189

!,PD651 . . . 191

!,COM-45 . . . . 193

!,PD550 . . . 195

!,PD550L . . . 197

!,PD554 . . . . 199

!,PD554l .. . . 201

!,PD652 . . . . 203

Evaluation Chip !,PD556 . . . 205

!,COM-75 !,PD7502 . . . 209

!,PD 7503 . . . 223

!,PD7507 . . . 225

!,PD7520 . . . . . . 227

Evaluation Chip !,PD7500 '" . . . .. 237

SINGLE CHIP 8-BIT MICROCOMPUTERS Selection Guide. . . . 155

Alternate Source Guide . . . 157

ROM Ordering Procedure . . . 111

!,PD7800 . . . 239

!,PD7801 . . . 251

!,PD7802 . . . 277

!,PD8021 . . . 303

!' PD8022 . . . 309

!,PD8041 . . . 315

!,PD8041A/8741A . . . 323

!'PD8048/8748/8035L . . . 333

!,PD80C48/80C35 . . . 345

!'PD8049/8039L . . . 357

MICROPROCESSORS Selection Guide . . . 155

Alternate Source Guide . . . _ . 157 !,PD780 . . . 367

!,PD8080AF . . . 383

!,PD8085A . . . 397

!,PD8086 . . . _ . 411 PERIPHERALS Selection Guide . . . 155

Alternate Source Guide . . . 157

!,PD765 . . . . 423

!,PD781 . . . 443

!,PD782 . . . 455

!,PD3301 . . . • . 467

!,PD7001 • . . . • . 475

!,PD7002 . . . 479

!,PD7201 . . . 483

!,PD7210 . . . 495

!,PD7225 . . . 505

!,PD7227 . . . 517

!,PD7720 . . . 519

!,PD8155/8156 . . . ' . . . . 537

!,PB8212 . . . 545

!,PB8214 '. . . . 553

!'PB8216/8226 . . . . 561

!,PB8224 . . . 565

!,PB8228 . . . 571

!,PD8243 . . . • . . . 577

!'PD8251/8251A . . . . 583

!,PD8253/8253-5 . . . . 601

!'PD8255/8255A-5 . . . . 609

!'PD8257/8257-5 . . . . 617

!'PD8259/8259-5 . . . . 625

!,PD8259A . . . 641

!,PD8279-5 . . . 659

!'PB8282/8283 . . . 669

!,PB82B4 . . . 673

!'PB8286/8287 . . . 681

!,PB8288 . . . • . . . 687

!'PD8355/8755A . . . 695

BOARD PRODUCTS BP-0200 . . . 703

BP-0220 . . . 705

BP-0575 . . . . • . • . . . 707

BP-2190 . . . 709

NOTES

NEe Microcomputers, Inc. NEe

NUMERICAL INDEX

PRODUCT PAGE

ILCOM4 . . . 159

ILCOM43 . . . 169

ILCOM44 . . . 181

ILCOM45 . . . 193

ILPB406/426 . . . 133

ILPB409/429 . . . 137

ILPD411 . . . 11

ILPD411A . . . 19

, ILPD416 . . . .. , 27--

ILPD421 . . . 77

ILPD444/6514 . . . , 89

ILPD445L . . . .. 93

ILPD446 . . . .. 99

ILPD447 . . . 105

ILPB450 . . . 151

ILPD546 . . . 173

ILPD547 . . . 185

ILPD547L . . . 187

ILPD550 . . . 195

ILPD550L . . . 197

ILPD552 . . . 189

ILPD553 . . . 175

ILPD554 . . . 199

ILPD554L . . . 201

ILPD556 . . . 205

ILPD557 L . . . 177

ILPD650 . . . 179

ILPD651 . . . 191

ILPD652 . . . 203

ILPD765 . . . 423

ILPD780 . . . 367

ILPD781 . . . 443

ILPD782 . . . 455

ILPD2114L . . . 59

ILPD2118 . . . 37

ILPD2147 . . . 65

ILPD2149 . . . 71

ILPD2167 . . . 81

ILPD2308A . . . 113

ILPD2316E . . . 117

ILPD2332A/B . . . 121

ILPD2364 . . . 125

ILPD2716 . . . 143

ILPD2732 . . . 149

ILPD3301 . . . 467

ILPD4104 . . . 53

ILPD4164 . . . 47

ILPD51 01 L . . . 83

ILPD7001 . . . 475

PRODUCT PAGE ILPD7002 . . . 479

ILPD7201 . . . 483

pPD7210 . . . 495

pPD7225 . . . 505

pPD7227 . . . 517

ILPD7500 . . . 237

pPD7502 . . . 209

pPD7503 . . . 223

pPD7507 . . . 225

pPD7520 . . . 227

.uPD7720 . . . 519

pPD7800 . . . 239

ILPD7801 . . . 251

pPD7802 . . . 277

pPD8021 . . . 303

pPD8022 . . . • . . 309

pPD8041 . . . 315

pPD8041 A/8741 A . . . 323

pPD8048/8748/8035 L . . . 333

pPD80C48/80C35 . . . 345

pPD8049/8039L . . . 357

pPD8080AF . . . 383

pPD8085A . . . 397

pPD8086 . . . 411

pPD8155/8156 . . . 537

pPB8212 . . . 545

pPB8214 . . . 553

pPB8216/8226 . . . 561

pPB8224 . . . 565

pPB8228 . . . 571

pPD8243 . . . 577

pPD8251 /8251 A . . . 583

pPD8253/8253-5 . . . 601

pPD8255/8255A-5 . . . 609

pPD8257/8257-5 . . . 617

pPD8259/8259-5 . . . 625

pPD8259A . . . 641

pPD8279·5 . . . 659

pPB8282/8283 . . . 669

pPB8284 . . . 673

pPB8286/8287 . . . • 681

pPB8288 . . . 687

pPD8355/8755A . . . 695

pPD23128 . . . 129

BP'()200 . . . 703

BP-0220 . . . 705

BP-0575 . . . 707

BP-2190 . . . 709

NOTES

MEMORIESfi

7

NEe Microcomputers, Inc.

MEMORY SELECTION GUIDE

DEVICE

DYNAMIC RANDOM ACCESS MEMORIES

pPD41 1 4K xl TS NMOS 150 ns

pPD411·4 4K xl TS NMOS 135 ns

,uPD411A 4K xl TS NMOS 200 ns

pPD416 16K x 1 TS NMOS 120 ns

pPD2118 16K xl TS NMOS 100 ns

,uPD4164 64K xl TS NMOS. 150 ns STA TIC RANDOM ACCESS MEMORIES

pPD5101 L 256 x 4 TS CMOS 450 ns pPD444/6514 lK x 4 TS CMOS 200 ns ,uPD445L lK x 4 TS CMOS 450 ns

pPD446 2K x 8 TS CMOS 120 ns

pPD447 2K x 8 TS CMOS 120 ns

pPD4104 4K x 1 TS NMOS 200 ns pPD2114L lK x 4 TS NMOS 150 ns ,uPD2147 4K x 1 TS NMOS 45 ns pPD2149 1 K x 4 TS NMOS 35 ns

pPD421 lK x 8 TS NMOS 150 ns

pPD2167 16K x 1 TS NMOS 55 ns MASK PROGRAMMED READ ONL Y MEMORIES pPD2308A 1 K x 8 TS NMOS 450 ns ,uPD2316E 2K x 8 TS NMOS 450 ns ,uPD2316E· 1 2K x 8 TS NMOS 350 ns pPD2332A/B 4K x 8 TS NMOS 450 ns pPD2332A/B· 1 4K x 8 TS NMOS 350 ns ,uPD2364 8K x 8 TS NMOS 450 ns

,uPD23128 16Kx8TS NMOS 250 ns

FIELD PROGRAMMABLE READ ONL Y MEMORIES (Bipolar)

,uPB406 lK x 4 OC ,uPB426 1 K x 4 TS ,uPB409 2K x 8 OC ,uPB429 2K x 8 TS (Bipolar Logic Array)

,uPB450 9216 bit

(U.V. Erasable)

,uPD2716 2K x 8 TS ,uPD2732 4K x 8 TS Notes: O.C. = Open Collector

C - Plastic Package

BIPOLAR BIPOLAR BIPOLAR BIPOLAR BIPOLAR NMOS NMOS

D - Hermetic Package

50 ns 50 ns 50 ns 50 ns 200 ns 450 ns 450 ns

380 ns +12,+5,-5 320 ns +15,+5,-5 400 ns +12,-+:5,-5 320 ns +12,+5,-5 235 ns +5 270 ns +5

450 ns +5 200 ns +5 450 ns +5 120 ns +5 120 ns +5 310 ns +5 150 ns +5 45 ns +5 35 ns +5 150 ns +5 55 ns +5

450 ns +5 450 ns +5 350 ns +5 450 ns +5 350 ns +5 450 ns +5 250 ns +5

50 ns +5 50 ns +5 50 ns +5 50 ns +5 200 ns +5 450 ns +5 450 ns +5

NEe

D 22

D 22

C 22

C/D 16

C/D 16

C/D 16

C 22

C 18

C 20

C/D 24

C/D 24

C/D 18

C/D 18

D 18

D 18

D 22

D 20

C/D 24

C 24

C 24

C 24

C 24

C 24

C 28

C/D 18

C/D 18

C/D 24

C/D 24

D 48

D 24

D 24

NEe Microcomputers, Inc. NEe

MEMORY ALTERNATE SOURCE GUIDE

I

MANUFACTURER PART NUMBER, DESCRIPTION NEC REPLACEMENT

I

AMD 2716 2K x 8 EPROM IlPD2716

27S33 lK x 4 PROM IlPB426

8308 lK x 8 ROM IlPD2308A

9016 16K x 1 DRAM IlPD416

9060 4K x 1 DRAM IlPD411/411A

II

9107 4K x 1 DRAM IlPD411/411A

9114 lK x 4 SRAM IlPD2114L

9124 lK x 4 SRAM IlPD2114L

9147 4K xl SRAM IlPD2147

9216 2K x 8 ROM IlPD2316E

AM91 L14 lK x 4 SRAM IlPD444/IlPD6514

AM91 L24 lK x 4 SRAM IlPD444/IlPD6514

EM&M 2114 lK x 4 SRAM IlPD2114L

Bl08 lK x B SRAM IlPD421

FAIRCHILD 93453 lK x 4 PROM IlPB426

93511 2K x 8 PROM IlPB429

F2114 lK x 4 SRAM IlPD2114L

F2716 2K x 8 EPROM IlPD2716

F16K 16K

x

1 DRAM IlPD416

FUJITSU 7122 lK x 4 PROM IlPB426

7138 2K x 8 PROM IlPB429

MBM2147 4K xl SRAM IlPD2147

MBM2716 2K x 8 EPROM ,uPD2716

MBM2732 4K x 8 EPROM ,uPD2732

MB8107 4K x 1 DRAM IlPD411/IlPD411 A

MB8114 lK x 4 SRAM ,uPD2114L

MB8116 16K x 1 DRAM ,uPD416

MB8216 16K x 1 DRAM ,uPD416

MB8264 64K x 1 DRAM ,uPD4164

MB8308 lK x 1 ROM IlPD2308A

MB8414 lK x 4 SRAM PD444/6514

HARRIS 7643 lK x4 PROM IlPB426

76161 2K x 8 PROM ,uPB429

HM6501 256 x 4 SRAM IlPD5101L

HM6514 lK x 4 SRAM IlPD444/6514

HITACHI HM4334 lK x 4 SRAM IlPD444/6514

HM435101 256 x4 SRAM IlPD5101L

HN462716 2K x 8 EPROM IlPD2716

HN462732 4K x 8 EPROM ,uPD2732

HM472114 lK x 4 SRAM ,uPD2114

HM4716A 16K x 1 DRAM IlPD416

HM4816 16K x 1 DRAM ,uPD2118

HM4864 16K x 1 DRAM IlPD4164

HM4864 64K x 1 DRAM IlPD4164

HM6116 2K x 8 SRAM ,uPD446

NEe Microcomputers, Inc. NEe

MEMORY ALTERNATE SOURCE GUIDE

l

MANUFACTURER PART NUMBER DESCRIPTION NEC REPLACEMENT

I

HITACHI (CaNT.) HM6147 4K xl SRAM f.LPD2147

HM6148 1 K x 4 SHAM f.LPD444/6514

INTEL 2107 4K x 1 DRAM f.LPD411/f.LPD411A

2114 1K x 4 SRAM f.LPD2114L

2117 16K x 1 DRAM f.LPD416

2118 16K x 1 DRAM f.L PD2118

2141 4K xl SRAM f.LPD4104

2147 4K xl SRAM f.LPD2147

2164 64K x 1 DRAM f.LPD41 64

2167 16K xl SRAM f.LPD2167

2308A 1K x 8 ROM f.LPD2308A

2316E 2K x 8 ROM f.LPD2316E

2332 4K x 8 ROM f.LPD2332A/8

2364 8K x 8 ROM f.LPD2364

2716 2K x 8 EPROM f.LPD2716

2732 4K x 8 EPROM f.LPD2732

3625 1K x 4 PROM f.LPB426

3636·1 2K x 8 PROM f.LPB429

5101 256 x 4 SRAM - f.LPD5101L

MITSUBISHI M5K4164$ 64K x 1 DRAM f.LPD4164

MMI 63S1681 2K x 8 PROM f.LPB429

63S441 lK x'4 PROM f.LPB426

6353 1Kx4PROM f.LPB426

MOTOROLA MCM2132 2K x 8 EPROM f.LPD2732

MCM4516/4517 16K xl DRAM f.LPD2118

MCM6665 64K x 1 DRAM f.LPD4164

7643 lK x 4 PROM f.LPB426

NATIONAL MM2732 2K x 8 EPROM IlPD2732

NMC4164 64K x 1 DRAM f.LPD4164

NMC5295 16K x 1 DRAM f.LPD2118

74S573 lK x 4 PROM f.LPB426

OKI MSM5114 1K x 4 SRAM f.LPD444/6514

RAYTHEON 29681 2K x 8 PROM IlPB429

SIGNETICS 82S137 lK x4 PROM f.LPB426

82$191 2K x 8 PROM f.LPB429

T.!. TMS4164 64K xl DAAM f.LPD4164

TMS4516 16K x 1 DRAM f.LPD2118

TBP24S41 lK x 4 PROM f.LPB426

TBP28S166 2K x 8 PROM f.LPB429

74S476 lKx4PROM f.LPB426

NEe Microcomputers, Inc. NEe

!J PD411

JJ PD411·1 f'PD411·2 ,... PD411·3

flo PD411·4

FULLY DECODED RANDOM ACCESS MEMORY o

ESCR I PTION The J,lPD411 Family consists of six 4096 words by 1 bit dynamic N-channel MOS

RAMs. They are designed for memory applications where very low cost and large bit storage are important design objectives. The J,lPD411 Family is designed using dynamic circuitry which reduces the standby power dissipation.

Reading information from the memory is a non-destructive. Refreshing is easily accomplished by performing one read cycle on each of the 64 row addresses. Each row address must be refreshed every two milliseconds. The memory is refreshed whether Chip Select is a logic high ol'a logic low.

FEATUR ES All of these products are guaranteed for operation over the 0 to 70°C temperature range.

Important features of the fJPD411 family are:

• Low Standby Power

• 4096 words x 1 bit Organization

• A single low-capacitance high level clock input with solid ±1 volt margins.

• Inactive Power/0.3 mW (Typ.)

• Power Supply: +12, +5, -5V

• Easy System Interface

• TTL Compatible (Except CE)

• Address Registers on the Chip

• Simple Memory Expansion by Chip Select

• Three State Output and TTL Compatible

• 22 pin Ceramic Dual-in-Line Package

• Replacement for INTEL'S 2107B, TI'S 4060 and Equivalent Devices.

• 5 Performance Ranges:

ACCESS TIME RIW CYCLE RMW CYCLE REFRESH TIME

)1PD411 300 ns 470 ns 650 ns ? ms

)1PD411·1 250 ns 470 ns 640 ns 2 ms

)1PD411·2 200 ns 400 ns 520 ns 2 ms

)1PD411·3 150 ns 380 ns 470 ns 2 ms

)1PD411-4 135 ns 320 ns 320 ns 2 ms

PIN CONFIGURATION ^{VBB vss} PIN NAMES

Ag 2 AS AO All Address Inputs

AlO A7

AO AS Refresh Addresses

CE Chip Enable

A11 ₄

A6 CS Chip Select

CS 5

jJPD ^VDD

DIN 6 411 ^CE

DiN Data Input

DOUT Data Output

WE Write Enable

NC VDD Power (+12V)

8 _As ^VCC Power (+5V)

VSS Ground

9 A4 VBB IPower

A2 10 A3 ^NC No Connection

VCC 11 WE

Rev/3

II

}LPD411

CE Chip Enable

A single external clock input is required. All read, write, refresh and read·modify·write operations take place when chip enable input is high. When the chip enable is low, the memory is in the low power standby mode. No read/write operations can take place because the chip is automatically precharging.

CS Chip Select

The chip select terminal affects the data in, data out and read/write inputs. The data input and data output terminals are enabled when chip select is low. The chip select input must be low on or before the rising edge of the chip enable and can be driven from standard TTL circuits. A register for the chip select input is provided on the chip to reduce overhead and simplify system design.

WE Write Enable

The read or write mode is selected through the write enable input. A logic high on the WE input selects the read mode and a logic low selects the write mode. The WE terminal can be driven from standard TTL circuits. The data input is disabled when the read mode is selected.

AO-A" Addresses

All addresses must be stable on or before the rising edge of the chip enable pulse. All address inputs can be driven from standard TTL circuits. Address registers are pro- vided on the chip to reduce overhead and simplify system design.

DIN Data Input

Data is written during a write or read-modify-write cycle while the chip enable is high.

The data in terminal can be driven from standard TTL circuits. There is no register on the data in terminal.

DOUT Data Output

The three state output buffer provides direct TTL compatibility with a fan-out of two TTL gates. The output is in the high-impedance (floating) state when the chip enable is low or when the Chip Select input is high. Data output is inverted from data in.

Refresh

Refresh must be performed every two milliseconds by cycling through the 64 addresses of the lower-order-address inputs AO through A5 or by addressing every row within any 2-millisecond period. Addressing any row refreshes all 64 bits in that row.

The chip does not need to be selected during the refresh. If the chip is refreshed during a write mode, the chip select must be high.

AO ROW -oVDD

Al

A2 DECODE 64 MEMORY --<> VCC

A3 AND ARRAY _{- ¢} VSS

A4 BUFFER 64 X 64 --<> VBB

A5

CE DIN WE CS

DOUT A6 AS A10

A7 Ag A11

FUNCTIONAL DESCRIPTION

BLOCK DIAGRAM

ABSOLUTE MAXIMUM RATINGS*

DC CHARACTERISTICS

CAPACIT ANCE

Operating Temperature.

Storage Temperature All Output Voltages ..

All Input Voltages . . . Supply Voltage VDD ..

Supply Voltage Vee Power Dissipation . . . Note:

CD

Relative to VBB

f.LPD411 FAMILY (EXCEPT 411-41

... oOe

to +70^o

e

-55°C to +150^oe -0.3 to +20 Volts -0.3 to +20 Volts -0.3 to +20 Volts -0.3 to +20 Volts . . . 1.0W

JLPD411

f.LPD411-4 . +1O^oe to +55°e . .. -55°C to +150^oe -0.3 to +25 Volts

CD

-0.3 to +25 Volts·

CD

-0.3 to +25 Volts

CD

-0.3 to +25 Volts

CD

. . . . 1.5W COMMENT: Stress above those listed ·under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

"Ta = 25'C

Ta "" o°c to 70°C, Voo "" +12V ±5%, Vee = +5V ±S%-, Ves '" -5V ±5%, VSS = av.

Except VOO = +15V ±5%- for 4114.

LIMITS

PARAMETER SYMBOL UNIT

MIN TYP(D MAX

Input Load Current ILl 0.01 10 "A

CE Input Load Current ILC 0.01 10 "A

Output Leakage Current

ILO 0.01 10 "A

for High Impedance State VOO Supply Current

100 OFF 20 200 "A

during CE off V DO Supply Current

IOOON

during CE on 35® SO@ mA

Average VOO Current

"P0411 IOOAV 37 60 mA

"PD411·1 IOOAV 37 60 ",A

"P0411·2 IODAV 37 60 mA

"P0411·3 IOOAV 41 65 mA

"P0411-4 IOOAV 55 80 mA

Vaa Supply Current ® IBS 5 100 "A

V CC Supply Current

ICC OFF 0.01 10 "A

during CE off @

Input Low Voltage VIL 1.0 0.6 V

Input High Voltage VIH 2.4 VCC+l V

CE Input Low Voltage VILC 1.0 0.6 V

CE Input High Voltage VIHC VDO-l VDO VOO+1 V

Output Low Voltage VOL 0 0.40 V

Output High Voltage VOH 2.4 Vee V

Notes: <D Typical values are for Ta '" 25°C and nomln,.1 power supply voltages.

@ The ISS current is the sum of all leakage current.

@ During ce on VCC supply current is dependent on output loading.

Vee is connected to output buffer onlv.

@ 65 mA fo, "PD411-3 80 mA for JJ.P0411-4

® 41mAlo,"P0411-3 55 rnA for p,pD411-4

Ta=O" -70"C

LIMITS

TEST CONDITIONS

VIN '" VIL MIN to VIH MAX VIN '" VILe MIN to VIHC MAX CE = VILC or CS = VIH VO:: OV to 5.25V CE:: 1.0V to O.SV

CE::: VIHC. T a = 25°C Ta:: 25°C Cycle Time:: 470 ns CYcle Time = 470 ns Cycle Time :c 400 ns Cycle Time = 380 ns CYcle Time = 320 ns

CE "" VILC or CS = VIH

IOL =3.2mA IOH =2.0 mA

TEST

PARAMETER SYMBOL UNIT

CONDITIONS MIN TVP MAX

Address Capacitance, CS CAD 4 6 pF VIN = Vss

CE Capacitance CCE 18 27 pF VIN = VSS

Data Output Capacitance CoUT 5 7 pF VOUT=OV

01 N and WE Capacitance CIN 8 10 pF VIN = VSS

II

P. PD411

READ CYCLE

Ta "" O°C to 70°C. VOO '" 12V ± 5%, Vee = 5V ± 5%, Vas ~ -5V ± 5%, Vss = av. unless otherwise noted, Except VOO '" +15V ± 5% for 411-4

LIMITS

PARAMETER SYMBOL ,uPD411 ~PD411·1 IJP0411-2 "P04"-3 jjPD411-4 MIN MAX MIN MAl< MIN MAX MIN MAX MIN MAX

Time Between Refresh tREF 2 2 2 2 2

Address to CE Set Up Time tAC 0 0 0 0 0

Address Hold Time tAH 150 150 150 150 100

eE Off Time tcc 130 170 130 130 80

eE Transition Time tT 0 40 0 40 0 40 0 40 0 40

CE Off to Output High tCF 0 130 0 130 0 130 0 130 0 130

Impedance State

Cycle Time tCY 470 470 400 380 320

CE on Time tCE 300 3000 260 3000 230 3000 210 3000 200 3000

CE Output Delay tco 280 230 180 130 115

Access Time tAce 300 250 200 150 135

CE to WE tWl 40· 40 40 40 40

WE to CE on twc 0 0 0 0 0

WRITE CYCLE

Ta '" O°C to 70°C, VOO '" 12V ± 5%, Vee'" 5V ± 5%, Vas'" -5V ± 5%, Vss '" av. unless otherwise noted, Except VOO '" +15V ± 5% for 411-4

LIMITS

PARAMETER SYMBOL ,uP0411 jJP0411-1 jJPD411·2 "P04"-3 ,uPD411-4 MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX

Cycle Time tey 470 470 400 380 320

Time Between Refresh tREF 2 2 2 2 2

Address to CE Set Up Time tAC 0 0 0 0 0

Address Hold Time tAH 150 150 150 150 100

CE Off Time tcc 130 170 130 130 80

CE Transition Time tT 0 40 0 40 0 40 0 40 0 40

CE Off to Output High tCF 0 130 0 130 0 130 0 130 0 130 Impedance State

CE on Time tCE 300 3000 260 3000 230 3000 210 3000 200 3000

WE toCEoff tw 180 180 150 150 65

CE to WE tcw 300 260 230 210 200

D,N to WE Set UpG) tow 0 0 0 0 0

OJ N Hold Time tOH 40 40 40 40 40

WE Pulse Width twp 180 180 150 100 65

Note:

<D

If WE is low before CE goes high then DIN must be valid when CE goes high.

READ - MODIFY - WRITE CYCLE

T a'" O°C to 70°C, VDO >= 12V ± 5%, Vce::o 5V ,± 5%, VeB '" 5V ± 5%, VSS "' OV, unless otherwise noted, Except VDD '= +15V ± 5% for 411·4 .

LIMITS

PARAMETER SYMBOL J,lPD411 ~O4"-' ~PD411-2 "P04"-3 ^~PD411-4 MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX

Read-Modify-Write tRwe 650 640 520 470 320

(RMWI Cycle Time

Time Between Refresh tREF 2 2 2 2 2

Address to CE Set Up Time tAC 0 0 0 0 0

Address Hold Time tAH 150 150 150 150 100

CE Off Time tcc 130 170 130 130 80

CE Transition Time tT 0 40 0 40 0 40 0 40 0 40

CE Off to Output High tCF 0 130 0 130 0 130 0 130 0 130 I mpedance State

CE Width During RMW tCRW 480 3000 430 3000 350 3000 300 3000 200 3000

WE to CE on twc 0 0 0 0 0

WE to CEoff tw 180 180 150 150 _65

WE Pulse Width twp 180 180 150 100 65

DIN to WE Set Up tow 0 0 0 0 0

DIN Hold Time tDH 40 40 40 40 40

CE to Output Display tco 280 230 180 130 115

Access Time tACC 300 250 200 150 135

AC CHARACTERISTICS

UNIT

ms ns ns ns ns ns ns ns ns ns ns ns

UNIT

ns ms ns ns ns ns ns ns ns ns ns ns ns

UNIT

ns ms ns ns ns ns ns

ns ns ns ns ns ns ns ns

TIMING WAVEFORMS

","PD411

READ CYCLE

CD

'CE

CE

f - - - -tACC _ _ _ _ _ ~

CD For ,e/'esh cvcle 'Ow and column add,,,ss,,, musl be ,table TAC and ,ema,n .table lor entn" tAH period

@ VOO 2V IS the reference level 1o, measurong tImIng of CE

@ VSS • 2V IS the ,,,ference level for mea"",ng !Omlng 01 CE

@ VIHMIN" Ihe ,,,ierence level 1of meawrong Hm,,,,,, 01 the addresses, CS, WE and DIN

® VI LMAX IS the reference level 10' meaSU""9 tIming of Ihe add,e'S"5, Cs, WE and DIN

® VSS .2.QV oS the reference lev"llor measurIng !lm,ng 01 Dour.

CD VSS -Q.BV I, the ,,,Ie,ence level lor mea!u,,,,,! limIng 01 Dour

WRITE CYCLE

t - - - ' C y - - - !

CE

----~::::;;;:==.::::::.:===rt=;;;;;=::l

r-++=o-:---+- V'H

----+---,.j,,--'---f-'--""'-:-,..,.,,+-^V,H ----+---1.1"---f-'--, '---"-=::.::...+--V IL

Notes G) VOO -2V IS Ihe ,,,Ierence level for mealu,;ng 1,m"1gof CE

® VSS '2v IS the ,eterence level for measu'""9 ItrT""9 01 CE

@ VIHMIN" The reference level lor measu"ngTlm,ng 01 The addresses, Cs, WE and DIN

@) VILMAX" The releren<;e level 10' mea\U"ngT,mmg ollhe addresses, CS, WE and DIN

READ-MODI FY-WRITE CYCLE

t - - - ' R W C - - - i

CE

Ao -All

ANDCS

tCRW 'CC

V'H

I~==~========~!:====~ct:::::==~_++_---+_--VIH

---+-+r---"\.,,---'---~-t_'_--.,,~r::___:_:_::_+-VIH --+-+r---'1'---I--::~p.-==:_+-V<L DOUT =HIGH - -f-'---.J.----V.-L-'o---I---i

IMPEOANCE

- - -1-1-_-_

L._-_-_-~-<A-CC---_----J --I1---+--+===+---VOL

Note CD WE mU$T be aT VIH un"l end (,)11CO

II

,uPD411

70

60

30

·50

·40

·20

·10

14

13

~ g ¹²

>

"

10

IODAV - Ta

I I I I

S++T

I I

t ^I

- ^r--

^{Yp 'OOAV}

r-

f--^f--CYCLE TIME .

TT "

^{jOO n,}

I I I I

25 50

f"

~

1'\ I'\.

~

"-

_">00 ('I

"'C

~

1'\

...

l\..

~ SPEC LIMIT: .2ml',2.4V .'-~

I I

3 VOH (V) VOO - Vas

- t--

75

I'...

-

ru~y

~

_~L

^-

6~~R:T~~~E~EG10N

t"

^{,7' 0<·)' SJ}

_"

J....,'" R

/

10C ~ ^{, /}

%

~ 7'"

,/~ -

./'

·3. ·4 ·5 ·6 ·7 ·8

Vas (V)

1.25

1.0

0.5

0.25

50

40

20

10

1000

100

]

"-

'"

'"

10

t--

'ODAV - tCY

l -

t:;; ^IMIN~MU1

CVfLE tiME l -I--

1\ I I I_

_t--

L?

teE'" CONST.

I~

I'.

I'--...

NORMALIZED CYCLE TIME IOl - VOL

V Iv

00

V V

"~ ' /

:;-

_~ ^,0

V

/

V.

^V

t--

r-

V

SPEC LIMIT: 3.2mA,O.4V t--

1/-

I

...

... ^{... ...} _N'y~

I

...

...

...

...

SPE~ LI~T ~m'

I

20 60

Power consumption; VDD x IDDAV + VBB x IBB . Typical power dissiption for each product is shown below.

mW (TYP.) CONDITIONS

/lPD411 450 Ta; 25° C, tcy = 470ns, tCE; 300ns /lPD411-1 450 Ta = 25° C, tcy = 470ns, tCE = 260ns /lPD411-2 450 Ta = 25° C, tcy = 400ns, tCE = ^230ns /lPD411-3 550 Ta; 25° C, tcy = 380ns, tCE = 210ns /lPD411-4 660 Ta ; 25° C, tcy ; 320ns, tCE = 200ns See above curves for power dissipation versus cycle time.

TYPICAL OPERATING CHARACTERISTICS (Except 411-4)

POWER CONSUMPTION

CURRENT WAVEFORMS

PACKAGE OUTLINE J-IPD411 D

CE(V)

ICE (mA)

IDD (mAl

188 (rnA)

JLPD411

100 200 300 400 500

] I \

~I ^{11 v 7\}

120

80

II

40

40

20 r---~.---~---

-20 f---\---,I---""~---+__+--- -40 ' - -______ .>0.<. _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ - - ' ' ' -_ _ _

M

(Plastic)

ITEM MILLIMETERS INCHES

A 27.43 MAX 1.079 MAX

B 1.27 MAX 0.05 MAX

C 2.54 ± 0.1 0.10

D 0.42 ± 0.1 0.016

E 25.4 ± 0.3 1.0

F 1.5 ± 0.2 0.059

G 3.5 ± 0.3 0.138

H 3.7 ± 0.3 0.145

I 4.2 MAX 0.165 MAX

J 5.08 MAX 0.200 MAX

K 10.16 ± 0.15 0.400

L 9.1 ± 0.2 0.358

M 0.25 ± 0.05 0.009

411DS-REV3-12-8()'CAT

17

NOTES

NEe

NEe Microcomputers, Inc. ^Jl.PD411A Jl.PD411A-1 Jl.PD411A-2

4096 BIT DYNAMIC RAMS

DESCR IPTION The ,uPD411A Famify consists of four 4096 words by 1 bit dynamic N-channel MOS RAMs. They are designed for memory applications where very low cost and large bit storage are important design objectives. The ,uPD411 A Family is designed using dynamic circuitry which reduces the standby power dissipation.

Reading information from the memory is non·destructive. Refreshing is easily

II

accomplished by performing one read cycle on each of the 64 row addresses. Each row address must be refreshed every two milliseconds. The memory is refreshed whether Chip Select is a logic high or a logic low.

FEATURES • Low Standby Power

• 4096 words x 1 bit Organization

• A single low·capacitance high level clock input with solid ±1 volt margins.

• Inactive Power 0.7 mW (Typ.)

• Power Supply +12, +5, -5V

• Easy System Interface

• TTL Compatible (Except CE)

• Address Registers on the Chip

• Simple Memory Expansion by Chip Select

• Three State Output and TTL Compatible

• 22 pin Plastic Dual·in-Line Package

• Replacement for INTEL's 21078, TI's 4060 and Equivalent Devices.

• 3 Performance Ranges:

ACCESS TIME RfW CYCLE RMWCYCLE REFRESH TIME

~PD411A 300 ns 470 ns 65Uns 2m.

~PD411A·l 250 ns 430 ns 600ns 2m.

~PD411A·2 200 ns 400 ns 520 ns ^2m,

PIN CONFIGURATION ^{VBB Vss}

Ag AS

PIN NAMES AO' All Address Inputs

A10 A7

AO-AS Refresh Addresses

CE ChiD Enable

A11 AS ^CS Chip Select

Cs VOD

DIN CE

DIN Data Inpl..It DOUT Data O"tput

WE Write Enable

DOUT NC ^VOD Power (+12V)

AO A5 ^Vce

Powe, (+5V)

VSS Ground

"1 A4 ^Vas (Pow ... -5V)

A2 .4.3 INC No Connection

VCC WE

Rev/1

,..,PD411A

CE Chip Enable.

A single extemal clock input is required. All read, write, refresh and read-modify-write operations take place when chip enable input is high. When the chip enable is low, the memory isin the low power standby mode. No read/write operations can take place because the chip is automatically precharging.

CS Chip Select

The chip select terminal affects the data in, data out and read/write inputs. The data input and data output terminals are enabled when chip select is low. The chip select input must be low on or before the rising edge of the chip enable and can be driven from standard TTL circuits. A register for the chip select input is provided on the chip to reduce overhead and simplify system design.

WE Write Enable

The read or write mode is selected through the write enable input. A logic high on the WE input selects the read mode and a logic low selects the write mode. The

WE

terminal can be driven from standard TTL circuits. The data input is disabled when the read mode is selected.

AO-A11 Addresses

All addresses must be stable on or before the rising edge of the chip enable pulse. All address inputs can be driven from standard TTL circuits. Address registers are pro- vided on the chip to repuce overhead and simplify system design.

DIN Data Input

Data is written during a write or read-modify·write cycle while the chip enable is high.

The data in terminal can be driven from standard TT L circuits. There is no register on the data in terminal.

DOUT Data Output

The three state output buffer provides direct TTL compatibility with a fan-out of two TTL gates. The output is in the high-impedance (floating) state when the chip enable is low or when the Chip Select input is high. Data output is inverted from data in.

Refresh

Refresh must be performed every two milliseconds by cycling through the 64 addresses of the lower-order-address inputs AO through AS or by addressing every row within any 2-millisecond period. Addressing any row refreshes all 64 bits in that row ..

The chip does not need to be selected during the refresh. If the chip is refreshed during a write mode, the chip select must be high.

AO o--_~

AI

A20--_--I Aa 0--_'"

A40--_--I

AS 0--_"'1

CE

a: w

l>- I>-

::>

'"

TIMING.

GENERATOR

CELL MATRIX 64 x 64

- - - - 0 Voo

---<I V CC

---oVss ---OVss

110

...

^-~cs

t--~ WE

FUNCTIONAL DESCRIPTION

BLOCK DIAGRAM

ABSOLUTE MAXIMUM RATINGS*

fLPD411A

Operating Temperature . . . oOe to +70oe Storage Temperature . . . -55°C to +12Soe Output Voltage

CD ...

+20 to -0.3 Volts All Input Voltages

CD ...

+20 to -0.3 Volts Supply Voltage VDD

CD ...

+20 to -0.3 Volts Supply Voltage Vee

CD ...

+20 to -0.3 Volts Supply Voltage VsS

CD . . . ...

+20 to -0.3 Volts Power Dissipation . . . .. 1.0W

Note:

CD

Relative to Vee.

COMMENT: Stress above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

*Ta = 25°C

DC CHARACTER ISTICS Ta = o°c to 70°C, Voo = +12V ± 10%, VCC = +5V ± 10%, Vee = -5V ± 10%, VSS = OV LIMITS

PARAMETER SYMBOL MIN. TYP. (]) MAX. UNIT TEST CONDITIONS

Input Load Current III 0.Q1 10 IlA VIN = VIL MIN to VIH MAX

CE Input Load Current ILC 0.01 10 pA VIN = VILC MIN to VIHC MAX Output Leakage Current

ILO 0.01 ±10 IlA CE = VILC or CS = VIH

for High Impedance State Vo = OV to 5.25V

VOO Supply Current

100 OFF 50 200 pA CE = -1.0V to 0.6V

during CE off VOO Supply Current

IOOON 35 50 mA CE = VIHC, T a = 25°C

during CE on

Average VOO Current Ta =25 C

IlP0411A IOOAV 38 55 mA Cycle Time = 470 ns

IlPD411A-l IOOAV 38 55 mA Cycle Time = 430 ns

IlP0411A-2 IOOAV 38 55 mA Cycle Time = 400 ns

VSS Supply Current (2) ISS 5 100 pA

VCC Supply Current

ICC OFF 0.01 10 pA CE = VILC or 1% = VIH during CE off @

Input Low Voltage VIL -1.0 0.6 V

Input High Voltage VIH 2.4 VCC + 1 V

CE Input Low Voltage VILC -1.0 0.6 V

CE Input High Voltage VIHC VOO- 1 VOO VOO + 1 V

Output Low Voltage VOL 0 0.40 V IOL =3.2mA

Output High Voltage VOH 2.4 VCC V IOH =-2.0 mA

Notes: (]) Typical values are for T a = 25°C and nl'minal power supply voltages.

(2) The ISS current is the sum of all leakage currents.

@ During CE on VCC supply current is dependent on output loading.

CAPACITANCE Ta = o°c to 70°C. VOO = 12V ± 10%. VCC =+5V ± 10%. VBB = -5V ± 10%. Vss = OV LIMITS ....

TEST PARAMETER SYMBOL MIN. TYP. MAX. UNIT CONDITIONS

Address Capacitance CAD 6 pF VIN = Vss

es

Capacitance CCS 6 pF VIN =VSS

DIN Capacitance CIN 6 pF VIN = Vss

DOUT CapaCitance COUT 7 pF VOUT= VSS

WE Capacitance CWE 7 pF VIN = Vss

CE Capacitance CCE1. 27 pF VIN ~ Vss

CCE2 22 pF VIN -VOO

II

JL ^PD411A

AC CHARACTERISTICS

READ CYCLE

T a'" aOc to 70^oe, VOO '" 12V ± 10%, Vee = 5V ± 10%, VSB '" - 5V ± 10010, VSS '" OV, unless otherwise noted.

LIMITS

~PD411A ~PD411A-l ~PD411A-2

PARAMETER SYMBOL MIN MAX MIN MAX MIN MAX UNIT TEST CONDITIONS

Time Between Refresh tREF 2 2 2 ms

·"Address to CE Set Up Time tAC 0 0 0 ns

Address Hold Time tAH 150 150 150 ns

CE Off Time tcc 130 130 130 ns

tT'" tr '" tf = 20 ns

CE Transition Time tT 0 40 0 40 0 40 ns

CL = 50 pF CE Off to Output High

tCF 0 130 0 130 0 130 ns Load'" lTTL Gate

Impedance State

Cycle Time 'CY 470 ' 430 400 ns Vref'" 2.0 or .0.8 Volts

CE on Time 'CE 300 3000 260 3000 230 3000 ns

CE Output Delay teo 280 230 180 ns

Access Time tACC 300 250 200 ns

CE to WE IWL 40 40 40 ns

WE to CE on IWC 0 0 0 ns

WRITE CYCLE

T a'" o°C to looe Voo '" 12V + 10% Vee'" 5V + -10% vee'" - 5V + ^- 10% Vss '" OV unless otherwise noted LIMITS

~PD411A ~D411A-l ~PD411A-2

PARAMETER SYMBOL MIN MAX MIN MAX MIN MAX UNIT TEST CONDITIOIIIS

Cvcle Time 'CY 470 430 400 ns

Time Between Refresh tREF 2 2 2 ms

Address to CE Set Up Time tAC 0 0 0 ns

Address Hold Time tAH 150 150 150 ns

CE Off Time tcc 130 130 130 ns

-CE Transition Time r-r ^{0 40 0 40 0 40 ns} tT '" tr '" tf '" 20 ns CE Off to Output High

tCF 0 130 0 130 0 130 ns CL = 50 pF

Impedance State

CE on Time 300 3000 260 3000 230 3000 Load", ITTL Gate

'CE ns

WE to CE off 'W 180 180 150 ns Vref:::; 2.0 or 0.8 Volts

CE ,oWE tcw 300 260 230 ns

DIN toWE Se-( U",. (1) _'OW 0 0 0 ns

DIN Hold Time tDH 40 40 40 ns

WE Pulse Width IWP 180 180 150 ns

Note:<D If WE is low before CE goes high then DIN must be valid when CE goes hig,.

READ·MODIFY·WRITE CYCLE

T a:::; oOe to 1O^oe. VDD '" 1,2V ± 10%, Vce '" 5V ± 10%, VSS = --5V ± 10%, VSS ::: OV, unless otherWise noted.

LIMITS

~PD411A ~PD411A-l pPD411A-2

PARAMETER SYMBOL MIN MAX MIN MAX MIN MAX UNIT TEST CONDITIONS Read-Modify-Write (RMW)

tRWC 650 600 520 ns

CydeTime

Time Between Ref(esh tREF 2 2 2 ms

Address to CE Set Up Time tAC 0 0 0 ns

Address H~d Time tAH 150 150 150 ns

CE OHTime tcc 130 130 130 ns

CE Transition Time r-r ^{0 40 0 40 0 40 ns}

CE Off to OutPUt High tT ::: tr '" tf '" 20 ns

Impedance State tCF 0 130 0 ' 130 0 130 ns CL = 50 pF

CE Width During RMW tCRW 480 3000 430 3000 350 3000 ns Load:::; lTTL Gate

'WrtoCE on 'WC 0 0 0 ns Vref'" 2.0 or 0.8 Volts

~toCEo" IW 180 180 150 ns

WE Pulse Width IWP 180 180 150 ns

DIN to WE Set Up tow 0 0 0 ns

TIMING WAVEFORMS

Cf

Cf

CE

AO- All AND CS

DIN

fLPD411A

READ AND REFRESH CYCLE

CD

WRITE CYCLE

---l-~~=~':::=::::jct=;;;;;_=:J r-++~----,-::-+_-V,H

____ ~---,~~L---+_-~r_-~_+---V,H

---l---',"jc---+--.f '-....:::.=~+--

VIL

R EAD-MOD I FY -WR ITE CYC LE

---t---++---,.k-~---~~~.r_--+_-VIH ---r--++---r~---~~~~~~+_-VIL

L-______ ~~__'~---~--~~~~--VOL

~---tACC - - - _

Notes: CD For refresh cycle. row and column addresses must be stable tAC and remain stable for entire tAH period.

(2) VOO - 2V is the reference level for measuring timing of CEo (l) VSS + 2V is the reference level for measuring timing of CEo

® VIHMIN is the reference level for measuring timing of the addresses,

CS. WE and DIN.

@ VILMAX is the reference level for measuring timing of the addresses,

CS. WE and DIN.

@ VSS + 2.0'", is the reference level for measuring timing of DOUT·

(j) VSS + O.8'J is the reference level for measuring timing of DOUT·

<B> ~ must be at VIH until end of teO·