Z8® Family

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June 1988

Z8® Family

Design Handbook

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June 1988

Z8® Family

Design Handbook

INTRODUCTION

Zilog was founded in 1974, and within its first year brought to market the most popular and best selling microprocessor in the world, the Z80 8~bit

microprocessor.

With the unparalleled success of the Z80 CPU, the name Zilog became synonomous with quality, design integrity, and complete company support elements that remain integral to Zilog today.

Headquartered in Campbell, California, Zilog draws upon the services and skills of the most talented high technology minds in the industry. Zilog's Nampa, Idaho manufacturing facility, and assembly plant in the Philippines are the best of their size today. They provide Zilog customers with a total solution, from engineering, to production, to worldwide on-time delivery of the growing family of Zilog microprocessor and peripheral products.

Z8 Family Design Handbook Table of Contents

Z8 NMOS MCU Microcomputers

Z8600 Z8601111

Z8603/13 Z8671 Z8681 182 Z8691

MCU 2K 28-pin MCU 2K!4K

MCU Protopak 2K!4K

MCU with Basic/Debug Interpreter MCU ROMless

MCU ROMless

Z8 CMOS MCU Microcomputers

Z86C08

Z86COO/C10/C20 Z86C11/E11

Z86C21 IZ86E21 IC 12 Z86C91

MCU 2K 18-pin MCU 4K8K 28-pin MCU4K

MCU 8K!OTP (One lime Programmable MCU) MCU ROMless

Z8 Application Notes and Technical Articles

Memory Space and Register Organization App Note A Programmer's Guide to the Z8 MCU

Z8 Subroutine Ubrary A Comparison of MCU Units Z86xx Interrupt Request Registers Z8 Family Framing

Z8 MCU Technical Manual Super8 MCU Microcomputer

Z8800/01 Z8820 Z8822

MCU ROM less MCU8K

MCU 8K Protopak

Super8 Application Notes and Technical Articles

Getting Started with the Zilog SuperS

Polled Asynchronous Serial Operation with the SuperS Using the Super8 Interrupt Driven Communications Using the SuperS Serial Port with DMA

Generating Sine Waves with Super8 Generating DTMF Tones with Super8

A Simple Serial Parallel Converter Using the Super8

Page

13 30 50 71

89 105 117 134 153

171 173 198 248 261 262

264

403 403 403

434 438 443 448 453 458 462

SuperS Technical Manual Military Electrical Specifications

Z8611 Z8~81

MCU4K MCU ROMless

Packaging Information Ordering Information

470

609

632

645 651

FEATURES

[J Complete microcomputer, 2K bytes of ROM, 128 bytes of RAM, and 221/0 lines.

o

144-byte register file, including 124 general-purpose registers, four I/O port registers, and 14 status and control registers.

o Vectored, priority interrupts for I/O and counter/timers.

o Two programmable 8-bit counter/timers, each with a 6-bit programmable prescaler.

GENERAL

DESC~IPTION

The Z8600 microcomputer introduces a new level of sophistication to single-chip architecture. Compared to earlier single-chip microcomputers, the Z8600 offers:

o faster execution

o more efficient use of memory

o more sophisticated interrupt, input/output, and bit manipulation capabilities

TIMING (~ RESET +5V

...-

AND

os -I

CONTROL ^XTALl

~~.{~

^{po, po,} po. ^{po. po, Z8S00} _MCU ^{XTAL2 CLOCr( PORT 3} po.

~mm

^{P2, P2, P2, P2. Pl. Pl.}

^...

^PORTf

P2. Pl,

-

-<H> GND P17

...

Figure 1. Pin Functions

~$$@@~~®

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June 1937

o Register Pointer so that short, fast instructions can access anyone of the nine working register groups.

o

On-chip oscillator that accepts crystal or external clade drive.

o

8MHz

o Single + 5 power supply-all pins TTL-compatible.

o Average instruction execution time of 2.2 !!S.

minimum 1.5 !!S.

o easier system expansion

Under

progr~m

control, the MCU can be tailored to the needs of its user. It can be configured as a stand-alone microcomputer with 2K bytes of internal ROM. In all configurations, a large number of pins remain available for 110.

The MCU is offered in a28 pin Dual-In-Line-Package (DIP) (Figures 1 and 2).

+5V P3,

XTAL2 P3,

XTALl P2.

RESET P2.

os

^P2,

P3. P2,

GND P2,

po. P17

PO, Pl,

PO, Pl.

PO, Pl.

PO • Pl,

PO. Pl,

Pl. Pl,

Figure 2. Pin Assignments

PIN DESCRIPTIONS

OS. Data Strobe (output. active Low). Data Strobe is activated once for each memory transfer.

POo·POs • P10·P17. P21·P2S. P310 P3S. P36' liD Port lines (bidirectional. TTL-compatible). These 22 110 lines are grouped in four ports that can be configured under program control for 1/0.

ARCHITECTURE

The MCU's architecture is characterized by a flexible I/O scheme, an efficient register and address space structure.

and a number of ancillary features that are helpful in many applications. (Figure 3).

Microcomputer applications demand powerful I/O capabilities. The MCU fulfills this with 22 pins dedicated to input and output. These lines are grouped in four ports and are configurable under software control to provide timing, status signals, and parallel I/O.

110 (BIT PROGRAMMABLE)

RESET. Reset (input. active Low). RESET initializes the MCU. When RESET is deactivated. program execution begins from internal program location OOOCH.

XTAL 1. XTAL2. Crystal 1, Crystal 2 (time-base input and output). These pins connect a parallel-resonant 8 MHz crystal to the on-chip clock oscillator and buffer.

Two basic internal address spaces are available to support this wide range of configurations: program memory and the register file. The 144-byte random-access register file is composed of 124 general-purpose registers. four I/O port registers, and 14 control and status registers.

To unburden the program from coping with real-time problems such as counting/timing, two counter/timers with a large number of user-selectable modes are offered on-chip.

I/O 110

(BYTE PROGRAMMABLE)

Figure 3. Functional Block Diagram

ADDRESS SPACES

Program Memory. The 16-bit program counter addresses 2K bytes of program memory space as shown in Figure 4.

The first 12 bytes of program memory are reserved for the interrupt vectors. These locations contain three 16-bit vectors that correspond to the three available interrupts.

Register File. The 144-byte register file includes four I/O port registers (Ro-R3), 124 general-purpose registers (R4-R127) and 14 control and status'registers (R241-R255)' These registers are assigned the address locations shown in Figure 5.

2047

Instructions can access registers directly or indirectly with an 8-bit address field. The MCU also allows short 4-bit register addressing using the Register Pointer (one of the control registers). In the 4-bit mode, the register file is divided into nine working-register groups, each occupying 16 contiguous locations (Figure 6). The Register Pointer addresses the starting location of the active working-register group.

Stacks. An 8-bit Stack Pointer (R255) is used for the internal stack that resides within the 124 general-purpose registers (R4-R127)' .

ON·CHIP

LOCATION 255 254 253 252 251 250 249 248 247 246 245 244 243 242 241

127

·1

o

LOCATION OF FIRST BYTE OF INSTRUCTION EXECUTED AFTER RESET

INTERRUPT VECTOR (LOWEll BYTE) INTERRUPT VECTOR (UPPER BYTE)

STACK POINTER (BITS 7-0) RESERVED REGISTER POINTER PROGRAM CONTROL FLAGS INTERRUPT MASK REGISTER INTERRUPT REQUEST REGISTER INTERRUPT PRIORITY REGISTER

PORTS 0-1 MODE PORT 3 MODE PORT 2 MODE TO PRESCALER TIMER/COUNTER 0

T1 PRES CALER TIMER/COUNTER 1

TIMER MODE

NOT IMPLEMENTED

GENERAL·PURPOSE REGISTERS

PORT 3 PORT 2 PORT 1 PORTO

Figure 5. Register File

ROM

~

~---

11 IRQ5

10 IRQ5

9 IRQ4

8 IRQ4

7 RESERVED

8 RESERVED

5 "'.

IRQ2

4~ IRQ2·

3 RESERVED

2 RESERVED

1 RESERVED

0 RESERVED

Figure 4. Program Memory Map

IDENTIFIERS SPL

RP FLAGS IMR IRQ IPR POIM P3M P2M PREO TO PREI Tl TMR

P3 P2 PI PO

- ... { .... ...;,..;...;...;...L.._;...;..;.... .... 253

THE UPPER NIBBLE OF THE REGISTER FILE ADDRESS PROVIDED BY THE REGISTER POINTER SPECIFIES THE ACTIVE WORKING-REGISTER GROUP.

--.

--.

--.

-,.

--.

--.

- ...

1 27

SPECIFIED WORKING·

REGISTER GROUP -!--

THE LOWER NIBBLE OF THE REGISTER FILE ADDRESS PROVIDED BY THE INSTRUCTION POINTS TO THE SPECIFIED REGISTER.

15 r - - - " i / O P O R T s - - - 3

Figure 6. Register Pointer

3

COUNTER/TIMERS

The MCU contains two a-bit programmable counter/timers (To and T1), each driven by its own 6-bit programmable prescaler. The T1 presca,ler can be driven by internal or external clock sources; however, the To prescaler is driven by the internal clock only.

The 6-bit prescalers can divide the input frequency of the clock source by any number from 1 to 64. Each prescaler drives its counter, which decrements the value (1 to 256) that has been loaded into the counter. When the counter reaches the end of count, a timer interrupt request-IR04 (To) or IR05 (T1)-is generated.

The counters can be started, stopped, restarted to continue, or restarted from the'initial value. The counters can also be programmed to stop upon reaching zero (single-pass

I/O PORTS

The MCU has 22 lines dedicated to input and output grouped in four ports, Under software control, the ports can be programmed to provide address outputs, timing, status signals, and parallel I/O. All ports have active pull-ups and pull-downs compatible with TIL loads.

Port 0 can be programmed as an 110 port.

Port 1 can be programmed as a byte 110 port.

INTERRUPTS

The MCU allows three different interrupts from three sources, the Port 3 line P31 and the two counter/timers.

These interrupts are both. maskable and prioritized. The Interrupt Mask register globally or individually enables or disables the three interrupt requests. When more than one interrupt is pending, priorities are resolved by a programmable priority encoder that is controlled by the Interrupt Priority register.

All interrupts are vectored. When an interrupt request is granted, an interrupt machine cycle is entered. This disables

CLOCK

The on-chip oscillator has a high-gain parallel-resonant amplifier for connection to· a crystal or to any suitable external clock source (XTAL 1

=

Input, XTAL2

=

Output).

Crystal source is connected across XTAL 1 and XTAL2 using the recommended capacitors (C1 ~ 15 pf) from each pin to ground. The specifications are as follows:

mode) or to automatically reload the initial value and continue counting (modulo-n continuous mode). The counters, but not the prescalers, can be read any time without disturbing their value or count mode.

The clock source for T 1 is user-definable and can be the internal microprocessor clock (4 MHz maximum) divided by four, or an external signal input via Port 3, The Timer Mode register configures the external timer input as an external clock (1 MHz maximum), a' trigger input that can be retriggerable or non-retriggerable, or as a gate input for the internal clock, The counter/timers can be programmably cascaded by connecting the To output to the input of T1.

Port 3 line P36 also serves as a timer output (TOUT) through which To, T 1 or the internal clock can be output.

Port 2 can be programmed independently as input or output and is always available for I/O operations. In addition, Port 2 can be configured to provide open'drain outputs.

Port 3 can be configured as 110 or control lines. P31 is a general purpose input or can be used for an external interrupt request signal (IR02)' P35 and P36 are general purpose outputs. P36 is also used for timer input (TIN) and output (TOUT) signals.

all subsequent interrupts, saves the Program Counter and status flags, and branches to the program memory vector locations reserved for that interrupt. This memory location and the next byte contain the 16-bit address of the interrupt service routine for that particular interrupt request.

Polled interrupt systems are also supported. To accom- modate a polled structure, any or all of the interrupt inputs can be masked and the Interrupt Request register polled to determine which of the interrupt requests needs service.

m AT cut, parallel resonant

III Fundamental type, a MHz maximum III Series resistance, Rs ~ 10011

INSTRUCTION seT NOTATION

Addressing Modes. The fol/owing notation is used to describe the addressing modes and instruction operations as shown in the instruction summary.

IRR Indirect register pair or indirect working-register pair address

Irr Indirect working-register pair only )( Indexed address

DA Direct address RA Relative address

1M Immediate

R Register or working-register address r Working-register address only

IR Indirect-register or indirect working-register address

Ir Indirect working-register address only RR Register pair or working register pair address Symbols. The fol/owing symbols are used in describing the instruction set.

dst src

cc

@

Destination location or contents Source location or contents Condition code (see list) I ndirect address prefix SP

PC FLAGS

RP

IMR

Stack pointer (control registers 254-255) Program counter

Flag register (control register 252) Register pointer (control register 253) Interrupt mask register (control register 251) CONDITION CODES

Value Mnemonic

1000 Always true

0111 C Carry

1111 NC No carry

0110 Z Zero

1110 NZ Not zero

1101 PL Plus

0101 MI Minus

0100 OV Overflow

1100 NOV No overflow

0110 EQ Equal

1110 NE Not equal

Assignment of a value is indicated by the symbol "-': For example,

dst - dst

+

src

indicates that the source data is added to the destination data and the result is stored in the destination location. The notation "addr(n)" is used to refer to bit "n" of a given location. For example,

dst (7) refers to bit 7 of the destination operand.

Flags. Control Register R252 contains the fol/owing six flags:

C Carry flag

Z Zero flag

S Sign flag

V Overflow flag D Decimal-adjust flag H Half-carry flag Affected flags are indicated by:

o

Cleared to zero

1 Setto one

*

Set or cleared according to operation Unaffected

}( Undefined

Meaning Flags Set

C = 1 C=O Z = 1 Z=O S=O S = 1 V = 1 V=O Z = 1 Z=O

1001 GE Greater than or equal (S XOR V) = 0

0001 LT Less than (SXOR V) = 1

1010 GT Greater than [Z OR (SXOR V)] = 0

0010 LE Less than or equal [Z OR (S XOR V)] = 1

1111 UGE Unsigned greater than or equal C=O

0111 ULT Unsigned less than C=1

1011 UGT Unsigned greater than (C = OANDZ = 0) = 1

0011 ULE Unsigned less than or equal (CORZ) = 1

0000 Never true

5

INSTRUCTION FORMATS

OPC MODE

dstlsrc OR 11 1 1 01 dsllsre 1

OPC

lOR 11 1 101

dst dst

OPC VALUE

OPC MODE dst sre

dst/src OPC

src/dst OR 11 1 1 01 sre

dsl

I

^OPC

VALUE

I

^{dsUCC R~ OPC}

OPC

dst OPC

CCF, DI, EI, IRET, NOP, RCF, RET, SCF INCr

One-Byte Instructions

CLR, CPL, DA, DEC, DECW,INC,INCW, POP, PUSH, RL, RLC, RR, RRC, SRA, SWAP

OPC MODE ADC,ADD, AND, CP,

sre OR 1 1 1 0 sre LD, OR, SBC, SUB, dst OR 1 1 1 0 TCM, TM, XOR

dst JP, CALL (Indirect)

OPC MODE ADC, ADD, AND, cp,

SRP

dst ORj11101 dst LD, OR, SBC, SUB,

VALUE TCM, TM, XOR

MODE OPC LD

ADC, ADD, AND, CP, OR, SBC, SUB,

src OR r:-:....:...+..;::..:'--l

dst OR L!....:'--'-"-L.~'--I TeM, TM, XOR

LD LD, LDC, LDCI

LD ee OPC JP

DAu DAL LD

CALL DJNZ, JR

Two-Byte Instructions Three-Byte Instructions

Figure 7. Instruction Formats INSTRUCTION SUMMARY

AddrMode Opcode Flags Affected AddrMode Opcode Flags Affected

Instruction Byte Instruction Byte

and Operation ' dst src (Hex) C ZS V 0 H and Operation dst src (Hex) CZSVDH ADCdst,src (Note 1) 10 * * * * 0 * CP dst,src (Note 1) AD * * * * - -

dst - dst + src + C dst - src

ADDdst,src (Note 1) 00 * * * *

o

* DAdst R 40 * *.*

X--

dst - dst + src dst-OAdst IR 41

AND dst,src (Note 1) 50 - * * 0 - - DECdst R 00 - * * * - -

dst - dstANOsrc dst-dst - 1 IR 01

CALLdst OA 06

- - - -

^{DECWdst RR 80} - * * * - -

SP-SP - 2 IRR 04 dst - dst - 1 IR 81

@SP - PC; PC - dst

01

CCF EF * - - - ; - - - IMR(7)-0 8F - - - -

C-NOTC

DJNZr,dst RA rA - - - -

CLRdst R BO - - - r - r - 1 r = 0 - F

dst-O IR B1 if r;lo 0

COMdst R 60 - * * 0 - - PC-PC + dst

dst .... NOT dst IR 61 Range: +127, -128

INSTRUCTION SUMMARY (Continued)

Instruction and Operation

Addr Mode Opcode Flags Affected Byte

dst src (Hex) C Z S V 0 H EI

IMR(7)+-1 INCdst dst+-dst + 1

INCWdst dst +-dst + 1

R IR RR

IR

9F

rE - 1: 1: 1: - - r=O-F

20 21

AD - '" 1: 1: - - A1

IRET SF

'* '" '* '*

1: '"

FLAGS +- @SP; SP +- SP + 1 PC +-@SP; SP +- SP + 2; IMR (7) +-1 JPee,dst

ifee is true PC +- dst JRee,dst if ee is true,

PC-PC + dst Range: + 127, -128 LO dst,sre

dst-sre

LOCdst,sre dst ""'sre LOCI dst,sre dst-sre

r+-r + 1; rr+-rr + 1 NOP

ORdst,sre dst +- dst OR sre

DA IRR RA

r R r X r Ir R R R IR IR r Irr Ir Irr

1m R X r Ir r R IR 1M 1M R Irr

Irr' Ir

(Note 1)

POPdst R

dst +- @SP; IR

SP .... SP + 1

PUSHsre R

SP +- SP - 1; @SP +- sre IR RCF

C+-O RET

PC +- @SP; SP +- SP + 2

eD e:'O-F

30 eS e=O-F

rC r8 r9 r = 0 - F

C7 D7 E3 F3 E4 E5 E6 E7 F5 C2 D2 C3 D3

FF 40

50

70 71 CF

AF

0 - - - - -

Instruction and Operation

Addr Mode Opcode Flags Affected Byte

dst src (Hex) C Z S V 0 H

RLdst r==I R

0~IR RLC dst

LE:J+E:iIJ

^R

c , 0 IR

RR dst

LEI LE:3J

^R

C , 0 IR

RRC dst

If:ri=!i:3J

^R

C , 0 IR

SBC dst,sre (Note 1) dst +- dst +- sre +- C

90 91 10 11 EO

E1 CO C1 3D

'" '" '" '"

SCF C+-1

DF 1 - - - - -

SRA dst

Lci]

C

@J

, 0 IR ^R SRPsre

RP +-sre SUBdst,sre dst +- dst +- sre

1m (Note 1)

SWAPdst _I,

S

_{" oliR} ^R

TCM dst,sre (NOT dst) AND sre TM dst,sre dstANDsre XORdst,sre dst +- dst XOR sre

(Note 1)

(Note 1)

(Note 1) DO D1 31

20 FO F1 60 70 SO

'It '" '" 0

NOTE 1: These instructions have an identical set of addressing modes, which are encoded for brevity. The first opcode nibble is found in the instruction set table above. The second nibble is expressed symbolically by a 0 in this table, and its value is found in the following table to the right of the applicable addressing mode pair.

For example, the opcode of an ADC instruction using the addressing modes r (destination) and Ir (source) is 13.

AddrMode

dst src

R R R IR

Ir R IR 1M 1M

Lower Opcode Nibble

REGISTERS

(Continued)

R248 P01M PORT 0 AND 1 MODE REGISTER

(F8H; Write Only)

PO'.PD'MODE~· ~-r

POo.PO, MODE OUTPUT"" 00

--.J L

⁰⁰ = OUTPUT

INPUT = 01 01 = INPUT

RESERVED S~A:~N;i~~C:{ON

P10·P17MODE 00 = BYTE OUTPUT 01 = BYTe INPUT 11 = HIGH·IMPEDANCE os

R2491PR

INTERRUPT PRIORITY REGISTER (F9H; Write Only) I~I~I~I~I~I~I~I~I

"~"'. ~ I I III".

RESERVED TERRUPT GROUP PRIORITY = 000 452 = 001

DON'T CARE 524 :: 010

542 = 011 245 = 100

DON'TeARE 425:: 101

254=110

DON'T CARE RESERVED = 111

R250lRQ

INTERRUPT REQUEST REGISTER (FAH; Read/Write) I~I~I~I~I~I~I~I~I

RESERVED

=r c=

^{IRQ2 =} P3,INPUT (02 = IROS) IRO'4 = To

lAOS == T,

R2511MR INTERRUPT MASK REGISTER

(FBH; Read/Write) I~I~I~I~I~I~I~I~I

II ^c=

1 ENABLES IROo-IROs

(00 = IROO) ' - - - R E S E R V E D ' - - - 1 ENABLES INTERRUPTS

REGISTER POINTER

Figure 8. Control Registers (Continued)

R252 FLAGS FLAG REGISTER (FCH; Read/Write)

E~l§llli

LUSERFLAGF1 ^.

LUSER FLAG F2 HALF CARRY FLAG DECIMAL ADJUST FLAG OVERFLOW FLAG SIGN FLAG ZERO FLAG CARRY flAG

R253 RP REGISTER POINTER

(FDH; Read/Write)

R255SPL STACK POINTER

(FFH; Read/Write) I~I~I~I~I~I~I~I~I

~I

^____

~~~~~s~~~~:~R

^LOWER

OPCODEMAP

Lower Nibble (Hex)

3 4 7 8 9 A B C o E F

6.5 6.5 6.5 6,5 10,5 10.5 10,5 10.5 6,5 6,5 '2/10,5 12/10.0 6,5 12/10.0 6,5

o DEC DEC ADD ADD ADD ADD ADD ADD LD LD DJNZ JR LD JP INC

R, IR, (1"2 '1. lr2 R2· R, IR2,R, R"IM IR"IM rl,R2 r2. Rl r,.RA cc.RA r"IM ccDA rl

6,5 6,5 6,5 6,5 10,5 10,5 10,5 10,5 -

RLC RLC ADC ADC ADC ADC ADC ADC R, IR, '1,(2 '1,lr2 R2,R, IR2,R, R"IM IR"IM

-

6,5 6,5 6,5 6,5 10,5 10,5 10,5 10,5

2 INC INC SUB SUB SUB SUB SUB SUB

R, IR, _{'1,(2 '1,}lr2 R2,R, IR2,R, R"IM IR"IM

8,0 6,1 6,5 6,5 10,5 10,5 10.5 10,5 -

JP SRP SBC SBC SBC SBC SBC SBC

IRR, 1M _{'1,r2 '1, lt2} R2. R, IR2,R, R"IM IR"IM

-

8,5 8,5 6,5 6,5 10,5 10,5 10,5 10,5

4 DA DA OR OR OR OR OR OR

R, IR, '1,(2 '1, lr2 R2,R, IR2,Rl R"IM IR1,IM

~

10,5 10,5 6,5 6,5 10,5 10,5 10,5 10,5

5 POP POP AND AND AND AND AND AND

R, IR, '1,'2 '1, lr2 R2,R, IR2,R, R"IM IR"IM

6,5 6,5 6,5 6,5 10,5 10,5 10,5 10,5 -

6 COM COM TCM TCM TCM TCM TCM TCM

R, IR, '1,(2 '1, lr2 R2,Rl IR2,R, R"IM IR1,IM

-

10/12,1 12/14,1 6,5 6,5 10,5 10,5 10,5 10,5

PUSH PUSH TM TM TM TM TM TM

i e

7

R2 IR2 '1,'2 '1, lr2 R2,R, IR2,R, R"IM IR"IM

"

:;;

10,5 10,5

---e:1

.c Z

DECW DECW DI

RR, IRI t 8

c. c.

:::> -

6,5 6,5 6.1

9 RL RL EI

Rl IR,

-

10,5 10,5 6,5 6,5 10,5 10,5 10,5 10,5 14.0

A INCW INCW CP CP CP CP CP CP RET

RR, IR, _'1,(2 '1. lr2 R2,Rl IR2,R, R"IM IR"IN!

-

6,5 6,5 6,5 6,5 10,5 10,5 10,5 10,5 16.0

B CLR CLR XOR XOR XOR XOR XOR XOR IRET

R, IRI '1,{2 '1, lr2 R2,Rl IR2,Rl R"IM IR"IM

6,5 6,5 12,0 18,0 10,5

r----

_6,5

C RRC RRC LDC LOCI LD RCF

R, IR, _{'1, lrr2} Ir1,lrr2 rj,x,R2

I - - -

6,5 6,5 12,0 18,0 20,0 20,0 10,5 6.5

0 SRA SRA LDC LOCI CALL' CALL LD SCF

R, IR, _{'2, lrr 1} Ir2.lrr1 IRRI DA '2,x,Rl

6,5 6,5 6,5 10,5 10,5 10,5 10,5 I - - -

6.5

E RR RR LD LD LD LD LD CCF

R, IR, rl, IR2 R2,Rl IR2,R, R"IM IR"IM

8.5 I - - -

8,5 6,5 10,5 6.0

F SWAP SWAP LD LD NOP

R, IRI Irl,r2 R2,IR,

'-... - - - -... v ....

----J'-... ----...

^{v ....}

----J'-... ---...

^{v ...} -..;....~--... #~~

2

EXECUTION CYCLES

FIRST OPERAND

LOWER OPCODE

NllLE

*2-byte instruction; fetch cycle appears as a 3-byte instruction

PIPELINE CYCLES

MNEMONIC

SECOND OPERAND

Bytes per Instruction

2 3

Legend:

R = 8-bi' address r = 4-bit address Rt or'1 = Dst address R2 or'2 = Src address Sequence:

Opcode, First Operand, Second Operand NOTE: The blank areas are not defined.

9

REGISTERS

R241 TMR TIMER MODE REGISTER

(F1 H; Read/Write)

To", MODES

j ^US~o

= NO FUNCTION

NOT USED = 00

-.J

^{1 = LOAD To}

. ~o g~~

:

~~ ^{0 =} DISABLE To COUNT INTERNAL CLocK OUT = 11 1 = ENABLE To COUNT

T MODES 0 = NO FUNCTION

EXTERNAL CLOCK IN~OT = 00 1 = LOAD Tl

GATE INPUT", 01 0 = DISABLE T, COUNT

TRIGGER INPUT", 10 1 = ENABLE 11 COUNT

(NON·RETRIGGERABLE) TRIGGER INPUT = 11 (RETRIGGERABlE)

R242 T1

COUNTER TIMER 1 REGISTER (F2H; Read/Write)

R243 PRE1 PRESCALER 1 REGISTER

(F3H; Write Only)

I

^D,

I

D,I D, I D.I D, I D, I D, I D,

I

~L ^caUNTMaDE

^{o =} T\ SINGLE·PASS 1 =,11 MODUlO·N CLOCK SOURCE

1 '" Tl INTERNAL

.

0 '" T 1 EXTERNAL TIMING INPUT (TIN) MODE

PRESCALER MODULO (RANGE: 1-64 DECIMAL 01-00 HEX)

R244 TO

COUNTER/TIMER 0 REGISTER (F4H; Read/Write)

Tn INITIAL VALUE (WHEN WRITTEN) ' - - - ( R A N G E : 1 256 DECIMAL 01 00 HEX) To CURRENT VALUE (WHEN READ)

R245 PREO PRESCALER 0 REGISTER

(F5H; Write Only)

~L ^caUNTMaDE

o '" To SINGLE·PASS 1 = To MODULO·N RESERVED

PRESCALER MODULO (RANGE: 1-64 DECIMAL 01-00 HEX)

R246P2M PORT 2 MODE REGISTER

(F6H; Write Only)

P21·P2S DEFINITION ' - - - 0 DEFINES BIT AS OUTPUT

1 DEFINES BIT AS INPUT

R247P3M PORT 3 MODE REGISTER

(F7H; Write Only)

~~~

opaRT2 PULL·UPsaPEN DRAIN

1 PORT 2 PULL·UPS ACTIVE RESERVED

RESERVED RESERVED

o P3l = INPUT (TIN) P36", OUTPUT (Tour>

RESERVED ' - - - RESERVED

Figure 8. Control Registers

AC CHARACTERISTICS Timing Table

Number Symbol

1 TpC

2 TrC,TIC

3 TwC

4 TwTinL 5 TwTinH 6 TpTin 7 TrTin,TfTin S TwlL 9 TwlH NarES:

Figure 9. Timing

Parameter Input Clock Period

Clock Input Rise and Fall Times Input Clock Width

Timer Input Low Width Timer Input High Width Timer Input Period

Timer Input Rise and Fall Times Interrupt Request Input Low Time Interrupt Request Input High Time 1. Clock timing references use 3.BVfor a logic "1" and O.BV for a logic "0':

2. Timing references use 2.0Vfor a logic "1" and O.BV for a logic "a':

3. Interrupt request via Port 3 (P31-P33)'

• Units in nanoseconds (ns).

,Z8600 Min Max 125 1000 25 37 100 3TpC STpC

100 100 3TpC

Notes·

2 2 2 2 2,3 2.3

ABSOLUTE MAXIMUM RATINGS

Voltages on all pins with respect

toGND ... , ... -0.3Vto +7.0V Operating Ambient

Temperature ... See Ordering Information Storage Temperature ... - 65°C to + 150°C

STANDARD TEST CONDITIONS

I

The DC characteristics listed below apply for the following standard test conditions, unless otherwise noted. All voltages are referenced to GND. Positive current flows into the referenced pin.

Standard conditions are:

• +4.75V~Vee~ +5.25V

• GND = OV

DC CHARACTERISTICS

Symbol Parameter Min

VeH Clock Input High Voltage 3.8

Vel Clock Input Low Voltage -0.3

VIH Input High Voltage 2.0

Vil I nput Low Voltage -0.3

VRH Reset Input High Voltage 3.8

VRl Reset Input Low Voltage -0.3

VOH Output High Voltage 2.4

VOL Output Low Voltage

III Input Leakage -10

IOH Output Drive Current

IOl Output Leakage -10

IIR Reset Input Current

lee Vee Supply Current

Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only;

operation of the device at any condition above those indicated in the operational sections of these specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect . device reliability.

+5V

2.1K

Figure 10. Test Load 1

Max Unit Condition

Vee V Driven by External Clock Generator 0.8 V Driven by External Clock Generator

Vee V

0.8 V

Vee V

0.8 V

V IOH

=

-250,..A

0.4 V IOL

=

+2.0mA

10 ,..A OV ~ VIN ~ + 5.25V

1.5 rnA VOH

=

+2.4V 2.50 ~A VOH

=

+4.0V

10 ,..A OV ~ VIN ~ + 5.25V -50 ,..A Vee

=

+ 5. 25V, VRl

=

OV

150 mA

~ ~,~ ., < ~ II' '" 'l' ' " . f 'X ,H __ " ~ }'" V' , • - "'" :'''~ ~ ~."'. ""~!"! 'tN' , , JI "'1'0 /, ".u, ~ '" \

Zilo, " . . '.prbdu'~t s,,~Cifica~ion .••...•. '. ':;:",

, , '

June

1987

Features

General Description

2037-001. 002

I , " ; 'I.;

Z8601/Z8603 Z86111Z8613 Z8®

I!II Complete microcomputer, 2K (8601) or 4K (8611) bytes of ROM, 128 bytes of RAM, 32 I/O lines, and up to 62K (8601) or 60K (8611) bytes addressable external space each for program and data memory.

!lD 144-byte register file, including 124 general- purpose registers,Jour I/O port registers, and 16 status and control registers.

II!l Average instruction execution time of 1.5 /LS, maximum of 1 /LS.

II Vectored, priority interrupts for I/O, counter/timers, and UART.

The 28 microcomputer introduces a new level of sophistication to single-chip architecture.

Compared to earlier single-chip micro- computers, the 28 offers faster execution; more efficient use of memory; more sophisticated interrupt, input/output and bit-manipulation capabilities; and easier system expansion.

Under program control, the 28 can be tailored to the needs of its user. It can be configured as a

PORTO (NIBBLE PROGRAMMABLE) I/O OR Aa-A15

PORT 1 (BYTE PROGRAMMABLE) 110 OR AD,-AD,

PORT 3 SERIAL AND PARALLEL 110 AND CONTROL

2860l Single-Chip MCU with 2K ROM

28603 Prototyping Device with 2K EPROM Interface 28611 Single-Chip MCU with 4K ROM . 28613 Prototyping Device with 4K EPROM Interface iii Full-duplex UART and two programmable

8-bit counter/timers, each with a 6-bit programmable prescaler.

Il:l Register Pointer so that short, fast instruc- tions can access any of nine working register groups in 1 /LS.

tllI On-chip oscillator which accepts crystal or external clock drive.

I!] Single + 5 V power supply-all pins TTL compatible.

1:'1 12.5 MHz.

stand-alone microcomputer with 2K or 4K bytes of internal ROM, a traditional-microprocessor that manages up to 124K bytes of external memory, or a parallel-processing element in a system with other processors and peripheral controllers linked by the 2-BUS® bus. In all configurations, a large number of pins remain available for I/O.

+5V P3,

XTAL2 P3,

XTAl1 P2,

P3, P2,

P3, P2s

RESET P2,

RIW P2,

os P2,

AS P2,

P3s P20

GND P3,

P3, P3,

PO, P1,

PO, P1.

PO, P1,

PO, P1,

PO, P1,

POs P1,

PO, P1,

PO, P1,

Figure 2a. 40-pin Dual-In-Line Pacl,age (DIP).

Pin Assignments

Pin Description

AS. Address Strobe (output, active Low).

Address Strobe is pulsed once at the begin- ning of each machine cycle. Addresses output via Port 1 for all external program or data memory transfers are valid at the trailing edge of AS. Under program control, AS can be placed in the high-impedance state along with Ports 0 and 1, Data Strobe and Read/Write.

OS. Data Strobe (output, active Low). Data Strobe is activated once for each external memory transfer.

POO-P07' PIo-PI7' P2o-P27' P30-P37. IIOPort Lines (input/outputs, TTL-compatible). These 32 lines are divided into four 8-bit I/O ports that can be configured under program control for I/O or external memory interface.

RESET. Reset (input, active Low). RESET ini- tializes the Z8. When RESET is deactivated,

program execution begins from internal program location OOOCH.

ROMIess. (input, active LOW). This pin is only available on the 44 pin versions of the Z8601 and Z8611. When connected to GND disables the internal ROM and forces the part to function as a Z8681 ROMless Z8. When left unconnected or pulled high to Vee the part will function normally as a Z8601 or Z8611.

R/W. Read/Write (output). R/W is Low when the Z8 is writing to external program or data memory.

XTALl. XTAL2. Crystall, Crystal2 (time-base input and output). These pins connect a parallel resonant 12.5 MHz crystal or an external single- phase 12.5 MHz clock to the on-chip clock oscillator and buffer.

~ ... '::!!.-t),

~CJ q"~<l"'.¢"'.¢"':if' q"~'l"''l''''<l''~'l'''~

RESET ⁷ RrW 8

os ⁹

AS 10 P3s 11 GND 12 P3, 13 PO. 14 PO, 15 PO, 16 ROMless 17

6 5 4 3 2 t « ~ ~ ~ ~

Z8601/11 MCU

18 19 20 21 22 23 24 25 26 27 28 qt:,~ q~::l" q0ft, qO'O q({\q"f:J <I. ... q ... q ... ~ ~l ... "" ~CJ

39 NC 38 P2.

37 P2, 36 P2, 35 P2, 34 P2.

33 P3, 32 P3.

31 P17 30 Pl.

29 PIs

Figure 2b. 44-pin Chip Carrier. Pin Assignments

Architecture 28 architecture is characterized by a flexible Three basic address spaces are available to support this wide range of configurations:

program memory (internal and external), data memory (external) and the register file (inter- nal). The 144-byte random-access register file is composed of 124 general-purpose registers, four I/O port registers, and 16 control and status registers.

2037-003

I/O scheme, an efficient register and address space structure and a number of ancillary features that are helpful in many applications.

Microcomputer applications demand power- ful I/O capabilities. The 28 fulfills this with 32 pins dedicated to input and output. These lines are grouped into four ports of eight lines each and are configurable under software control to provide timing, status signals, serial or parallel I/O with or without handshake, and an address/

data bus for interfacing external memory.

Because the multiplexed address/data bus is merged with the I/O-oriented ports, the 28 can assume many different memory and I/O con- figurations. These configurations range from a self-contained microcomputer to a micropro- cessor that can address 124K (28601) or 120K (28611) bytes of external memory.

OUTPUT

To unburden the program from coping with real-time problems such as serial data com- munication and counting/timing, an asynchro- nous receiver/transmitter (UART) and two counter/timers with a large number of userse- lectable modes are offered on-chip. Hardware support for the UART is minimized because one of the on-chip timers supplies the bit rate.

XTAL AS

2048 x 8·BIT 28611 }

Z8601 r...._-::=:~_..11 4096 x 8·BIT

110 (BIT PROGRAMMABLE)

ADDRESS OR 110 (NIBBLE PROGRAMMABLE)

ADDRESS/DATA OR 110 (BYTE PROGRAMMABLE)

Figure 3. Functional Block Diagram

Address Spaces

Program Memory. The 16-bit program counter addresses 64K bytes of program memory space.

Program memory can be located in two areas:

one internal and the other external (Figure 4).

The first 2048 (28601) or 4096 (28611) bytes consist of on-chip mask-programmed ROM. At addresses 2048 (28601) or 4096 (28611) and greater, the 28 executes external program memory fetches.

The first 12 bytes of program memory are reserved for the interrupt vectors. These loca- tions contain six 16-bit vectors that correspond to the six available interrupts.

Data Memory. The 28 can address 62K (28601) or 60K (28611) bytes of external data memory beginning at location 2048 (28601) or 4096 (28611) (Figure 5). External data memory may

••

^{53 •}

0 . . Z8601 2 2047

Location of Ilrst byte 01 Instruction executed after reset

IntelTUpt Vector (Lower Byte)

'ci

11 10

•

8 7 5

•

EXTERNAL ROM OR RAM

ON·CHIP ROM

~---

lAOS IR05 IRQ4 IRQ4 IR03 IR03 IRQ2

IntelTUpt Vector (Upper Byte)

4~ IRQ2

3 IRQ1

2 IRQ1

IROO

0 IRQO

~:~Z8611 4

Figure 4. Program Memory Map

LOCATION 255 254 253 252 251 250 24.

248 247 246 24.

244 243 242 241 240

127

STACK POINTER (BITS 7-0) STACK POINTER (BITS 15-8) REGISTER POINTER PROGRAM CONTROL FLAGS INTERRUPT MASK REGISTER INTERRUPT REQUEST REGISTER INTERRUPT PRIORITY REGISTER

PORTS 0-1 MODE PORT 3 MODE PORT 2 MODE TO PRESCAlER TIMER/COUNTER 0

T1 PRESCALER TIMER/COUNTER 1

TIMER MODE SERIAL 110

NOT IMPLEMENTED

i

GENERAL·PURPOSE REGISTERS

PORT 3 PORT 2 PORT 1

IDENTIFIERS SPL SPH RP FLAGS IMR IRQ IPR P01M P3M P2M PREO TO PRE1 T1 TMR SIO

P3 P2 P1

be included with or separated from the external program memory space. DM, an optional I/O function that can be programmed to appear on pin P34, is used to distinguish between data and program memory space.

Register File. The 144-byte register file includes four IIO port registers (RO-R3), 124 general-purpose registers (R4-R127) and 16 control and status registers (R240-R255). These registers are assigned the address locations shown in Figure 6.

28 instructions can access registers directly or indirectly with an 8-bit address field. The 28 also allows short 4-bit register addressing using the Register Pointer (one of the control regis- ters). In the 4-bit mode, the register file is

EXTERNAL DATA MEMORY

Z8601 ~~ 1---I=~Z8611

NOT ADDRESSABLE

Figure 5. Data Memory Map

-_I

^{I rrr,rsr, o 0 0 0 25 25} 24 The upper nibble of the register file addres

;>---provided by the register pointer specifies the active worklng·reglster group.

--

12

-- --

_. --

SPECIFIED WORKING·

- f - REGISTER GROUP

-- ,...-

--

~---'IO"O"TS---15 The lower nibble of the register file address provided by the Instruction points to the specified register.

Serial Input/

Output

Counter/

Timers

2037-009

divided into nine working-register groups, each occupying 16 continguous locations (Figure 6).

The Register Pointer addresses the starting location of the active working-register group ..

Staclts. Either the internal register file or the external data memory can be used for the stack.

Port 3 lines P30 and P37 can be programmed as serial I/O lines for full-duplex serial asynchro- nous receiver/transmitter operation. The bit rate is controlled by Counter/Timer 0, at 12 MHz.

The 28 automatically adds a start bit and two stop bits to transmitted data (Figure 8). Odd parity is also available as an option. Eight data bits are always transmitted, regardless of parity

T

Transmitted Data (No Parity)

LSTARTBIT ' - - - E I G H T DATA BITS

TWO STOP BITS

Transmitted Data (With Parity)

ISplpl

pl~I~I~I~I~I~I~lsij

T ^I

' - - - S E V E N DATA BITS ^{LSTART BIT} ' - - - 0 0 0 PARITY

TWO STOP BITS

A 16-bit Stack Pointer (R254 and R255) is used for the external stack, which can reside anywhere in data memory between locations 2048 (8601) or 4096 (86U) and 65535. An 8-bit Stack Pointer (R255) is used for the internal stack that resides within the 124 general-purpose registers (R4-RI27).

selection. If parity is enabled, the eighth bit is the odd parity bit. An interrupt request (IRQ4) is generated on all transmitted characters.

Received data must have a start bit, eight data bits and at least one stop bit. If parity is on, bit 7 of the received data is replaced by a parity error flag. Received characters generate the IRQ3 interrupt request.

Received Data (No Parity) Ipl~I~I~I~I~I~I~I~lsij

LSTARTBIT ' - - - E I G H T DATA BITS ' - - - O N E STOP BIT

Received Data (With Parity) Iplpl~I~I~I~I~I~I~lal

I L

_ L S T A R T B I T

' - - - S E V E N OATA BITS PARITY ERROR FlAG ' - - - O N E STOP BiT

Figure S. Serial Dala Formala

The 28 contains two 8-bit programmable counter/timers (To and Tl), each driven by its own 6-bit programmable prescaler. The Tl prescaler can be driven by internal or external clock sources; however, the To prescaler is driven by the internal clock only.

The 6-bit prescalers can divide the input fre- quency of the clock source by any number from I to 64. Each prescaler drives its counter, which decrements the value (l to 256) that has been loaded into the counter. When the counter reaches the end of count, a timer interrupt request-IRQ4 (to) or IRQ5 (Tl)-is generated.

The counters can be started, stopped, restarted to continue, or restarted from the initial value. The counters can also be pro- grammed to stop upon reaching zero (single-

pass mode) or to automatically reload the initial value and continue counting (modulo-n contin- uous mode). The counters, but not the presca- lers, can be read any time without disturbing their value or count mode.

The clock source for T I is user-definable and can be the internal microprocessor clock divided by four, or an external signal input via Port 3. The Timer Mode register configures the external timer input as an external clock, a trigger input that can be retriggerable or non- retriggerable, or as a gate input for the internal clock. The counter/timers can be prog'rammably cascaded by connecting the To output to the input of T I. Port 3 line P36 also serves as a timer output (TOUT) through which To, TI or the inter- nal clock can be output.

I/O Ports The 28 has 32 lines dedicated to input and output. These lines are grouped into four ports of eight lines each and are configurable as input, output or address/data. Under software control, the ports can be programmed to provide address

Port 1 can be programmed as a byte 1/0 port or as an addressldata port for interfacing external memory. When used as an I/O port, Port

I may be placed under handshake con- trol. In this configuration, Port 3 lines P33 and P34 are used as the handshake controls RDY J and DAV J (Ready and Data Available).

\ Memory locations greater than 2048 (28601) or 4096 (28611) are referenced through Port I. To interface external memory, Port I must be programmed for the multiplexed Address/Data mode. If more than 256 external locations are required, Port 0 must output the additional lines.

Port I can be placed in the high-impedance state along with Port 0, AS, DS and RIW,

Port 0 can be programmed as a nibble 1/0 port, or as an address port for interfacing external memory. When used as an 1/0 port, Port 0 may be placed under handshake con- trol. In this configuration, Port 3 lines P32 and P35 are used as the handshake controls DAVo and RDYo. Handshake signal assignment is dictated by the 1/0 direction of the upper nibble P04-P07·

For external memory references, Port 0 can provide address bits As-AlJ (lower nibble) or As-AJ5 (lower and upper nibble) depending on the required address space. If the address range requires 12 bits or less, the upper nibble of Port 0 can be prograrvmed independently as 1/0 while

Port 2 bits can be programmed independently as input or output. The port is always available for 1/0 operations, In addition, Port 2 can be configured to provide open-drain outputs.

Like Ports 0 and 1, Port 2 may also be placed under handshake control. In this con- figuration, Port 3 lines P3J and P36 are used as the handshake controls lines DAV 2 and RDY 2.

The handshake signal assignment for Port 3 lines P3 J and P36 is dictated by the direction (input or output) assigned to bit 7 of Port 2.

Port :3 lines can be configured as 1/0 or control lines. In either case, the direction of the eight lines is fixed as four input (P30-P33) and four output (P34-P37)' For serial I/O, lines P30 and P37 are programmed as serial in and serial out respectively.

Port 3 can also provide the following con- trol functions: handshake for Ports 0, 1 and 2 (DAVand RDY); four external interrupt request signals (IRQO-IRQ3); timer input and

outputs, timing, status signals, serial I/O, and parallel 1/0 with or without handshake. All ports have active pull-ups and pull-downs compatible with TTL loads.

allowing the 28 to share common resources in multiprocessor and,DMA applications. Data transfers can be controlled by assigning P33 as a ,Bus Acknowledge input and P34 as a Bus

Request output.

PORT 1 (Ito OR ADo-AD1)

Figure 9a. Pori 1

the lower nibble is used for addressing. When 'Port 0 nibbles are defined as address bits , they

can be set to the highimpedance state along with Port 1 and the control signals AS, DS and RIW.

'Meu Z8

I

^{(110 OR PORT 0 A.-A1~}

_ } ~:~~~~~~NTROLS (P32 AND P3S>

Figure 9b. Pori 0

PORT 2(110)

} HANDSHAKE CONTROLS

DAV2 AND RDYz (P3l AND P3S>

Figure 9c. Port 2

PORT 3 (UO OR CONTROL)

Figure 9d. Pori 3

Interrupts

Clock

The 28 allows six different interrupts from eight sources: the four Port 3 lines P30-P33, Serial In, Serial Out, and the two counter/timers.

These interrupts are both maskable and prioritized. The Interrupt Mask register globally or individually enables or disables the six inter- rupt requests. When more than one interrupt is pending, priorities are resolved by a pro- grammable priority encoder that is controlled by the Interrupt Priority register.

All 28 interrupts are vectored. When an inter- rupt request is granted, an interrupt machine

The on-chip oscillator has a high-gain, parallel-resonant amplifier for connection to a crystal or to any suitable external clock source (XTALl = Input, XTAL2 = Output).

The crystal source is connected across XTALl and XTAL2, using the recommended capacitors

cycle is entered. This disables all subsequent interrupts, saves the Program Counter and status flags, and branches to the program memory vector location reserved for that interrupt. This memory location and the next byte contain the 16-bit address of the interrupt service routine for that particular interrupt request.

Polled interrupt systems are also supported. To accommodate a polled structure, any or all of the interrupt inputs can be masked and the Interrupt Request register polled to determine which of the interrupt requests needs service.

(Cl s 15 pF) from each pin to ground. The specifications for the crystal are as follows:

III AT cut, parallel resonant

III Fundamental type, 12.5 MHz maximum III Series resistance, Rs

s

1000