Digital Equipment Corporation Maynard, Massachusetts
PDP-15 Systems
. Volume 1.
Maintenance Manual
PDP-15 SYSTEMS
MAINTENANCE MANUAL VOLUME 1
DEC-lS-H2BB-D
1st Printing October 197'0 2nd Printing December 1970
Copyright © 1970 by Digital Equipment Corporation
The material in this manual is for informa- tion purposes and is subject to change with- out notice.
The following are trademarks of Digital Equipment Corporat ion, Maynard, Massachusetts:
DEC FLIP CHIP DIGITAL
PDP FOCAL
COMPUTER LAB
CONTENTS
Page CHAPTER 1 GENERAL DESCRIPTION
1.1 Introduction 1-1
1.2 System Descripti on 1-1
1.3 Central Processor 1-4
1 .3. 1 K P 15 Centra I Processor 1-4
1.3.2 Teletype Control 1-4
1.3.3 KC15 Console 1-4
1.3.4 KE 15 Extended Arithmetic Element 1-4
1.3.5 KF15 Power Fail 1-6
1.4 I/O Processor 1-6
1.4.1 KD15 I/O Processor 1-6
1.4.2 KW15 Real-Time Clock 1-6
1.5 Memory 1-6
1.5.1 . MM15 Memory 1-6
1.5.2 MK 15 4K Memory Expander 1-6
1.5.3 MP 15 Memory Parity 1-7
1.6 BA 15 Peripheral Option Expander 1-7
1.6.1 PC 15 High-Speed Paper-Tape Reader/Punch 1-7
1.6.2 LT15A Single Teletype Control 1-7
1.6.3 VP15 Display Control 1-7
1.7 BB 15 Internal Option Expander 1-7
1 .7. 1 KA 15 Automatic Priority Interrupt 1-8
1.7.2 K M 15 Memory Protect 1-8
1.7.3 KT15 Memory Protect and Relocate 1-8
1.8 System Interconnecti ons 1-8
1 .8. 1 CPU and IPU-to-Memory Bus 1-8
1.8.2 IPU-to-I/O Devi ces 1-8
1.8.3 Console-to-CPU 1-9
1.8.4 BB Option Panel to Central Processor 1-9
1.9 System Specifications 1-9
CHAPTER 2 MEMORY
2.1 Introduction 2-1
2.2 Core Addressing Matrix 2-1
2.2.1 Stack Dimensions 2-1
CONTENTS (Cont)
Page
2.2.2 X - Y Matrix Constructi on 2-2
2.2.3 Inhibit/Sensing Construction 2-2
2.3 Control Logic Architecture 2-5
2.4 Control Logic Flow 2-6
2.4. 1 Read/Restore C yc Ie 2-8
2.4.2 Clear;Write Cycle 2-8
2.4.3 Read/Pause;Write Cycle 2-9
2.5 Memory Port Switch 2-12
CHAPTER 3 CENTRAL PROCESSOR
3. 1 Registers 3-1
3.1.1 Accumu lator (AC) 3-1
3.1.2 link (L) 3-1
3.1.3 Program Counter (PC) 3-1
3.1.4 Memory Input Register (MI) 3-1
3.1.5 Memory Output Register (MO) 3-2
3.1.6 Operand Address Register (OA) 3-2
3.1.7 Instru.ction Register (IR) 3-2
3.1.8 Index Register (XR) 3-2
3.1.9 limit Register 3-2
3.2 Bus Structure 3-2
3.2. 1 C Bus 3-3
3.2.2 A Bus 3-4
3.2.3 B Bus 3-4
3.2.4 Sum Bus 3-4
3.2.5 Shift Bus 3-5
3.3 Data Manipulation Hardware 3-5
3.4 Control State Generation 3-6
3.5 Addressing 3-7
3.5. 1 Page Mode 3-7
3.5.2 Bank Mode 3-9
3.6 Memory Read and Write 3-10
3.7 Instruction Fetch 3-10
3.8 Instruction Operation Detai Is 3-11
3.8. 1 Read Group (LAC, ADD, TAD, AND, XOR) 3-11
3.8.2 DAC and DZM 3-11
3.8.3 JMP 3-11
3.8.4 JMS and CAL 3-11
CO NTE NTS (Cont)
Page
3.B.5 ISZ 3-15
3.B.6 SAD 3-16
3.B.7 XCT 3-16
3.B.B OPR 3-16
3.B.9 LAW 3-17
3.B.l0 lOT 3-17
3.B.11 Index Group (XG) 3-17
3.B.12 Interrupts (API and PI) 3-1B
3.9 Defer and Auto-Increment 3-1B
3.10 Console Operati on 3-20
3. 10. 1 Console Cable Multiplexer 3-20
3.10.2 Key Functi ons 3-21
3. 11 Read In 3-21
CHAPTER 4 I/O PROCESSOR
4.1 KD15 Input/Output Processor 4-1
4.2 Timing Generator 4-3
4.3 Request Synchronization 4-4
4.4 lOT 4-4
4.5 I/O Bus 4-5
4.6 Data Channel Faci! ity (DCH) 4-5
4.7 I/O Bus Device Priority and Synchronization 4-16
4.B Single Cycle Input Transfers 4-18
4.9 Single Cycle Output Transfers 4-24
4.10 Multicycle Input Transfers 4-24
4.11 Multicycle Output Transfers 4-35
4.12 Add to Memory 4-35
4.13 Increment Memory 4-35
4.14 Inhibit Increment the Current Address 4-35
4.15 Data Channel Latency 4-43
4.16 Program Interrupt 4-43
CHAPTER 5 POWER DISTRIBUTIO N
5.1 General 5-1
5.2 715 Power Supply 5-1
CO NTE NTS (Cont)
Page
5.3 AC Control 5-2
5.4 DC Power Source 5-2
5.5 Bulk Regulation 5-3
5.6 Power Harness 5-4
5.7 Local Regulation 5-4
5.8 Power Mon itor Network 5-4
CHAPTER 6 OPTIONS
6.1 KE 15 Extended Arithmetic Element (EAE) 6-1
6.1.1 Genera I Operati on 6-1
6.1.2 Normal ize Instructions 6-3
6.1 .3 MUL (S) Instructi on 6-6
6.1.4 DIV(S) Instruction 6-15
6.1.5 IDIV(S) Instructi on 6-20
6.1.6 FRDIV(S) Instructi on 6-21
6.1.7 Indicators 6-22
6.1.8 EAE Execution Times 6-22
6.2 KW15 Real-Time Clock 6-22
6.3 KF15 Power Fail Option 6-23
6.4 KA 15 Automatic Priority Interrupt (API) 6-26
6.4.1 General Description 6-26
6.4.2 Operational Description 6-29
6.5 Mp15 Memory Parity 6-35
6.6 K M 15 Memory Protect 6-36
6.7 KT15 Memory Protect and Relocate 6-40
6.8 PC 15 High-Speed Paper-Tape Reader/Punch 6-43
6.8.1 High-Speed Reader 6-43
6.8.1.1 Alpha Mode 6-44
6.8.1.2 Binary Mode 6-45
6.8.1.3 Read-In 6-45
6.8.2 High-Speed Punch 6-45
6.9 L r15A Teletype Interface 6-45
6.10 VP 15 General Description 6-52
6.10. 1 Display Control 6-53
6.10.2 Digital-to-Analog Converters (D/ A) 6-53
CO NTE NTS (Cont)
Page
6.10.3 VP15A Storage Tube Display lOTs 6-54
6.10.3.1 Non-Store Mode 6-54
6.10.3.2 Store Mode 6-54
6.10.3.3 Store and Non-Store Mode 6-54
6.10.4 VP15C and VP15B Oscilloscope lOTs 6-54
6.10.5 Principles of Operation 6-55
CHAPTER 7 MAINTENANCE
7.1 Introducti on 7-1
7.2 System Maintenance 7-1
7.2.1 Maintenance Equipment 7-1
7.2.2 Mai ntenance Test Programs 7-2
7.3 Preventive Maintenance 7-4
7.3.1 Introducti on 7-4
7.3.2 Scheduled Maintenance 7-5
7.4 Corrective Maintenance 7-6
7.4.1 Introducti on 7-6
7.4.2 Preliminary Investigation. 7-7
7.4.3 System Troubleshooting 7-7
7.4.4 Console Checks 7-8
7.4.5 Processor Troubleshooting 7-9
7.4.6 Logic Troubleshooting 7-10
7.4.7 Module (Circuit) Troubleshooting 7-11
7.4.8 Repairs and Replacements 7-12
7.4.9 Validation Tests 7-13
7.4.10 Recording 7-14
7.5 Ad justment Procedure 7-14
7.5.1 DC Voltage Adjustments 7-14
7.5.2 Memory Timing Adjustments 7-16
7.5.2.1 Memory Strobe 7-16
7.5.3 CP Timing Adjustment 7-17
7.5.3.1 CP Clock 7-17
7.5.4 I/O Timing 7-19
7.5.4.1 I/O Clock 7-19
7.5.4.2 Console Clock 7-19
CONTENTS (Cont)
Page
7.5.4.3 Teletype Clock 7-21
7.5.5 Timing Adjustment Summary 7-21
IllUSTRA TIO NS
Figure No. Title Art No. Page
1-1 PDP-15 Configuration 15-0272 1-1
1-2 PDP-15 System Block Diagram 15-0274 1-2
1-3 PDP-15/10 System Configuration Diagram 15-0013 1-3
1-4 PDP-15/20 System Configuration Diagram 15-0326 1-3
1-5 PDP-15/30 System Configuration Diagram 15-0327 1-5
1-6 PDP-15/40 System Configuration Diagram 15-0328 1-5
2-1 Current Path Diagram 15-0133 2-3
2-2 Sense Amplifier/Inhibit Driver, Simplified 15-0119 2-3 Diagram
2-3 Typical Inhibit Current Waveforms 15-0275 2-4
2-4 Basic Device-Memory Control Signal Flow 15-0276 2-7
2-5 Memory Cycle Detailed Flow Chart 15-0311 2-13
2-6 Central Processor Read Cycle 15-0277 2-15
2-7 Central Processor Write Cycle 15-0278 2-16
3-1 CPU Bus Structure 15-0279 3-3
3-2 :Page (PDP-15) Mode Address Formation 15-0280 3-8
3-3 :Bank (PDP-9) Mode Address Formation 15-0281 3-9
3-4 Read-In Flow Diagram 15-0294 3-22
4-1 Basic I/O Timing 15-0282 4-3
4-2 lOT Instruction Format 15-0203 4-4
4-3 lOT Instruction Timing 15-0176 4-6
4-4 lOT Flow Diagram 15-0293 4-7
4-5 I/O Bus Cables 15-0325 4-9
4-6 Data Channel Block Diagram 15-0181 4-17
4-7 Simplified M104 Module Diagram 15-0283 4-17
4-8 M 104 Timing Diagram 15-0087 4-18
4-9 Single Cycle Data In Transfer, Block Dia- 15-0284 4-19 gram
4-10 Single Cycle Data In Transfer, Detai led 15-0285 4-21 flow Chart
ILLUSTRATIONS (Cont)
Figure No. Title Art No. Page
4-11 Single Cycle Back-To-Back Transfer, 15-0286 4-23 Detailed Flow Chart
4-12 Single Cycle Data Out Transfer, Block 15-0287 4-25 Diagram
4-13 Single Cycle Data Out Transfers, Detailed 15-0288 4-27 Flow Chart
4-14 Multicycle Data In Transfer, Block Diagram 15-0289 4-29
4-15 Multicycle Timing Diagram 15-0274 4-31
4-16 Multicycle Data In Transfer, Detailed Flow 15-0290 4-33 Chart
4-17 Multicycle Data Out Transfers, Block Di- 15-0291 4-37 agram
4-18 Multicycle Data Out Transfer, Detailed 15-0298 4-39 Flow Chart
5-1 Power Distribution Block Diagram 15-0292 5-1
6-1 EAE General Flow Diagram 15-0301 6-4
6-2 EAE Multiply 15-0302 6-7
6-3 EAE Divide 15-0303 6-17
6-4 Real-Time Clock, General Flow Diagram 15-0134 6-24 6-5 Power Fail Sequence With Power Fail Op- 15-0308 6-25
tion Disabled, Flow Diagram
6-6 Power Restore Sequence With Power Fai I 15-0305 6-25 Option Disabled, Flow Diagram
6-7 Power Fai I Sequence With Power Fail Op- 15-0307 6-26 tion Enabled, Flow Diagram
6-8 Power Restore Sequence With Power Fai I 15-0306 6-27 Option Enabled, Flow Diagram
6-9 API Flow Diagram 15-0310 6-31
6-10 API/PI/Central Processor Flow Diagram 15-0309 6-33
6-11 KM 15 Memory Protect Flow Diagram 15-0313 6-39
6-12 KT15 Memory Protect/Relocate Flow Dia- 15-0312 6-42 gram
6-13 Tape Format and Accumulator Bits 15-0232 6-44
6-14 HRI Tape Format and Accumulator Bits 15-0233 6-46 6-15 High-Speed Reader Operation, Flow Dia- 15-0315 6-47
gram
6-16 High-Speed Punch Operation, Flow Diagram 15-0314 6-48
6-17 Teletype Receiver (Keyboard) Timing 15-0318 6-50
Figure No.
6-18 6-19 7-1 7-2 7-3 7-4 7-5 7-6 7-7 7-8 7-9 7-10 7-11 7-12 7-13 7-14
Table No.
1-1
2-1 2-2 3-1 3-2 3-3 3-4 3-5 3-6 3-7 4-1
4-2
6-1 6-2
ILLUSTRATIONS (Cont) Title
Teletype Transmitter (Printer) Timing VP 15 Controller, Simpl ified Block Diagram Integrated Circuit Location
Integrated Circuit Pin Location G821 Module Adjustment
G822 Module Adjustment Locations G823 Module Adjustment Locations MEM Current
MEM Strobe Delay
MEM Strobe/Sense Amp Output CP Clock
TS01 Duration Machine Cycle Time I/O Clock
Console Clock Teletype Clock
TABLES Title
Art No.
15-0317 15-0316 15-0295 15-0296 15-0297 15-0299 15-0300
PDP-15 Central Processor Cycle Times, Basic and Ex- panded Configurations
Memory Bus Signals and Data Lines Control Flops and Register Responsibilities Control States for LAC Instruction
CPU/Memory Interacti on Instruction Operation ISZ Instruction Operati on XCT Instruction Operation Deferred Addressing Operation Auto-Increment 0 perat ion
Summary of PDP-15 Input/Output Facilities I/O Bus Signal Functions
EAE Instructions EAE Microinstructions
Page 6-51 6-55 7-12 7-12 7-15 7-15 7-16 7-16 7-17 7-18 7-18 7-19 7-20 7-20 7-21 7-22
Page 1-10 2-5 2-10 3-7 3-12 3-13 3-15 3-16 3-19 3-20
4-2
4-10 6-2 6-3
TABLES (Cont)
Table No. Title Page
6-3 EAE NOP 640000 6-9
6-4 OSC 640001 6-9
6-5 OMQ 640002 6-9
6-6 CMQ 640004 6-10
6-7 LACS 641001 6-10
6-8 LACQ 641002 6-10
6-9 ABS 644000 6-11
6-10 CLQ 650000 6-11
6-11 LMQ 652000 6-11
6-12 GSM 664000 6-12
6-13 LRS 6405XX and LRSS 6605XX 6-12
6-14 LLS 6406XX and LLSS 6606XX 6-13
6-15 ALS 6407XX and ALSS 6607XX 6-13
6-16 NO RM 640444 and NO RMS 660444 6-13
6-17 MULS 6531XX and MULS 6571XX 6-14
6-18 DIV 6403XX and DIVS 6443XX 6-19
6-19 IDIV 6533XX and IDIVS 6573XX 6-21
6-20 FRDIV 6503XX and FRDIVS 6543XX 6-21
6-21 EAE Indicators 6-22
6-22 Standard API Channel/Priority Assignments 6-28
6-23 MP 15 10 T Instructi ons 6-36
6-24 High-Speed Reader lOTs 6-44
6-25 High-Speed Paper Tape Punch 6-45
6-26 Primary Teletype lOTs 6-49
6-27 The L T 15A Instructi on Set 6-52
6-28 Settling and Intensification Times 6-56
7-1 Mai ntenance Equipment 7-2
7-2 MAINDEC Diagnostic Programs 7-3
7-3 PDP-15 Timing Adjustment Summary 7-22
INSTALLATION MANUAL
MODULE MANUAL
HARDWARE
ACCEPTANCE TE ST PROCEDURES
INTERFACE MANUAL
MANUFACTURERS EQU I PMENT
MANUALS
PDP-15 FAMILY OF MANUALS
OPERATORS GUIDE
SOFTWARE
MACRO -15
FOCAL-15
UTILITY PROGRAMS
MANUAL
FORTRAN IT
8/15 TRANSLATOR
15-0040
SYSTEMS REFERENCE MANUAL - Provides overview of PDP-IS hardware and software systems and options, in- struction repertoire, expansion features, and descriptions of system peripherals. (DEC-IS-BRZB-D)
USER'S HANDBOOK VOLUME I, PROCESSOR - Princi- pal guide to system hardware includes system and sub- system features, functional descriptions, machine-language programming considerations, instruction repertoire, and system expansion data. (DEC-IS-H2DB-D)
VOLUME 2, PERIPHERALS - Features functional de- scriptions and programming considerations of peripheral devices. (DEC-lS-H2DB-D)
OPERATOR'S GUIDE - Lists procedural data, including operator maintenance, for using the operator's console and the peripheral devices associated with PDP-IS Systems.
(DEC-lS-H2CB-D)
PDP-IS/IO SYSTEM USER'S GUIDE - Features COM- PACT and Basic I/O Monitor operating procedures.
(DEC-IS-GG I A-D)
PDP-IS/20 SYSTEM USER'S GUIDE - Lists Advanced Monitor System operating procedures. (DEC-lS-MG2B-D) BACKGROUND/FOREGROUND MONITOR SYSTEM USER'S GUIDE - Lists operating procedures for the DEC- tape and disk-oriented Background/Foreground monitors.
(DEC-IS-MG3A-D)
PDP-IS/IO SOFTWARE SYSTEM - Describes COMPACT software system and Basic I/O Monitor System.
(DEC-IS-GRI A-D)
PDP-IS/20/30/40 ADVANCED MONITOR SOFTWARE SYSTEM - Describes Advanced Monitor System; programs include system monitor language, utility, and application types; operation, core organization, and input/output operations within the monitor environment are discussed.
(DEC-IS-MR2A-D)
PDP-IS/30/40 BACKGROUND/FOREGROUND MONI- TOR SOFTWARE SYSTEM - Describes Background/
Foreground Software System including the associated language, utility, and applications program.
(DEC-IS-MR3A-D)
RSX USER MANUAL - Describes the disk-oriented real time system executive language and applications.
MAINTENANCE MANUAL VOLUME I, PROCESSOR - Provides block diagram and functional theory of operation of the processor logic; lists preventive and corrective maintenance data. (DEC-lS-H2BB-D)
VOLUME 2, ENGINEERING DRAWINGS - Provides engi- neering drawings and signal glossary for the basic processor and options. (DEC-lS-H2BB-D)
INST ALLA nON MANUAL - Provides power specifica- tions, environmental considerations, cabling, and other information pertinent to installing PDP-IS Systems.
(DEC-IS-H2AB-D)
ACCEPTANCE TEST PROCEDURES - Lists step-by-step procedures designed to insure optimum PDP-IS Systems operation.
PDP-IS MODULE MANUAL - Provides characteristics, specifications, timing and functional descriptions of mod- ules used in PDP-IS Systems. (DEC-IS-H2EA-D)
INTERF ACE MANUAL - Provides information for inter- facing devices to a PDP-IS System. (DEC-IS-HOAB-D)
UTILITY PROGRAMS MANUAL - Provides utility pro- grams common to PDP-IS Monitor systems.
(DEC-lS-YWZA-D)
MACRO-IS - Provides MACRO assembly language for the PDP-IS. (DEC-IS-AMZA-D)
FORTRAN IV - Describes PDP-IS version of the FORTRAN IV compiler language. (DEC-lS-KFZA-D)
FOCAL-IS - Describes an algebraic interactive compiler level language developed by Digital Equipment Corpora- tion. (DEC-IS-KJZB-D)
CHAPTER 1
GENERAL DESCRIPTION
1 • 1 I NTRO DUCTIO N
This chapter identifies and describes the modular parts of the PDP-15 system hardware, and shows how they are incorporated into the system. Figure 1-1 shows the physical location of these parts in the PDP-15 system configurati on. Figure 1-2 is a block diagram of the inter-connection of the elements of the system which are covered by this manual. Other options are covered by separate manuals.
1.2 SYSTEM DESCRIPTION
715 PS
H963D BAY 00
MM15 MK15
KP15 K015 KE15 KF15 KW15
KC15
8815
8A15
H963E BAY1R
INO PANEL FANS
KT15 KM15
01 SPLAY
PC05
FANS PC1S VP15 OW15A
MP15 KAIS
LT15A
1~-0272
Figure 1-1 PDP-15 Configuration
The PDP-15 System consists of a KP15 Central Processor, KD15 I/O Processor, KC15 Console, MM15 Memory, associated cabinets, hardware, power supplies, and any of a large number of options.
I I 1 I
I I
MM15 MK15 MM15 MK15 MM15 I MK15 MM15 MK15
4K I I
I 4K 4K 4K 4K I 4K 4K 4K
n: ni n: n,
I J I r I I
BB15
B8 OPTION CABLE MEMORY DATA LINES
MEM MEM MEM
PROTECT RELOCATE PARITY
KM15 KT15 MP15
API KA15
MEMORY PORT SWITCH BA15
IPU CPU
PC15 KD15 KP15
READER PUNCH
VP15 KE15 EAE
-
01 SPLAY KW15 RTC KF15 PWRFAILH I
TTY CONTROL TTY
LT15A TTY
POS 110 BUS I BUS
POS I/O BUS
KC15 CONSOLE DW15A
NEG I/O BUS
~ POS TO NEG BUS CONVERTER
15 -0274
Figure 1-2 PDP-15 System Block Diagram
Hardware configurations for which special software systems have been developed are designated as follows:
a. PDP-15/10 Compact System - consists of a 4K core memory, Central Processor, I/O Pro- cessor, and ASR33 Teletype ®. This is the basic PDP-15 System (see Figure 1-3).
b. PDP-15/20 Advanced Monitor System - consists of the basic PDP-15 with 8K of core memory, DECtape control and 2 DECtape transports, high-speed paper-tape reader/
punch, extended arithmetic element, and KSR 35 Teletype (see Figure 1-4).
® Teletype is a registered trademark of Teletype Corporation.
LOGO
MEMORY
CP/IO
CP/IO
CONSOLE
r - - - POWER SUPPLY
FANS CARAVEL FAN
LOGIC r - - _ I
ENCLOSED LOGIC C
INTER- ONNECTION
COVERS MOVABLE) (RE
C
D O O R - - - -
DEC 19" CABINET DIMENSIONS:
30" DEEP 2HI/16"WIDE 71- 7/16" HIGH
POWER SUPPLY
REAR - D O O R
15-0013
Figure 1-3 PDP-15/10 System Configuration Diagram
35 KSR TELETYPE
H963D (BAY 00) FAN
MM15A, MK15A 8K MEMORY
KPI5 CENTRAL PROCESSOR AND 1/0 PROCESSOR AND KE 15 EXTENDED ARITHMETIC ELEMENT
KC15 CONSOLE TABLE
715 POWER SUPPLY
H963E (BAYIR) FAN INDICATOR
BLANK
PC15 HIGH SPEED PAPER TAPE READER/PUNCH BLANK FANS
BA15 (CONTROL FOR PC15)
BLANK AC UTILITY OUTLETS
H963F (BAY 2R) FAN INDICATOR
BLANK
TU56 DUAL DECTAPE TRANSPORT
TCI5 DECTAPE CONTROL
BLANK
Fiaure 1-4 PDP-15/20 System Configuration Diagram
15-0326
c. PDP-15/30 Background-Foreground System - consists of a PDP-15/20 with a 16K core memory, four IDECtapes, a real-time clock, automatic priority interrupt, a second on- line Teletype and memory protect (see Figure 1-5).
d. PDP-15/35 Disk Oriented Real-Time Executive System (RSX) - consists of a PDP-15/2~
with a 16K co(e memory, two DECtape transports, automatic priority interrupt option, real-time clock, a DECdisk file with 262K words of storage and memory protect.
e. PDP-15/40 Disk Oriented Background-Foreground System - consists of a PDP-15/30 with a 24K core memory, two DECtapes, DECdisk Control, two random access DECdisk files with a capacity of 524K words of storage and memory protect (see Figure 1-6).
1.3 CENTRAL PROCESSOR 1 .3. 1 KP 15 Central Processor
The KP15 Central Processor functions as the main component of the computer by carrying on bi- directional communication with both the memory and I/O Processor. Provided with the capability to perform all required arithmetic and logical operations, the central processor controls and executes stored programs. It accomplishes this with an extensive complement of registers, control lines, and logic.
1 .3.2 Teletype Control
This provides the control fori the console Teletype which may be an ASR or KSR Type 33 or 35 Tele- type. Logic is provided for the hardware readin of tapes from the Teletype reader in systems withoul"
high-speed tape facilities. Characters may be read from the keyboard in either half-duplex mode (characters echoed onto the printer) or full-duplex mode.
1 .3.3 KC 15 Console
The KC 15 Control Console provides facilities for operator initiation of programs, monitoring of central processor (CPU) and I/O Processor (IPU) registers, starting program executi on and the manual exami··
nation and modification of memory contents.
1.3.4 KE15 Extended Arithmetic Element (optional)
The optional KE15 Extended Arithmetic Element (EAE) facilitates high-speed arithmetic operations alld register manipulations. The EAE adds an la-bit multiplier quotient register (MQ) to the system as well as a 6-bit step counter register (SC). Worst case multiplication time is 7.4 tJS; division time is 7.65 tJS.
3S KSR TELETYPE
3S KSR TELETYPE
H963D (BAY 00) FAN
MMI5 A, MKISA 8K MEMORY (See Note I) KP1S CENTRAL PROCESSOR AND
~EOI~~~~~~~~~I
ARITHMETIC ELEMENT, AND KWIS REAL TIME CLOCK
KCIS CONSOLE TABLE
71S POWER SUPPLY
NOTES
H963E (BAY IR) FAN INDICATOR FANS
KAIS AUTOMATIC PRIORITY INTERRUPT AND
KMI5 MEMORY PROTECTION
BLANK
PCI5 HIGH SPEED PAPER TAPE READER /PUNCH BLANK FANS
BAIS (CONTROL FOR LTISA AND PCIS) BLANK AC UTILITY OUTLETS
H963F (BAY 2R) FAN INDICATOR
BLANK
TUS6 DUAL DECTAPE TRANSPORT TU 56 DUAL DECTAPE TRANSPORT
TCIS DECTAPE CONTROL
BLANK
I. An Identical 8K memory is mounted on the rear door of cabinet H963D.
There is space on this door for mounting two more 8K modules.
Figure 1-5 PDP-15/30 System Configuration Diagram
H963B (BAY 2L) FAN INDICATOR RFI5 DECDISK CONTROL
RS09 DECDISK
RS09 DECDISK
AI R DISTRI BUTION SYSTEM AND POWER SUPPLIES
H963D (BAY 00)
FAN
MMI5A. MK15A 8K MEMORY (See Note I) KPI5 CENTRAL PROCESSOR AND
~~~t~~f~~5~~'
ARITHMETIC
~~~~ERNEALAND
TIME CLOCK
KCI5 CONSOLE TABLE
71S POWER SUPPLY
H963E (BAY IR) FAN INDICATOR FANS KA15 AUTOMATIC PR IORITY INTERRUPT AND
KMI5 MEMORY PROTECTION
BLANK
PC15 HIGH SPEED PAPER TAPE READER/PUNCH BLANK FANS
BA15 (CONTROL FOR LTl5A AND PCI5)
AC UTILITY OUTLETS
H963F (BAY2R) FAN INDICATOR
BLANK
TU56 DUAL DECTAPE TRANSPORT
TUS6 DUAL DECTAPE TRANSPORT
TCI5 DECTAPE CONTROL
BLANK
33 KSR TELETYPE
NOTES
1. Two more 8K memory modules are mounted on the rear door of cabinet H963D. There is space on this door for mounting one more 8K module.
Figure 1-6 PDP-15/40 System Configuration Diagram
15-0327
33 KSR TELETYPE
15-0328
1.3.5 KF15 Power Fail (optional)
The KF15 Power Fail option offers maximum protection to programs during power failure and recovery of power after failure. It enables the PDP-15 system to store active registers in memory before power diminishes to a point beyond which data will be lost. It also enables the PDP-15, upon the restora- tion of power, to restore these registers and continue with the program that was previously in progmss.
1.4 I/O PROCESSOR 1 .4. 1 K D 15 I/O Processor
The KD15 Processor (IPU) is an autonomous subsystem of PDP-15 which supervises and synchronizes :JII lOT and Data Channel (DCH) transfers between the devices and the PDP-15 central processor and memory. The I/O Processor contains the arithmetic and control logic hardware to supervise all I/O device activity. The IPU is, however, a passive system in that it responds to requests for activity from devices or the CPU rather than initiating activity.
1.4.2 KW15 Real-Time Clock (optional)
The KW15 Real-Time Clock option gives the user a time reference capability. The real-time clock produces clock pulses at a rate of 1 every 16.7 ms for 60 Hz systems; these systems increment a com location which can be preset and monitored under program control.
1.5 MEMORY 1 .5. 1 MM 15 Memory
The MM 15 Memory is the primary storage area for the computer instructions and data. Memory is or- ganized into pages which are paired into memory banks. Each MM15 has 4K l8-bit binary words of
high-speed random access magneti c core storage. Each bank is a unit of 8K words. The Central Pro- cessor and I/O Processor have provisions to address up to 128K words of core memory with the aid of a MX 15 Memory Multiplexer. Any word in memory may be addressed by either the Central Processor or the I/O Processor.
1 .5.2 MK 15 4K Memory Expander (optional)
This option expands the MM15 memory control from 4K to 8K 18-bit words. It consists of the core memory stack and the necessary read/write circuits and must be used with an MM 15.
1.S.3 MP1S Memory Parity (optional)
The MP15 Memory Parity option enables the PDP-1S to continuously check information being read from core memory and determine whether information has been erroneously picked up or dropped. It does this by monitoring all information as it is being sent to the memory for storage, and writing a parity bit. When this word is read from memory, the word and the bit are checked to determine whether any information has been changed, and a parity error flag is raised if a change is detected.
1.6 BA1S PERIPHERAL OPTION EXPANDER
This option houses power and I/O bus interface logic for the PC15, LT1SA, and VP1S which are des- cribed below; only one BA lS is required per system.
1.6.1 PC15 High-Speed Paper-Tape Reader/Punch (optional)
This option includes a PCOS Reader/Punch and the control to interface it to the PDP-1S. Characters can be read from paper tape at a maximum rate of 300 characters per second or punched at a rate of SO characters per second. When this opti on is installed, the PC lS, instead of the TTV, is used for hardware READIN.
1.6.2 LT1SA Single Teletype Control (optional)
This option provides the logic to receive and transmit information through a KSR33 or KSR3S Teletype.
This provides a second Teletype capabil ity to the PDP-15 system.
1 .6.3 VP1S Display Control (optional)
This opti on interfaces the PDP-15 to vari ous display devi ces by providing the digital-to-analog con- verters and the control logic for the x and y positioning as well as the intensification of the VP1SA Storage Tube Display, VP1SB Oscilloscope Display, or VP1SC X-V Oscilloscope Display.
1.7 BB15 INTERNAL OPTION EXPANDER
This expander houses the power, I/O bus interface, memory bus interface and various control signals from the processor for the operati on of the KA 15 Automati c Priority Interrupt, KM 15 Memory Protect,
KT1S Memory Protect and Relocate, and MP15 Memory Parity options. Only one BB15 is required per system.
1 .7.1 KA 15 Automatic Priority Interrupt (API - optional)
The API option adds 8 additional levels of priority to the PDP-15. The upper 4 levels are assigned to I/O devices and are inifiated by flags (interrupt requests) from these devices. The lower four levels are programming levels ond are initiated by software requests. High data rate or critical device:; are assigned to high priority levels and can interrupt slower device service routines. The API option holds the slower device interrupt request until it can be serviced. The cause of the interrupt is also direct- ly identified eliminating the need for service routines and flag search routines.
1.7.2 KM15 Memory Protect (optional)
The KM 15 memory protect provides the PDP-15 core memory with protected memory locations tha~
cannot be accessed by the user. It includes a boundary register and associated control logic to e:;tab- lish the lower limit of the user's program. It has the facility to trap lOT , HALT OAS and chained execute instructions and the addressing of a non-existent memory bank.
1.7.3 KT15 Memory Protect and Relocate (optional)
The memory protect and relocate option is similar to the memory protect option. The KM15 must be used with the KT15. However, it contains a relocation register as well as a core allocation regis~er.
The relocation register provides the lower limit of the user program and relocates the user upward from the real machine location by the quantity contained in the relocation register. The core allocatkm register indicates the last 256 word increment available to the user. Other features of the memor:, protect option are also included in this option.
1.8 SYSTEM INTERCONNECTIONS 1 .8. 1 CPU and IPU-to-Memory Bus
The central processor and I/O processor each asynchronously access memory over the same memory da- ta lines (MDl). The priority structure concerning which processor's request is sent to memory is dE~ter
mined by the memory port switch . The I/O processor is given first priority. The memory data linE~s consist of 18 bi-directional lines over which address and then data information is transmitted to and from memory. Various control signals are on this bus.
1.8.2 IPU-to-I/O Devices (I/O Bus)
The I/O processor commun;icates with all devices over a common I/O bus which contains bi-
directional data lines; address lines; enable, request, and grant lines for API and data channel; and others such as program interrupt and skip request.
1 .8.3 Console-to-CPU (I Bus)
The indicator bus contains bi-directional lines to transmit information to the lights on the console and switch information from the console to the central processor. Several control lines are also located on the cable.
1.8.4 BBOption Panel to Central Processor
Because the BB15 Option Panel contains several internal options which deal with the operation of the central processor, a special cable is required so that the option may utilize these internal central pro- cessor signals.
1.9 SYSTEM SPECIFICATIONS Functi ona I Characteri sti cs
Word Length Cycle time
Core memory capacity Core memory access
Page mode Direct Indirect Indexed Bank mode
Direct Indirect Computati on rate ASR33 Teletype
Program-controlled I/O capacity Data channel capacity
18 bits
Refer to Table 1-1
4096 words, expandable to 131,072 words in 4K increments
4096 words 32,768 words 131,072 words
8,192 words 32,768 words
625,000 additions per second 10 characters per second
Up to 256 devices including prewired CPU and IPU lOTs
Up to 8 device controllers Operating Characteristics (H963D Cabinet; CP, I/O and Memory)
Power requirements
Power consumpti on
Power supply outputs after local regulation
115± 15%,50 or 60 cps±2%, single phase, 18-30A or 230V ± 15%, 50 or 60 cps ± 2%, si ng I e phase, 18-30A
4 KW max +5, -6, -24 Vdc
Logic levels
Test temperature range Relative humidity Heat dissipation
Dimensions
Cabinet height Cabinet width Cabi net depth Shelf widths Shelf depth
Door clearance (rear) Cabinet weight (loaded) Teletype height
Teletype width Teletype depth Teletype weight
O-.4V
=
logic 0 50o-120°F10-95%
13,650 BTU/hr.
71-7/16 in.
21 - 11 /16 in . 30 in.
19 in.
19-5/16 in.
18-7/32 in.
750 Ibs.
8-3/8 in.
22 in.
18-1/2 in.
441bs.
Table 1-1
2.4-5V
=
logic 1PDP-15 Central Processor Cycle Times, Basic and Expanded Configurations*
Not In User Mode In User Mode
Configurati on Read Write Read Write
Max Typical Max Typical Max Typical Max Typi(:al
Basic 800 800 800 800 800 800 800 80D
K M 15 Memory Protect 830 800 830 800 830 800 975 92)
KM 15 Memory Protect and 965 880 965 880 1165 1080 1165 lOB) KT15 Memory Protect/Relocate
MP15 Memory Parity 1100 1050 1100 1050 1100 1050 1100 1050
MP15 Memory Parity and 1130 1130 1130 1255
K M 15 Memory Protect
MP 15 Memory Parity, 1155 1155 1355 1355
KM15 Memory Protect and KT15 Memory Protect/R~locate
. , -
* All cycle times are listed in nanoseconds.
CHAPTER 2 MEMORY
2. 1 I NTRO Dueno N
The basic PDP-15 computer has a 4096 word, 18-bit memory. It occupies the top four racks of the PDP-15 mainframe (racks A through D). The principal elements comprising rack A are control logic, bus drivers, and INPUT slots for the memory bus cables. The memory address and memory buffer reg- isters, x- and y-select and driver controls, and OUTPUT slots for the memory bus cables comprise rack B. The stack matrix, sense amps and inhibit drivers, and slots for the indicator bus, make up racks C and D.
This basic memory may be expanded to 8192 words by adding a 4K stack, a set of X- and Y-select and driver modules, and a set of inhibit and sense amp modules. The appropriate slots are available in the MM 15 and the addition is the option ca lied MK 15.
Each 4K unit of memory is called a page. Two 4K pages form an 8K bank. The physical capacity of the mainframe is 32K (32,768) words. One 8K bank of memory is located above the mainframe front panel. The three remaining 8K banks are located on the rear door. This 32K unit is called a block of memory.
2.2 CORE ADDRESSING MATRIX 2.2.1 Stack Dimensions
The MM 15 memory stack is a three dimension-three wire matrix (3D-3 wire). The term three dimen- sion refers to an X-current, a Y-current, and an inhibit current. The X- and Y -currents are used to switch the direction of the flux of a core; the inhibit current is used during the writing time to pre- vent the writing of bits where 0 bits are desired.
One matrix control network is used for each 4096 core words. The memory address selects which word of the 4096 words is to be read or written into or both. The drive current pulses are generated by G223 Read/Write Drivers. G222 Memory Selectors steer the direction of these currents.
When these currents flow through the core region they pass through 18 planes; the X-current pulse through one set of wires and V-current pulse through another set of wires. In each plane, the X and Y current pulses intersect at one of the possible 4096 cores (bits). This happens in all 18 planes pr::>- ducing an 18-bit word selection. A nineteenth plane is added for parity options.
The inhibit current pulse occurs only during a write portion of the memory cycle. The inhibit current controls the bit data to be written into the address selected. This control is accomplished by stringing a wire through all the cores of each individual plane to nullify the effect of the Y current at the core intersection point. In addition to using these wires for the inhibit current during a write portion of a memory cycle, they are used for sensing the data during a read portion of a memory cycle.
2.2.2 X-V Matrix Construction
Each of the 4096 word locations provided by a 64 x 64 X-V matrix may be referenced by a 12-bit memory address. This memory address is separated into two sections: bits 06-11 for the Y-select alld bits 12-17 for the X-select. It is decoded by the G222 modules. The tota I combination resu Its in a 4096 word selection. The current pulse, generated from the G223s, provides the current needed to change the flux in the core. There is a G223 for each X and Y matrix.
Figure 2-1 shows the current path produced by the combination of the modules and stack. Although this figure represents only one matrix of either X or Y, both matrices run at the same time. The so! id arrows show a read current path and the dashed arrows show a write current path through the same se- lected network. In this figure one can visualize four different core line paths by having pre-selecl'ed the gates. Block schematics MM06 through MM09 (Volume 2) show the X and Y matrices contained in a bank of memory. The 'I Loop is a jumpered wire on the back panel wiring for observation of current waveforms on an oscilloscope. There is a loop for each matrix.
2.2.3 Inhibit/Sensing Constructi on
The construction of the sense/inhibit network consists of one wire threaded through all the cores in each plane. The circuitry, for the sensing of a bit during a readtime and inhibiting during a write'~
time, is contained in the Gl00 Sense Amplifier and Inhibit Driver modules.
The G 100 module contains four sense amplifiers and four inhibit drivers. Five of these modules are used in the PDP-15 for each 4K memory stack. (Refer to block schematics MM10 through MM15.) Each inhibit driver consists of a two-input NAND gate and a high-speed current switch. One driver is used for each bit plane of the memory array. An inhibit signal is received by all inhibit drivers only during a write operation (see Figure 2-2).
READ CURR ENT
WRITE CURRENT - - - -...
---,
I RE~
1/2 G223
SOURCE 1
I
I
'-.1
" I r-- ---,
...L I I
I I -: :
I 1 WRITE SOURtE 1
SINK I 1
I •
11
01 :- 1
I I L .J
-24y+ l
1 1
1/2 G223 ~---*----~--~~--~--~~--~---\.1:
_ _ _ ...I I rl
SELECTEDMA~
READ~
WRITE _ _ _ _ _ _ _
...JIlL...-___ _ i"" L
-24YT:
I ---~MA HI GH
Figure 2-1 Current Path Diagram
AD2 AC1 STROBE
MA LOW
AH1
AVI (TEST POINT)
15-0119
Figure 2-2 Sense Amplifier/Inhibit Driver I Simpl ified Diagram
Each driver also receives a signal indicating the state of the corresponding bit in the MB. Inhibit drivers that receive a signa:1 indicating a 0 state in the MB bit are gated on and cause inhibit current to be applied to the associated bit plane of the memory array. Each inhibit driver employs a dis- charge network to speed up inhibit current cutoff. The output of the inhibit driver is connected to the middle of one core sensing string, which represents one bit plane of the memory array. The bal un network at the front end of the sense amplifier ensures equal current at all times through both sides of the core stri ng •
In addition to the balun network, the sense amplifier consists of a differential amplifier and output driver. One sense amplifier is used for each bit plane of the memory array. During a read operation only the signal induced on the sense winding of a core plane by a core-changing state is received by the differential amplifier. The differential amplifier has a nominal threshold of 17 mV. Output pulses of standard ampl itude and durati on are suppl i ed by the output driver when the sense amplifi er reads a logi c 1 from the associated core, and is strobed by a standard positive going pulse at AC 1 • Propagation delay from the input to the sense amplifier to the buffered output is 25 ns {maximum} and from strobe input to buffered output is 15 ns {maximum}. These output pulses directly set the MB re~l
ister.
Typical waveforms of the inhibit current and the test point of the sense amplifier during a readtime (~re
shown in Figure 2-3. The only way to look at an inhibit current is to place a current probe around one of the twisted pairs of wires coming out of the stack at the plug end.
X-YDRIVE
r :
CURRENTS ~. READ:
CORE OUTPUT (READ TIME) (TEST POINT)
I -1
I
I 1-50 NS
INHIBIT CURRENT
.~/
WRITE
Figure 2-3 Typical Inhibit Current Waveforms
15- 0275
2.3 CONTROL LOGIC ARCHITECTURE
The control logic is designed so that each bank can be coupled to one bus network called the memory bus. Each bank responds when address lines 03 and 04 equal the setting of the manual switches on the bank select card. These two switches can be preset by the operator (refer to Volume 2, drawing MM01).
Maintenance hint: Any computer with more than one bank of memory may interchange one addressing bank number with another bank. All that is necessary is to manipulate the toggle switches on each bank of memory. No two should be set to the same number. Volume 2, drawing MM01 shows the logic representation of the switches.
An exchange of signals between the memory and the device requesting access to the memory provides asynchronous operation. The device has to provide five control signals, a 17-bit address (15 bits for 32K addressing and two more bits for the multiplexer option when addressing up to 128K) I 18 bits of data I and one more bit for parity, when a parity option is included. In return the memory accepts the signals and notifies the device with a combination of four control signals and 18 bits of data plus one bit for parity checking. Table 2-1 identifies the bus signals and data lines on the memory bus. All signal lines are considered activated when at ground level. All data lines are considered a one when at ground level.
Table 2-1
Memory Bus Signals and Data Lines
Abbreviation Signal & Directi on Definition
MDLOO-17 Memory Data Li nes, Sends a seventeen bit word to memory I address- (MA) 00 through 17 ing up to 128K locations.
(Memory Address to memory)
(DATA) (Data bidirectional) Data consisting of 18 bits per word going in both directions on the memory data lines (MDL).
MWR Memory Write Two levels used by the memory to identify what MRD Memory Read (to mode of operation the device has selected.
(to memory) There are three:
1 Read/Restore (MRD ground) (MWR high) 2 Clear/Write (MRD high)
(MWR ground) 3 Read/Pause/Write (MRD ground)
(MWR ground) M REQ Memory Request (to The initial signal that begins the memory cycle.
memory)
M BUSY B Memory Busy on the This signal inhibits a memory request from being Bus (from Memory accepted by any memory bank on the same bus bank to other Mem- while anyone of the memory banks is busy.
ory banks)
Abbreviation
ADR ACK B
RD RST B
DATA ACK
MRLS
MRLS ACK B
M PAR
Table 2-1 (Cont)
Memory Bus Signals and Data Lines
Signal & Direction
Address Acknow- ledge on the Bus (to device)
Read/Restart on the bus (to device)
Data Acknowledge (to memory)
Memory Release (to memory)
MemQry Re I ease Acknowledge on the Bus (to dev i ce) Memory Parity (bi- directional)
Definition
Notifies the device of acceptance of the Memo- ry Request, the Memory Address, and the mode of operation (MRD and MWR signals).
Notifies the device that the memory data is on the bus for the device to strobe into its buffer.
This signal occurs only during a Read/Restore cy- cle or Read/Pause/Write cycle.
Notifi es the memory that it may take the memo- ry data off the bus. This signal is only needed during a Read/Restore cycle or a Read/Pause/
Write cycle.
Notifies the memory it has accepted the data from memory during a Read/Restore cycle. Dur- ing a Clear/Write cycle or a Read/Pause/Write cycle, this signal tells the memory the devi ce has placed data on the bus.
Notifies the device that the memory accepted the data from the device and the memory cycle is terminating.
This signal line carries a 19th bit of data to be stored into or readout of memory. This bit is used to check data errors when a memory parity option is implemented into the system.
Refer to Figure 2-4 for the device-memory control signal flow.
Only one memory is a I lowed to be activated at a time. In order to guarantee that only one bank wi II be accessed, a Memory Busy level (refer to Volume 2, MM01 and MM19) is placed on the bus, in- hibiting any other Memory Request from being accepted. The internal timing of this signal, as well as all other signals, is descri~ed in Paragraph 2.4.
2.4 CONTROL LOGIC FLOW
Refer to Figure 2-4. The memory is able to operate in any of three modes: Read/Restore, Clear/
Write, or Read/Pause/Write. The mode of operation to be selected depends entirely upon the needs of the device. This can be seen as the sequence of a memory cycle is defined.
Before memory can be started, Memory Busy must not be true and a 17-bit memory address (MOL 00-11') and MRD, MWR, or both must be activated on the bus.
DEVICE
M REO
0 - M REO
MRLS DATA ACK
O-MRLS 0 - DATA ACK
DEVICE
M REO
0 - M REO
MRLS
O-MRLS
READ CYCLE
WRITE CYCLE
MEMORY
ADR ACK
o ___ADR ACK RD RST
MRLS ACK
o - R D RST
o -MRLS ACK
MEMORY
ADR ACK
0---- ADR ACK
MRLS ACK
0---- MRLS ACK
READ/PAUSE/WRITE CYCLE DEVICE
M REO
O-M REO
DATA ACK
MRLS
O-MRLS 0---. DATA ACK
MEMORY
ADR ACK
O-ADR ACK RD RST
o -BUS ENABLE
MRLS ACK O-RD RST
o --e.MRLS ACK
15-0276
Figure 2-4 Basic Device-Memory Control Signal Flow
The memory cyc Ie starts with the Memory Request level from the device. This level is generated 50 ns after the above levels to allow for settling time on the bus. (Settling time is needed to avoid potential skewing problems.) The device will wait until it receives an acceptance level from the memory called Address Acknowledge (ADR ACK (1) B L). This occurs approximately 110 ns after M REQ. The initiation of this level tells the device that the memory has accepted the request forac- cess to memory, the mode of operation, and has strobed the memory address lines into the MA latch register. The Address Acknowledge causes Memory Busy to go low and a Iso clears the Memory Request level. The fall of the Memory Request level clears the Address Acknowledge level. At this point the sequence of the memory cycle may go into any of the three modes of operation. Each is described in the following paragraphs.
2.4.1 Read/Restore Cycle
For this mode of operation the RD CON (read control) flop would have been set and the memory would proceed to read data from the address requested. The 18 bits of data read from core are strobed into the Memory Buffer register and enable'd on the bus (MDL 00-17) approximately 150 ns after ADR ACK is set. A parity bit is also strobed, if the option is present (MDL PAR (1) B L). In order to a "ow for settling time on the bus, the .device only strobes this data when a Read/Restart level (RD RST (1) B L) is placed on the bus by the memory, approximately 100 ns after the data is on the bus. The total dafa access time is approximately 350 ns.
After a delay, the memory sets the WR EN (write enable) flop which is ANDed with the WR CON (write control) flop on a zero state to begin the write portion of the cycle. The sequence is to rewri re the data from the memory buffer registers into the same location from which it was read. In parallel with the memory data rewrite, the device sends a level called Data Acknowledge (DATA ACK L) wh ich the memory uses to clear the bus enable register, removing data from the bus. A Memory Release level (MRLS L) is sent at the same time as the Data Acknowledge level to tell the memory that the device has accepted the data. When the MRLS level has been received and the write enable flop has been set in the memory, the memory sends to the device an acknowledge called MRLS Acknowledge (MRLS ACK (1) B L). The device uses the MRLS ACK level to clear its MRLS level which, in turn, clears MRLS Acknowledge. (This sequence occurs in every mode of operation.) The memory cycle then terminates with the Memory Bus level (M Busy B L) going high.
2.4.2 Clear;Write Cycle
For this mode of operation the WR CON (write control) flop is set, and the memory proceeds to read the data from the address requested as is done ina Read/Restore cycle. The exceptions are that the data is not loaded into the Memory Buffer, and the bu~ enable and read/restart flops are not set. Th(~
function of this read is to clear the core location for the writing process. In parallel with this, the device accepts the Address Acknowledge level and places the data to be written into memory on the bus. To ensure settling time on the bus, a 50 ns delay occurs before the MRLS level is sent to memory.
In the memory, an MB load pulse is generated with the MRLS level and the data is loaded into the Memo.ry Buffer register. A Data Acknowledge level is not needed at this time with the MRLS level because it is only used to clear the bus enable register.
The MRLS level sets the MRLS ACK flop telling the device that the memory has accepted the data. The MRLS ACK flop ANDed with the Write Enable flop (detecting the termination of the read portion of this cycle) begins the write portion of this cycle, writing the data into the address requested.
During the write portion, a delayed sequence sets the inhibit flop and the write flop. The inhibit flop ANDed with the memory buffer bits produces inhibit currents that are applied to each individual bit plane, depending on the status of the memory buffer bit. A Zero bit initiates the current pu lse. The memory cycle then terminates with a Memory Busy level going high.
2.4.3 Read/Pause/Write Cycle
For this mode of operation both the read control and write control flops are set. The memory proceeds to read the data from the address requested as in a Read/Restore cycle. When the Read/Restart level is sent out to the device, the device strobes the data into its registers and proceeds to modify the data.
The device at this time sends to memory a Data Acknowledge level which in turn clears the bus enable flop taking the memory data off the bus. The MRLS level is not sent at this time. The write enable flop does not initiate a write portion of the cycle. Instead the memory cycle halts. This is called the Pause portion of the Read/Pause/Write cycle.
While the memory is in the Pause state, the device modifies the data it has previously read from the memory and places it back on the bus. In order to provide settling time on the bus, the MRLS level is sent to the memory approximately 50 ns after the data is on the bus. When the memory receives MRLS, the modified data is strobed into the memory buffer registers. The write portion of this cycle begins with the MRLS ACK flop and the Write enable flop set. The data is written into the same address as requested at the beginning of this cycle. A Memory Address Hold flop ensures the address will be saved throughout the cycle. The memory cycle then terminates with a Memory Busy level going high.
The advantage of a Read/Pause/Write cycle is that a memory word may be read, modified, and rewritten in one memory cycle. An example of this is when a device wishes to update a current address location by adding one and restoring it. The flow chart in Figure 2-5 shows these same sequences with a little more attention to the internal logic flow.
Table 2-2 describes control flop and register nomenclature and major responsibilities. It is an aid in understanding the detailed flow chart shown in Figure 2-5.
Abbreviati on
RD Con WR Con
MA HOLD
MAOO through MA 17
ADR ACK
RDY
RDX
MBOO through MB17 PAR MB
BUS EN
RD RST
Table 2-2
Control Flops and Register Responsibilities
Control Flops or Register
Read Control Write Control
Memory Address Hold
Memory Address 00 through 17 (bus ad- dress to memory di- rection only)
Address Acknowledge (bus signal)
Read Y-matrix
Read X-matrix
Memory Buffer 00 through 17
Pari ty Memory Buffer (bus data, bidirec- tional)
Bus Enable
Read/Restart (bus signal)
Responsibi lity
Strobed when a request is accepted.
Holds data throughout memory cycle.
Tells memory which one of the three modes to pursue.
Cleared and set when a request is ac- cepted. It holds the memory address in- formation in the latches throughout the memory cycle.
A set of 18 latches which contain the ad- dress to be accessed duri ng the memory cycle.
This control flop tells the device that it has accepted the request for memory use and strobed in the address. It will clear itself with the loss of the Memory Request on the bus.
This control flop turns on the y-matrix cur- rents duri ng a read porti on of a memory cycle. It automatically clears after ap- proximately 200 ns.
This control flop turns on the x-matrix cur- rents during a read portion of a memory cycle. It sets 50 ns after the RDY register to minimize stack noise. It clears at the same time theRDY register clears.
A set of 18 buffers plus a parity register are cleared when a request has been ac- cepted. During a Read/Restore cycle they are di recti y set from the sense amp I ifi ers • During a Clear/Write cycle they are strobed, accepti ng data from the memory bus.
This control flop enables the data in the memory buffers, that was read out of mem- ory, onto the memory bus. A Data Ack-
nowedge from a device clears it.
This control flop is used to tell the device that data from memory is stable on the.
memory bus. It sets only during a readout cycle and clears with a Memory Release Acknowledge.
Abbrevi ati on
WREN
MRLS ACK EN
MRLS ACK
INH
WR
BUS DONE
WRDONE
Table 2-2 (Cont)
Control Flops and Register Responsibilities
Control Flops or Register
Write Enable
Memory Release Acknowledge Enable
Memory Re I ease Acknowledge (bus signal)
Inhibit
Write
Bus Done
Write Done
Responsibi I ity
This control flop is used to set up a defi- nite delay between the readout of memory and the rewrite back into memory on a Read/Restore cyc Ie. It a I so sets up a net- work to accept a Memory Release from the device.
This control flop ensures a delay time be- fore a Memory Release is accepted by the memory. This delay is important during a Clear/Write cycle. It sets with the Write Enable register setting, and clears on the next Memory Address Hold register clear in the next cycle.
This control flop is used to tell the device that it has accepted the devi ces Memory Release. It will clear itself with the loss of the Memory Release on the bus.
This control flop enables all the inhibit drivers only during a write portion of a memory cycle. The on-time is approxi- matey 200 ns.
Not being concerned with stack noise at this time, this register turns on both the x- and y-matrices only during the write portion of the memory cycle. The on- time is approximately 175 ns. It is de- layed 25 ns after the Inhibit register to allow for the slower rise time of the in- hibit current to skew up with the Write.
This control flop setS with a setting of the Memory Release Acknowledge register. It denotes the extent of ti me that the memo- ry bus is busy. The next setti ng of the Read X register will clear it.
This control flop is used to set up a defi- nite delay between the write portion of the memory cycle and the read portion of the next memory cycle. It sets with the termination of the write and clears on the next setti ng of the Read X reg i ster •
