ARM Architecture Emanuele Valea

20  Download (0)

Full text

(1)

ARM Architecture

Emanuele Valea

valea@lirmm.fr

LIRMM - CNRS

October 23, 2019

(2)

Computer Organization

Hardware:

I CPU (Central processing Unit): it is the "brain" of the computer

I Datapath: registers and ALU (Arithmetic-Logic Unit) I Control Unit: it sets the datapath according to the executed

instruction

I Memory: the place where software programs (program instructions) and data (program variables) are stored I I/O devices: enter data into the computer and display the

outputs

Software: programs

I A program is a set of instructions that the computer hardware can execute

(3)

Emanuele VALEA - valea@lirmm.fr 3

Computer Organization

(4)

Inside the CPU

Datapath:

I Register le: a register is a storage location inside the CPU I ALU: performs all the arithmetic computations and logic

evaluations Control Unit:

I Decodes and monitors the execution of instructions and coordinates the operations.

I It manages some special registers, for example:

I Program Counter(PC): keeps track of the address of the next instruction to be executed

I Status Register: ags the instruction execution result

(5)

Emanuele VALEA - valea@lirmm.fr 5

Microprocessor Basic Operations

Program (instructions) and data are stored into the memory Each instruction is fetched from memory, decoded and executed

The program counter indicates the current memory location of the program that is being run. It is automatically

incremented after each instruction

(6)

Instruction Set Architecture

The Instruction Set Architecture (ISA) is an abstract model of a computer. In more practical words, the ISA tells you how the computer is seen by the programmer (or the compiler).

The same ISA can be implemented on dierent microarchitectures.

I Example: all processors from Intel and AMD implement the x86 instruction set

In this course we'll focus on the ARMv7-M instruction set.

Software

Hardware

(7)

Emanuele VALEA - valea@lirmm.fr 7

ISA Taxonomy

The architectures can be classied according to the kind of internal storage:

(8)

ISA Taxonomy

Code Example

Operation: C = A + B

A, B and C are memory locations

R1, R2 and R3 are CPU internal registers

(9)

Emanuele VALEA - valea@lirmm.fr 9

RISC VS CISC

CISC: it is the acronym of Complex Instruction Set Computer.

It is a computer where single instructions can execute several low-level operations. In practice, each assembly instruction involves more complex hardware operations, but programs are made of a few instructions. For example, the x86 instruction set.

RISC: it is the acronym of Reduced Instruction Set Computer.

It is a computer which only uses instructions that performs very simple operations. Programs are made of a bigger number of instructions. For example, all the ARM instructions sets are RISC.

(10)

RISC VS CISC

Example

Let us take as example the multiplication of two numbers:

C = A * B CISC solution(assembly):

MULT A, B, C

Advantages:

I little work for the compiler;

I easy to program;

I little memory to store the code.

RISC solution(assembly):

LOAD R1 ,A LOAD R2 ,B MUL R3 , R1 , R2 STORE R3 , C

Advantages:

I simpler microarchitecture;

I less power consumption;

I pipeline oriented.

(11)

Emanuele VALEA - valea@lirmm.fr 11

Advanced RISC Machines (ARM)

(12)

Advanced RISC Machines

ARM Cortex-M

(13)

Emanuele VALEA - valea@lirmm.fr 13

Case Study

ARM Cortex-M4

(14)

Programmer Model

Processor Modes:

I Thread mode: Used to execute application software (default mode)

I Handler mode: Used to handle exceptions (returns to Thread mode when it has nished exception processing)

Privilege Levels:

I Unprivileged: Some Limitations (not all the registers/instructions are accessible)

I Privileged: all instructions and all resources are accessible.

(15)

Emanuele VALEA - valea@lirmm.fr 15

CPU Registers

(16)

CPU Registers

General-purpose registers (R0-R12):

I 32-bit general-purpose registers for data operations I Only low registers can use immediate values Stack pointer, SP or R13:

I The stack is a region of the data memory. It is used to perform context switching.

Link Register, LR or R14

I It stores the return address for subroutines, function calls, and exceptions.

Program counter, PC or R15

I It contains the current program address

(17)

Emanuele VALEA - valea@lirmm.fr 17

Program Status Register (PSR)

It contains ags related to the results of the last executed operation.

(18)

Memory Model

This is a 32-bit architecture. This means that data, instructions and addresses are 32 bits long.

Up to 232 memory locations can be addressed =⇒ 4GB of memory space!

The memory space is divided into sub-regions:

I Each region is given for a particular usage I Easy for portability

Data types:

I Word32 bits I Halfword16 bits I Byte8 bits

(19)

Emanuele VALEA - valea@lirmm.fr 19

Memory Model

Code: program instructions;

SRAM: to store data (example:

variables and stack);

Peripheral: on-chip peripheral like AHB, APB peripherals

External RAM: data goes to the external DRAM chip.

External device: data goes to external memory, such as ash memory.

Private Peripheral: for interacting with special peripherals (example system timer)

(20)

Memory Endianness

Architectures can be divided into:

I Big-endian I Little-endian

The ARM architectures are little-endian.

In little-endian format, the processor stores the least signicant byte of a word at the lowest numbered byte, and the most signicant byte at the highest-numbered byte.

Figure

Updating...

References

Related subjects :