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FLAT-BAND VOLTAGE CONTROL OF GaAs SIS DIODE USING PSEUDOMORPHICALLY GROWN
InGaAs GATE
T. Kinosada, K. Matsumoto, Y. Hayashi, N. Hashizume
To cite this version:
T. Kinosada, K. Matsumoto, Y. Hayashi, N. Hashizume. FLAT-BAND VOLTAGE CONTROL OF
GaAs SIS DIODE USING PSEUDOMORPHICALLY GROWN InGaAs GATE. Journal de Physique
Colloques, 1987, 48 (C5), pp.C5-285-C5-288. �10.1051/jphyscol:1987562�. �jpa-00226766�
JOURNAL DE PHYSIQUE
C o l l o q u e C5, s u p p l e m e n t au noll, Tome 48, novembre 1987
FLAT-BAND VOLTAGE CONTROL OF GaAs SIS DIODE USING PSEUDOMORPHICALLY GROWN InGaAs GATE
T. KINOSADA*, K. MATSUMOTO, Y. HAYASHI a n d N. HASHIZUME E l e c t r o t e c h n i c a l L a b o r a t o r y M i t i Japan, 1 - l - 4 2 U m e z o n o , Sakura-mura, N i i h a r i - g u n , I b a r a k i , 3 0 5 , Japan
" c e n t r a l ~ e s e a r c h L a b o r a t o r i e s , S h a r p C o r p o r a t i o n , 2 6 1 3 - 1 , Ichinomoto-cho, T e n r i - s h i , N a r a 6 3 2 , Japan
A b s t r a c t
We p r o p o s e a method f o r c o n t r o l l i n g t h e f l a t - b a n d v o l t a g e o f a GaAs S I S (Semiconductor-Insulator-Semiconductor) diode i n which we use InGaAs a s t h e g a t e m a t e r i a l . We examine i t s e f f e c t i v e n e s s by capacitance-voltage measurement. Thermal s t a b i l i t y of InGaAs-gate SIS diode i s a l s o studied.
I n t r o d u c t i o n
I n 1985 [ I ] we r e p o r t e d a p l a n a r - t y p e GaAs c o m p l e m e n t a r y i n v e r t e r , w h i c h i s a n i n d i s p e n s a b l e element f o r u l t r a - l o w power high-speed l o g i c s , employing a n n-channel a n d a p - c h a n n e l S I S emic icon duct or-~nsulator-Semiconductor) FETs [2,31. However, i n o u r complementary c i r c u i t we could n o t o b t a i n l a r g e enough n o i s e margin s i n c e t h e t h r e s h o l d v o l t a g e of t h e SIS FETs were n e a r l y zero v o l t . I n t h i s paper we d e s c r i b e a method f o r c o n t r o l l i n g t h e f l a t - b a n d v o l t a g e of a S I S d i o d e i n which InGaAs i s used a s t h e g a t e m a t e r i a l , and i t s e f f e c t i v e n e s s examined by capacitance-voltage (C-V) measurements. I f t h i s method i s a p p l i e d t o t h e GaAs SIS FET, we can optimize i t s t h r e s h o l d voltage f o r t h e use i n complementary l o g i c c i r c u i t s . We a l s o r e p o r t t h e a n n e a l i n g c h a r a c t e r i s t i c s o f t h e InGaAs-gate S I S d i o d e a n d t h e t r a n s m i s s i o n e l e c t r o n m i c r o s c o p y (TEM) o b s e r v a t i o n o f t h e l a t t i c e - m i s m a t c h e d InGaAs/AlGaAs i n t e r f a c e of t h e InGaAs-gate SIS diode.
P r i n c i p l e of Flat-band Voltage Control
F i r s t we c o n s i d e r a GaAs-gate S I S d i o d e w h i c h h a s a n n + - ~ a ~ s g a t e , a n undoped AlGaAs i n s u l a t o r , and an n--GaAs channel forming l a y e r . Fig.l(a) shows i t s energy band d i a g r a m . The f l a t - b a n d v o l t a g e of t h e GaAs S I S d i o d e i s d e t e r m i n e d a u t o m a t i c a l l y by t h e work f u n c t i o n d i f f e r e n c e b e t w e e n t h e g a t e m a t e r i a l and t h e channel f o r m i n g l a y e r m a t e r i a l . Therefore, i n t h i s c a s e t h e f l a t - b a n d v o l t a g e i s a l m o s t zero v o l t s i n c e t h e g a t e l a y e r and t h e channel forming l a y e r a r e of t h e same m a t e r i a l (GaAs). A p o s i t i v e f l a t - b a n d v o l t a g e c a n b e r e a l i z e d by s u b s t i t u t i n g a m a t e r i a l w i t h l a r g e r work f u n c t i o n t h a n t h a t of GaAs, such a s InGaAs, f o r GaAs a s t h e g a t e m a t e r i a l ( S e e Fig.l ( b ) ) . The f l a t - b a n d v o l t a g e
,
w h i c h i s e q u a l t o t h e G a A s / I n G a ~ s work f u n c t i o n d i f f e r e n c e , c a n b e c o n t r o l l e d by c h a n g i n g t h e i n d i u m c o n t e n t (x) of t h e In,Gaj-,As gate.Experimental
The s t r u c t u r e o f t h e InGaAs-gate S I S d i o d e f a b r i c a t e d i s shown i n Fig.2. The f o l l o w i n g c r y s t a l was grown by MBE on t h e nf HB GaAs s u b s t r a t e a t a l o w s u b s t r a t e t e m p e r a t u r e of 530°C throughout t h e c r y s t a l growth t o prevent t h e re-evaporation of InGaAs l a y e r , : n-GaAs ( 2 ~ 1 0 ~ ~ c m - 3 , 1.5pm) /undo ed AlGaAs (0.05pm) / n + - 1 n G a ~ s ( 3 x l 0 ~ ~ c m - 3 , x=O, 0.1, 0.15, 2001) / n + - ~ a ~ a ( 3 ~ 1 0 ~ ~ c m - 3 , 48008). A f t e r t h e c r y s t a l
Article published online by EDP Sciences and available at http://dx.doi.org/10.1051/jphyscol:1987562
C5-286 JOURNAL DE PHYSIQUE
growth, the ohmic electrodes of A u - ~ e / ~ i / A u were formed at the top side and the bottom side of the crystal and alloyed at 440°C for Imin. in the H2 atmosphere. In this structure, the InGaAs layer is designed to be thin enough to avoid the generation of the misfit dislocation at the lattice-mismatched InGaAs/AlGaAs interface, that is, to be grown pseudomorphically. The flat-band voltage was obtained from the 1MHz C-V measurement at 77K. Samples were annealed in an infrared lamp furnace without a cap under arsenic pressure to investigate the annealing characteristics of the InGaAs-gate SIS diode.
Results and Discussion
Fig.3 shows the C-V curves of the GaAs SIS diode with the In content of x=O, i.e., the GaAs gate (solid line) and x=0.1 (dash-dot line). The curves are similar to those of Si MOS diode. As expected, the C-V curve of InGaAs-gate diode shifts toward the positive voltage direction. Furthermore, the maximum capacitance in the C-V curve of the InGaAs-gate SIS diode is the same as that of the GaAs-gate SIS diode. It means that there is no additional increase of the insulator layer, i-e., there are no misfit dislocations generated, which is confirmed by the TEM study.
Fig.4 shows the dependence of the flat-band voltage of the SIS diode on the In content of the InGaAs gate ;V B=90mV for x=0.1 and VFB=I 55mV for x=O.I 5. The dash- dot line represents the TnCaAsLaAs conduction band edge discontinuity AEc (which is almost equal to the work function difference). The flat-band voltages almost correspond to AE, ,respectively,as expected. Fig.5(a) and (b) are the distributions of the flat-band voltages of the GaAs-gate and InGaAs-gate (x=0.1) SIS diode in the area of 10x5mm2, respectively. The dispersion of the flat-band voltage distribution of the GaAs-gate SIS diode is as small as rvFB=7.6mV while rvFB'5.4mV for the InGaAs-gate SIS diode. Therefore, the feature of the small flat-band voltage dispersion is retained even if the gate material is changed to InGaAs. The InGaAs/AlGa~s interface (In content x=O.?) is observe6 by TEM. TEM observation shows that there are no misfit dislocations present at the lattice-mismatched InGaAs ( x = ~ . l ) / A l G a ~ s interface
,
which means that the InGaAs layer grows pseudomorphically on the AlGaAs insulator layer. It is clearly consistent with the fact in Fig.3, i.e., the maximum capacitance does not change by introducing the thin (200A) InGaAs layer. It is also found that there are still no misfit dislocations generated and the InGaAs (x=~.l)/AlGaAs interface after the annealing process ( 8 0 0 ~ ~ for 30sec) by TEM observation. Fig.6 shows the annealing effect on the flat-band voltage for the InGaAs-gate (x=0.1) SIS diode. The samples were annealed for 3Osec at 800°C, 850°C and 900°C.
In the figure, the flat-band voltage shows little change even after the 900°C, 30sec annealing. The distributions of the flat-band voltage in the area of 10x5mm2 after the annealing process of at 800°C and 900°C are shown in Fig.7(a) and (b), respectively. Even after the annealing process, the dispersion of the flat-band voltage still remained small ; cvFB=16mV for the 800°C annealed sample, and $FB=14mV for the 900°C annealed sample.Conclusion
A method for controlling the flat-band voltage of a GaAs SIS diode by using InGaAs as the gate material was proposed and examined. By adopting thin pseudomorphically grown InGaAs gate structure, the flat-band voltage could be controlled without missing the feature of the GaAs SIS diode, i.e., the uniformity of the flat-band voltage distribution. The thermal stability of the InGaAs gate GaAs SIS diode was also presented. By applying this method to a GaAs SIS FET, a complementary SIS logic with a sufficient noise margin and a proper threshold voltage will become possible.
Acknowledgments
The authors wish to thank Dr. T. Tsurushima for his continuous encouragement for the present work. They greatly appreciate Dr. Shiraga and Dr.Fukuhara of Sumitomo Chemical Industries Ltd. for precious TEM photographs.
References
[ I ] K. Matsumoto, M. Ogura, T. Wada, T. Yao, Y. H a y a s h i , N. Hashizume, M. K a t o , N.
Fukuhara, H. Hirashima
,
and T. Miyashita, IEEE E l e c t r o n Device Lett., Vol. EDL- 7, NO. 3, pp. 182-184, 1985.I21 K. M a t s u m o t o , M. Ogura, T. Wada, N. Hashizume, T. Yao, Y. H a y a s h i , E l e c t r o n Lett., vol. 20, pp.462-463, 1984
[ 3 ] K. Matsumoto, M. Ogura, T, Wada, T. Yao, Y. H a y a s h i , N. Hashizume, M. Kato, T.
Endo, and H. Inage, E l e c t r o n Lett., vol. 21, pp.580-581, 1985
I I
u n d o p e d AlGaAs
I
I
u n d o p e dAlGa As
Fig. 1
,
E n e r g y band d i a g r a m o f GaAs S I S s t r u c t u r e w i t h ( a ) GaAs g a t e,
a n d (b) InGaAs g a t e . InGaAs h a s l a r g e r work f u n c t i o n t h a n t h a t of GaAs.25 1 I I I I
InGaAs 20nm Gate 2 0 SIS Diode
0 1 0 -
5
-
0 1
'
I I I I-2.0 -1.5 -1.0 -Q5 0 0.5 GATE BIAS ( V )
Fig. 2, F a b r i c a t e d GaAs S I S
diode w i t h InGaAs g a t e . InGaAs Fig. 3, C-V curve of GaAs SIS diode w i t h l a y e r i s t h i n enough t o grown GaAs g a t e ( s o l i d l i n e ) and InGaAs g a t e
pseudomorphically. (Dash-dot l i n e ) a t 77K.
JOURNAL DE PHYSIQUE
Composition x for InxGal,As
Fig. 4 , Dependence of flat-band voltage on In content of InGaAs gate of SIS diode-Dash-dot line indicates InGaAs /GaAs conduction band edge
discontinuity. Fig. 5, Distribution of flat-band voltage of GaAs SIS diode with (a) GaAs gate
,
and (b) InGaAs gate at 77K.Fie. 6. D e ~ e n d e n c e of flat-band (a) (b) 0.15
-
> 0.10-
mP
0.05
vo'itage of - 1 n ~ a ~ s gate (In content
is 0.1) SIS diode on annealing Fig. 7, distribution of flat-band temperature. Annealing t i m e is voltage of InGaAs gate SIS diode
3Osec. after annealing process of (a)
800°C, and (b) 900°C for 30 sec.
I I
InGaAs(x=O.l) 30sec.
20nm Gate Anneaing
-
SIS Diode-
fn *-- -
L
n Q)
-
E,
Z I f( I
g?&i)750 8 0 0 8 5 0 9 0 0 0
Annealing Temp. (OC ) 0.05 0.1 0 1 5 0.05 0.1 0 1 5
