Low temperature high voltage analog devices in a 3D sequential integration

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Low temperature high voltage analog devices in a 3D sequential integration

Camila Cavalcante, X. Garros, P. Batude, A. Tataridou, J. Lacord, M. Casse, Christoforos Theodorou, T. Karatsori, R. Gassilloud, C. Fenouillet-Beranger,

et al.

To cite this version:

Camila Cavalcante, X. Garros, P. Batude, A. Tataridou, J. Lacord, et al.. Low temperature high volt-

age analog devices in a 3D sequential integration. 2020 International Symposium on VLSI Technology,

Systems and Applications (VLSI-TSA), Aug 2020, Hsinchu, Taiwan. pp.155-156, �10.1109/VLSI-

TSA48913.2020.9203691�. �hal-02969743�

Low temperature high voltage analog devices in a 3D sequential integration

C. Cavalcante^1,3, X. Garros¹, P. Batude¹, A. Tataridou², J. Lacord¹, M. Casse¹, C. Theodorou², T. Karatsori², R. Gassilloud¹, C.

Fenouillet-Beranger¹, L. Brunet ¹,O. Rozeau¹, N. Rambal¹, F. Gaillard¹, F. Ponthenier¹, F. Allain¹, G. Romano^1,4, G. Ghibaudo², J- P. Colinge¹, M. Vinet¹, F. Andrieu¹

1CEA-LETI, MINATEC Campus, 17 rue des Martyrs, 38054 Grenoble, France / ²IMEP-LAHC MINATEC Campus Grenoble France /

3Université Grenoble Alpes, Grenoble, France / ⁴STMicroelectronics, Crolles, France

A

BSTRACT

We built an original stackable 2.5V device on FDSOI with analog performance comparable to high temperature reference and passing the PBTI reliability criteria. In depth characterization of low temperature (LT) gate stack devices with thick EOT are investigated, enabling to draw guidelines for future optimization. This paper demonstrates the feasibility of LT high V_DD analog devices, which can be used for sensor read out operation, paving the way to ultra- miniaturized smart sensor arrays.

I

NTRODUCTION

3D sequential integration (3DSI) consists in stacking active device layers on top of each other, in a sequential manner [1]. 3DSI has been identified as a key technology for More-Than-Moore applications, thought to be particularly adapted for miniaturized smart sensors arrays [2,3](Fig. 1). The challenge of 3DSI relies in processing top devices with a limited thermal budget (TB), to prevent degradation of the bottom layer. While significant work has been done to develop high-performance low TB devices for digital applications V_DD=0.8/1V [4-9], almost no work has been published on higher voltage devices. This work presents for the first time, 2.5V devices fabricated with TB in the 500°C range. In-depth electrical characterization is provided in order to conclude on the potential use of these devices for analog applications.

L

OW

TB 2.5V

ANALOG

MOSFET

Architecture - The fabricated FDSOI device have 30nm thick undoped channel, 25nm BOX, and SiO₂ = 6nm/TiN/Poly-Si gate stack (Fig. 2). A High Temperature Oxide (HTO) is used as reference. Three types of LT oxides (<500°C) have been compared (1: 6nm plasma oxidation in O2/H2 (named Pl-O2/H2); 2: 1.6nm plasma oxidation in O₂+PEALDdeposition (Pl-O₂+PEALD); 3: 6nm PEALD). Post Deposition Treatments (PDT) has also been tested (450°C O₂ plasma densification and 500°C N₂ furnace anneal). For LT devices, Solid Phase Epitaxy Regrowth (SPER) at 500°C 30min was used for junction activation. The HTO ref device underwent conventional high temperature S/D activation anneal (Fig.3).

Gate Stack Characterization - The I_ON/I_OFF trade-off is shown (Fig.

4), where a clear ION shift is observed for the LT oxide splits w.r.t HTO. Given that all the LT splits have the same S/D process, the effect is attributed to the gate stack properties, analyzed independently for N&P in the following part. Several techniques are used to extract oxide features: low field mobility (µ0) from the Y function [10], interface state density (Dit) from the Subthreshold Slope SS [11] and oxide trap volumetric density (Nt) from Low Frequency Noise measures (LFN) [12] at T=25°C. Bias Temperature Instability (BTI) at T=125°C is also characterized using a fast measurement technique [13].

NMOS devices - Fig. 5 a-c depicts the maximum low-field mobility (µ0), Dit and Nt. Higher Dit values are extracted on LT oxides. This results in an enhanced Coulomb scattering effect, degrading the mobility w.r.t HTO. The Pl-O2/H2 exhibit better mobility amongst the LT splits, explained by its lower D_it=2x10^-11/cm²/eV. The later also presents the lower Nt=3x10¹⁸eV/cm³; It may result from a better passivation of the dangling bonds by H⁰ incorporated during the

plasma oxidation step [14]. Concerning PDT efficiency, better surface passivation is achieved with a reactive plasma O₂ applied on Pl-O2+PEALD, while the effect is limited for the furnace N2 split.

Further improvement of the Si/SiO₂ interface can be achieved with a forming gas under High-Pressure Deuterium anneal (HPD2) [15].

Finally, PBTI is investigated (Fig. 5 d). PBTI in LT oxides are comparable, or even better for the Pl-O2/H2, w.r.t HTO. It also largely meets the 5 years requirement at V_DDmax=2.5V. Note that N_t and PBTI results are not correlated. This is because traps responsible for both phenomena are not same (Fig. 7). Noise is mainly sensitive to Dit while PBTI is due to trapping in a band of “deep” defects localized above the silicon conduction band.

PMOS devices - Fig. 6 b-c report Dit & Nt densities. Both are (1) much higher than for NMOS and the HTO and (2) almost independent of the LT oxide. This asymmetry between N&P implies that not only silicon dangling bonds contribute to Dit & Nt,, but also border traps (Fig. 7). D_it for PMOS actually refers to the sum of interface and border traps, and not to pure dangling bonds, with the method to extract Dit, from the SS not being able to separate the two contributions. Moreover, these Nt values are well correlated to NBTI results [Fig. 6 d)], suggesting that, this time, the defects responsible for noise & NBTI are the same. Comparing the oxides, the TTF for the best LT oxide Pl-O₂/H₂ is degraded by ~4 decades w.r.t. HTO.

Additionally, no improvement has been achieved with PDT. This confirms that NBTI remains a major issue for LT gate stacks [15-17].

NBTI was associated to traps located in the interlayer and high-k [17]. Despite the high-k suppression of our stack, NBTI remains problematic, which could be an indication that the traps are actually mainly located in the SiO₂.

Oxide traps on N&P devices - Three types of oxide traps have been identified: “deep”, border and interface traps (Fig. 7). For NMOS, the majority of active traps are interface/dangling bonds located in the bandgap, which affects mobility features. There are also some high energetic “deep” traps in the bulk of the SiO2, responsible for electron trapping upon high field PBTI stress. For PMOS, in addition to dangling bonds, border donor traps must be considered. They are located close to the Si/SiO2 interface (~1nm depth), and affect all the device characteristics such as SS, noise and NBTI.

Analog Figure of Merit - N&P gm/Id ratio of the HTO reference and the best LT split (Pl-O2/H2) are compared (Fig. 8). In the region below threshold (ID=1x10^-9A), gm/Id values in the range of 30V^-1 are found for both HTO and the LT device. Additionally, the same voltage gain is observed between long and short LG, offering a range of utilization for circuit designers. Similarly, no degradation is observed for the nominal gate length (LG=300nm) from the analog gain gm/gd (Fig. 9).

C

ONCLUSIONS

This work enable to conclude on the feasibility of stacking high voltage analog devices in a 3DSI for More-than-Moore applications.

Low-cost and low thermal budget 2.5V devices show good analog performance. Reliable NMOS devices were demonstrated, ideal for readout circuits with NFETs only. An identification of the defects present in LT SiO2 oxides is provided by means of complementary

electrical characterization.

Digital Analog Back side Sensor

3DSI 3DSI

SSI

Front side Sensor Analog

Digital

3DSI 3DSI SSI

Parallel Stacking

Oxide Type Post Deposition Treatment

Pl-O2/H2

Pl-O2 + PEALD

Pl-O2 + PEALD + 450°C Pl-O2

PEALD

PEALD ⁺ 500°C N2

1.6nm 4nm

6nm

10^-910^-810^-710^-610^-510^-410^-3 0

5 10 15 20 25 30 35

10^-910^-810^-710^-610^-510^-410^-3 0 5 10 15 20 25 30 35

gm/ID (V-1)

ld (A) LT Pl-O2/H2

HT Ref NMOS

L = 1µm L = 0.3µm

ld (A) PMOS

10^-910^-810^-710^-610^-510^-410^-3 0

5 10 15 20

10^-910^-810^-710^-610^-510^-410^-30 5 10 15 20 NMOS

LT Pl-O2/H2 HT Ref

Analog Gain gm/gd

I_ds (A)

LT Pl-O2/H2 HT Ref

I_ds (A) PMOS 0

100 200 300 400 500 600

+5%

NMOS

µ0 (cm2/Vs)

Oxide Split

+30%

Oxide Type Treatment Pl-O2/H2 Pl-O2 + PEALD Pl-O2 + PEALD + ^{450°C Pl-O}2 PEALD

PEALD + 500°C N2

HTO Ref

10¹⁰ 10¹¹ 10¹² 10¹³

HTO

+ 450°C Pl-O2 PEALD + 500°C N2

PEALD

Pl-O2 + PEALD

Pl-O2 + PEALD

Dit (/cm2/eV)

Oxide Split NMOS

Pl-O2/H2

10¹⁷ 10¹⁸ 10¹⁹ 10²⁰

10^-9 10^-7 10^-5 10-10

10-7

Exp Fit SId/Id2

I_d (A) Pl-O2/H2

Nt (eV/cm3)

Oxide Split NMOS

a) b) c) d)

^{2 4 6 8 10 12}

10^-5 10^-3 10^-1 10¹ 10³ 10⁵ 10⁷ 10⁹

NMOS Pl-O₂/H₂

BTI TimeTo Failure (s)

Oxide field (MV/cm)

5 years

max VDD

Si = 30nm Tox= 6nm Offset Spacer

Fig. 1 Schematics of digital/analog bilayer sensors interface module for sensing applications for a) Back side sensors and b) for above IC sensors. In both cases, analog devices have to be fabricated at LT. (SSI = smart sensor interfaces)

Fig. 2 TEM cross-section of the proposed analog FDSOI architecture. Tsi= 30nm/SiO2

= 6nm.

Fig. 3 a) Detailed process flow of HT and LT devices and b) summary of the LT oxide with its respective split name. Owing to the thicker SiO2, different oxide deposition are used in comparison to advanded digital devices. Post deposition treatments such as plasma densification and furnace anneal were also tested.

Fig. 4 ION/IOFF trade off of N&P devices for all LT oxide splits and HTO reference. L = 1µm VDD = 2.5V. ION shift between LT splits is attributed to the gate stack dielectric.

Fig. 5 a) Mobility peak µ0. b) Calculated interface state density. c) Bulk oxide trap density deduced from LFN measurements with the CNF/CMF model. Inset: fit of the normalized drain current noise SId/Id² with drain current Id. d) PBTI TimeToFailure vs Oxide field. All oxides fullfill the 5 years requirements (purple dashed line). ∆Vth of 50mV is used as criterion for BTI lifetime prediction. The grey square area represents the forbidden zone, where the criteria is not reached.

Fig. 6 a) Mobility peak µ0. b) Calculated interface state density. c) Bulk oxide trap density Nt d) NBTI TimeToFailure vs oxide field. Unlike NMOS, no significant differences between LT splits are seen on the mobility. Also, all splits present a larger amount of Dit and Nt and no improvement after PDT is oberved. The NBTI remains critical for all LT oxides - extrapolated 5y TTFs fall inside the forbidden zone.

Fig. 7 Summary of oxide traps impacting device performance and reliability. a) 3 types of traps are identified namely deep -/0, border +/0 and interface defects. b) PBTI in NMOS is driven by e^- trapping in high energetic defects c) NBTI in PMOS is controlled by the filling & creation of both Si dangling bonds and hole border traps.

REFERENCES: [1] L. Brunet et al., VLSI 2016. [2] P.

Coudrain et al., IEDM 2008. [3] P. Batude et al., IEDM 2017. [4] L. Brunet et al., IEDM 2018. [5]

C.-M. V. Lu et al., VLSI 2017. [6] L. Pasini et al., VLSI 2016. [7] A. Vandooren at al., IEDM 2018.

[8] C.-H. Shen et al., IEDM 2014. [9] M. Shulaker et al., IEDM 2014. [10] G. Ghibaudo, Elec Letters 1988. [11] J.P. Colinge et al., Solid-State Electron 1994. [12] G. Ghibaudo et al., PSS 1991. [13] X.

Garros et al., IEDM 2010. [14] X. Garros et al., IRPS IEEE 2005. [15] A. Tsiara et al., VLSI 2017.

[16] J. Franco et al., IEEE T-ED, 2013. [17] J.

Franco et al., IEDM 2018. ACKNOWLEDGMENT: This work has been partially supported by H2020 3DMUSE European project.

Fig. 8 N&P FETs gm/Id (Vd=0.9V) of HT & the best LT split Pl-O2/H2. (Lg= 1µm and Lg = 0.3µm).

Fig. 9 N&P FETs gm/gd versus Lg. The LT split Pl- O2/H2 is not degraded w.r.t to the HTO reference.

140 210 280 10^-13

10^-12 10^-11 10^-10 10^-9 10^-8

10^-7 Oxide Type Treatment

Pl-O2/H2 Pl-O2 + PEALD Pl-O2 + PEALD + 450°C Pl-O2 PEALD

PEALD + 500°C N2 HTO Ref

0 50 100 15010^-13 10^-12 10^-11 10^-10 10^-9 10^-8 10^-7

Ioff A/µm

Ion µA/µm NMOS

Ion µA/µm PMOS

2 4 6 8 10 12 10^-5

10^-3 10^-1 10¹ 10³ 10⁵ 10⁷ 10⁹

Pl-O₂/H₂

Oxide field (MV/cm)

BTI TimeTo Failure (s)

5 years PMOS

10¹⁷ 10¹⁸ 10¹⁹ 10²⁰

Nt (eV/cm3)

Oxide Split 0 PMOS

100 200 300

PMOS µ0 (cm2/Vs)

Oxide Split

Oxide Type Treatment Pl-O2/H2 Pl-O2 + PEALD Pl-O2 + PEALD + ^{450°C Pl-O}2 PEALD

PEALD + 500°C N2

HTO Ref

10¹⁰ 10¹¹ 10¹² 10¹³

PMOS

Dit (/cm2/eV)

Oxide Splits

Pl-O2/H2 Pl-O2 + PEALD Pl-O2 + PEALD PEALD PEALD+ 500°C N2

+ 450°C Pl-O2 HTO

a) b) c) d)

•STI HTO 1000°C

LDD implant LDD implant

Anneal 1000°C

HDD implant Spike 1047°C

LT HT Reference

• Plasma Oxidation 450°C

• Plasma Oxidation 400°C

• PEALD 200°C

• Plasma Densification 450°C

• Furnace anneal 500°C Gate stack 525°C

Offset Spacer 500°C 2h HDD implant SPER 500°C 30min Standard back-end

-4.0 0E

-00 9

-2.0 0E

-00 9

0.0 0E

+00 0

2.0 0E

-00 9

-10 0 10

Energy a.u.

A SiO² = 6nm Energy Level a.u. Dangling

bonds

metal SC

Ef

Deep traps 0

0 Border +

traps

xxxx Ev

Ec

a)

Vg=0V

-4.0 0E

-00 9

-2.0 0E

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0.0 0E

+00 0

2.0 0E

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-10 0 10

Energy a.u.

A

B C D

0 -

-

0

xxxx

NMOS b)

Vg=4V

-4.0 0E

-00 9

-3.0 0E

-00 9

-2.0 0E -00

9

-1.0 0E

-00 9

0.0 0E

+00 0

1.0 0E

-00 9

2.0 0E

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Energy a.u.

A

B C D

0

0^xxxx + Vg=-4V

PMOS c)