Power and area efficient MOSFET-C filter for very low frequency
applications
Armin Tajalli•Yusuf Leblebici
Received: 17 January 2011 / Revised: 21 March 2011 / Accepted: 1 April 2011 / Published online: 17 April 2011 Ó Springer Science+Business Media, LLC 2011
Abstract New circuit design techniques for implementing very high-valued resistors are presented, significantly improving power and area efficiency of analog front-end signal processing in ultra-low power biomedical systems. Ranging in value from few hundreds of MX to few hundreds of GX, the proposed floating resistors occupy a very small area, and produce accurately tunable characteristics. Using this approach, a low-pass MOSFET-C filter with tunable cutoff frequency (fC= 20 Hz–184 kHz) has been
imple-mented in a conventional 0.18 lm CMOS technology. Occupying 0.045 mm2/pole, the power consumption of this filter is 540 pW/Hz/pole with a measured IMFDR of 70 dB.
Keywords CMOS integrated circuits Continuous-time filter High-valued resistance Low-power
MOSFET-C filter Programmable filter Subthreshold Weak inversion Widely tunable circuits
1 Introduction
Analog front-end data acquisition and signal processing are critically important functions in modern biomedical sys-tems, such as in biopotential capture and neural recording
[1–4]. Figure1depicts a conceptual data acquisition chain for biomedical systems. Based on this topology, the bio-medical signals are converted to electrical signals by par-allel transducers; the electrical signals are then amplified by a low-noise amplifier. The next step will be to convert the analog signals to digital signals (analog-to-digital con-verter) after filtering to be further analyzed by the digital signal processors. Performance parameters such as linear-ity, gain and noise, as well as system specifications such as power dissipation and silicon area, are the main issues in design of analog front-end for this type of applications. Because of very limited energy budget in such battery operated or battery less systems [5], extremely power effi-cient circuit design techniques must be employed.
Depending on application, the bandwidth of input signal ranges from below 1 Hz to few kHz [6]. For example, signal bandwidth for Electroencephalography (EEG), Electrooculography (EOG), and Electrocardiography (ECG) applications are in the range of 0.5–40 Hz, DC to 10 Hz, and 0.05–100 Hz, respectively. Therefore, versatile amplification and filtering front-end circuits with very low operating frequencies are very desirable.
In [1], capacitance and transconductance scaling tech-niques have been introduced to implement a low-pass 2.4 Hz filter with 690 nW/Hz/pole power dissipation and 0.16 mm2/pole area in 1 lm CMOS. To generate a very large time constant, transconductance-transimpedance technique has been used in [2]. An integrator with a time constant of 0.2–10 s has been implemented in 0.8 lm CMOS, consuming 230 nW and occupying 0.1 mm2. To implement low bandwidth amplification stages, a very high-valued pseudoresistor has been introduced in [3]. In this pseudoresistor topology, each transistor which occu-pies 16 lm2, is biased in weak inversion to exhibit a very high resistivity. While highly nonlinear, it shows a
A. Tajalli (&) Y. Leblebici
Microelectronic Systems Laboratory (LSM), Ecole Polytechnic Fe´de´rale de Lausanne (EPFL), 1015 Lausanne, Switzerland e-mail: armin.tajalli@epfl.ch
Y. Leblebici
e-mail: yusuf.leblebici@epfl.ch Present Address:
A. Tajalli
Kandou Technologies Inc., 1015 Lausanne, Switzerland DOI 10.1007/s10470-011-9640-7
resistivity of as high as 1012X. To reach to the same range of resistivity, in [6] a pseudoresistance combined of NMOS and PMOS devices with better linearity perfor-mance has been suggested.
As can be seen, very high resistivity devices are critical components for implementing power and area efficient fil-ters at very low frequencies. In this article some techniques for implementing very high-valued resistors (HVRs) will be presented and used to realize a low frequency MOSFET-C filter [7,8]. Having a cutoff frequency of as low as 20 Hz, the proposed low-pass filter consumes only 540 pW/Hz/ pole and occupies 0.045 mm2/pole in 0.18 lm CMOS.
2 High-valued resistance
One of the main concerns in the design of very low fre-quency circuits is the size of passive components [9]. Large passive components can be very expensive in terms of silicon area. Meanwhile, when the size of a component increases, the parasitic elements associated with this device can affect the circuit performance. Therefore, compact and high-valued resistors are very desirable for implementing low-frequency filters. This Section explains step-by-step the topology of the proposed HVRs.
2.1 Basic HVR with extended swing
Triode MOS devices have been widely used in design of MOSFET-C filters [10] (Fig.2(a)). However, the resistivity of such devices is generally limited to few tens of MX with a reasonable area occupation. To implement compact and high-valued resistors especially for biomedical applica-tions, several techniques have been proposed in literature [3,6,11–14]. The technique that will be discussed here is based on a simple topology first used to implement logic circuits [15]. Using this technique, resistors with values as high as 20 GX based on small size devices have been fabricated and tested [7].
Previously, it has been demonstrated by the authors that connecting the bulk of a PMOS transistor to its drain will extend the resistivity range of device compared to the
conventional bulk-source connected configuration (Fig.2(b)) [7]. As shown in Fig.2(c), while the I/V char-acteristic of the conventional topology saturates for VSD
values larger than few UT(UTis the thermodynamic
volt-age), with the modified topology the resistivity range extends to few hundreds of mV. Ignoring the current of the forward bulk-source PN junction, the equivalent resistance of this topology can be calculated by
RSD¼ oISD oVSD 1 ¼npUT ISD e VSD=UT 1 ðnp 1ÞeVSD=UTþ 1 ð1Þ
which is obviously very non-linear (here, np is the
subthreshold slope factor of the PMOS device). However it can be shown that as long as the device is in subthreshold regime, the linearity remains fairly independent to the absolute value of resistance. Using Taylor expansion for (1): RSD¼ R0 e VSD UT np1 np R0 1 a VSD UT þa 2 VSD UT 2! ð2Þ where: a¼ np np 1 ð3Þ
indicates that the nonlinear part of the I/V characteristics depends only on VSD/UT, and hence the nonlinear
compo-nent remains the same for different values of bias current or (a) (c) (b) 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.0 0.2 0.4 0.6 0.8 1.0 1.2 VSD[V] ISD [µA] VSG= 0.3V VSG= 0.4V VSG= 0.5V Conventional PMOS load device (a)
Proposed PMOS load device (b)
Fig. 2 High-valued resistance for implementing subthreshold source-coupled logic [15] LNA Filter ADC DSP Transducer Biological Environment
VSG. Here, R0stands for the resistivity of the circuit when
VSD= 0 V. Based on (2), nonlinearity depends weakly on
the biasing condition only through np.
The other important aspect of the device shown in Fig.2(b) is that when the drain voltage of this component becomes larger than the source voltage, then the drain and source of the device will be exchanged and the bulk is connected to the source node. Therefore, the resistivity of the device will quickly switch from a very high value to a very low value similar to a PN junction. Depicted in Fig.3, based on measurement results in 0.18 lm CMOS, the device switches from subthreshold to strong inversion by changing the polarity of the source-drain voltage.
As far as the voltage swing across the resistor shown in 2(b) is less than 500 mV, the forward biased diode of the source-bulk junction draws very small amount of current and it has a negligible effect on the I/V characteristics, and power dissipation of the circuit.
2.2 Floating HVR
To compensate the asymmetric I/V characteristics of the simple devices discussed above, one can use two back-to-back equal-sized devices to implement a symmetric and floating pseudoresistor. The schematic of such a device is shown in Fig.4.
Regarding Fig.4, since the two transistors in series are not linear devices, VA= (VIN?? VIN-)/2. Using the EKV
model [16], it can be shown that:
VA ¼ V0 UTln cosh 2nDV pUTðnp 1Þ cosh DV 2npUT 0 @ 1 A ð4Þ
Therefore, VA depends on input voltage swing, DV. The
voltage at node VAexhibits a ‘‘V-shape’’ characteristic with
respect to DV. The minimum value occurs at DV¼ 0 V, and then increases by increasingj DV j. Knowing the value of DV, it is possible to calculate the current flow through MP1 and MP2: IR ¼ I0e V0VB npUTe DV 2npUT 1 e2UTDV cosh2nDV pUT cosh DV 2npUTðnp 1Þ 0 @ 1 A: ð5Þ Based on this, the circuit shown in Fig.4 achieves its maximum resistivity when DV¼ 0 V, and then the resis-tivity drops whenj DV j increases. If we generate VBfrom
VA, for example using a level shifter, then the linearity can
be improved. The reason is that when VA increases with
increasingj DV j as can be deduced from (4), the drop in resistivity will be canceled out partially by reduction of VSGof the PMOS devices. In this case, the maximum value
of the resistance will be no longer at j DV j¼ 0 V, but at two different points symmetrically placed with respect to the j DV j¼ 0 V.
Based on this discussion, it is possible to combine the two possible topologies to improve the linearity. For example, a series connection of the two circuits like the one shown in Fig. 5could be used to significantly improve the linearity. In this circuit, MN has been used to generate the gate voltage of MP1–MP2, VB, with respect to VAas a level
shifter circuit. Transistors MP1–MP2 are put in series to MP3–MP4 which are biased with a constant gate voltage. The resistivity of this circuit can be adjusted through the bias current of the level shifter circuit, IC. By increasing
this current, the source-gate voltage of MP1–MP2 increa-ses, and hence the resistivity decreases. Based on simula-tion results shown in Fig. 5, the nonlinearity of this pseudoresistance is about 7% for 2 V peak-to-peak voltage swing. Using more transistors in series with appropriate gate bias voltages can provide HVRs with better linearity performance within a still compact area.
2.3 Extremely high-valued resistance
The analysis and discussion provided in Sect.2.2is based on the assumption that the devices are biased in inversion mode where VSG 0. If we reduce the gate source voltage
-0.4 -0.2 0 0.2 0.4 VSD[V] -0.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 ISD [ µ A] High Resistivity region Low Resistivity region Measurement result for VSG = 0.4V VG VS VD
Fig. 3 Measured I/V characteristics of the device shown in
Fig.2(b) for positive and negative VSD
VIN+= V0+ΔV/2 IR MP1 MP2 VB VA VIN-= V0-ΔV/2
Fig. 4 Implementing floating HVR using two equal-sized
back-to-back bulk-drain shorted PMOS devices. VC= VA- VB can be
even further and make it negative, as shown in Fig.6(a), it is possible to implement extremely high valued resistors with a fairly good linearity performance. This figure shows the resistivity of the circuit for two different configurations. Monte Carlo simulations have been performed to study the resistivity variation in this topology. As it is shown in Fig.6(b), the resistivity variation based on MC = 100 simulations is only r = 2.2%. In the Monte Carlo simu-lation, mismatch and process variation for transistors is considered, while the supply voltage, temperature, and gate voltage of the devices are constant.
3 Tunable MOSFET-C filter design
Using the HVR topology introduced in Sect.2, it is pos-sible to implement very low frequency MOSFET-C filters. Wide tuning range associated with this HVR is especially interesting for implementing a versatile filter that can be used in different applications.
Figure7 proposes a first order MOSFET-C filter that uses a variable resistance for adjusting its cutoff frequency. Here, a widely tunable resistance and a high-gain and robust OTA (operational transconductance amplifier) with scalable power consumption are the main building blocks to implement a wide tuning range MOSFET-C filter. To
scale the circuit power consumption with respect to the filter cutoff frequency (fc), it is necessary to change the
power consumption of the amplifier (through IB,OP)
pro-portional to fc(or inversely proportional to R). The circuit
topologies introduced in Sect.2 can be used to implement the required resistance in Fig.7.
VDD MP1 M MP2 N IC VB VA VC=VA-VB VB(0) VB(0) VIN+ V IN-VB(0) = VBforΔVIN= 0V MP4 MP3 -0.5 -0.4 -0.3 -0.2 -0.1 0 0.1 0.2 0.3 0.4 0.5 2.8 3.0 3.2 3.4 3.6 VIN[V] 1/R [nA/V] -2 -1 0 1 2 IOU T [nA] (a) (b)
Fig. 5 a Modified HVR with improved linearity performance.
bSimulated I/V characteristics of the proposed HVR. This figure also shows the variation on absolute value of the HVR in different voltage drops (a) (b) -0.4 -0.2 0 0.2 0.4 350 400 450 500 VIN [V] Equi val ent R [G Ohm] 30 20 10 0.94 0.96 0.98 1 1.02 1.04 Normalized Resistance MC = 100 Occurance -0.4 -0.2 0 0.2 0.4 0.6 340 380 420 460 500 VIN [V] Equiv al ent R [G O hm] -0.6 T1 T2 For topology T1 0
Fig. 6 a Extremely high-valued compact resistor with a good
linearity performance. The equivalent resistance of both topologies are shown. b Variation on resistivity based on Monte Carlo Simulations (MC = 100). The Monte Carlo simulations are shown for the topology T1. Here, supply voltage and temperature are constant and a fixed voltage is applied to the gate of transistors
+ -AV VIN VOUT C IB,OP R Cutoff frequency/Power Tuning Signal
Fig. 7 Tunable active-RC (MOSFET-C) filter using a variable
resistor. The power consumption of the amplifier needs to be scalable with respect to the filter cutoff frequency
3.1 Amplifier design
In this work a two stage amplifier topology has been uti-lized. Assuming that the dominant pole is at the output of the first stage of amplifier, then the unity gain-bandwidth (UGBW) of the amplifier will be:
UGBW’ gm1=ð2pCCÞ ð6Þ
which is proportional to gm1(transconductance of the input
stage shown in Fig.8(a)), and inversely proportional to the compensation capacitance (CC). Assuming that the input
devices are in subthreshold regime, then:
UGBW’ ISS 2nUT
1
2pCC
ð7Þ
which is proportional to the bias current of the input stage of amplifier (ISS). Meanwhile, to have a phase margin of at
least 60° [17]:
fp;nd 3 UGBW ð8Þ
where, fp,ndis the non-dominant pole of the amplifier. The
value of fp,ndis inversely proportional to the load resistance
RL. RLis the equivalent load resistance of the amplifier and
as calculated in (1), it can be adjusted by the bias current. It is assumed that the output resistance of OTA itself is much larger than RL.
As illustrated in Fig.8(a), a two stage amplifier topol-ogy has been utilized for this purpose. To achieve a phase margin of at least 60°, based on (8) it is necessary to have: 1 3 CC CLþ CC gm1 GL : ð9Þ
Since the value of gm1 and GL= 1/RL are both
proportional to the bias current, by properly choosing the size of devices, the right hand side of (9) can be made bias current independent. Therefore, as long as the devices are in subthreshold regime, the stability of the circuit can be guaranteed. In this figure, RCis implemented using NMOS
devices to follow the variations of the bias current. Figure8(b) shows the simulated gain and phase margin of the proposed amplifier for different bias currents ranging over five orders of magnitude.
3.2 Dynamic range
The topology of the MOSFET-C filter shown in Fig.7 is well suited for implementing constant dynamic range (DR) and widely adjustable filters. This property is mainly due to the almost constant noise and linearity performance of the filter over its tuning range. The total input referred noise power of the filter shown in Fig.7 is:
v2n;in¼ cF ðk T=CÞ ð10Þ
in which cF indicates the circuit excess noise factor and
depends on the topology of the amplifier, resistances, as well as to the filter frequency transfer function (here, k is Boltzmann’s constant, T is the junction temperature in Kelvin, and C is the integration capacitance as shown in Fig.7). Regarding (10) and assuming that cFis bias
inde-pendent, then selecting a constant capacitor size results in constant total filter noise power for different cutoff frequencies.
On the other hand, based on (2) the linearity of the resistance introduced in Fig.4 is independent of the bias current or VSGand the dependence on VSDis the same for
different resistor values. Hence, as long as the devices are in subthreshold regime, the linearity performance of the resistance remains unchanged, as well.
4 Experimental results
Using the proposed floating resistor topology shown in Fig.5, a second order MOSFET-C filter has been imple-mented. The topology of the filter is illustrated in Fig.9. In (a) (b) VI+ V I-CC RC CC RC VDD VSS VBP VCMFB M1 M2 M4 M3 M6 M8 M7 M9 M5 V O-CL RL VO+ CL RL ISS= IC 10-11 10-10 10-9 10-8 10-7 10-6 100 105 1010 IC[A] GBW [Hz] 10-11 10-10 10-9 10-8 10-7 10-6 80 90 100 110 120 IC[A] Phase M argin [ o ]
Fig. 8 aCircuit schematic of the amplifier. b Simulated unity gain bandwidth (UGBW) and phase margin of the amplifier for different current bias values. In this plot, ICis the reference current value used
this configuration, the cutoff frequency and the quality factor (Q) of the filter can be tuned independently by adjusting the value of the appropriate resistors [10].
Simulations show that the cutoff frequency of the filter can be adjusted from 10 Hz to 200 kHz. The linearity performance of the filter remains almost constant as long as the devices are in subthreshold. For high bias currents, when the devices are entering into medium and strong inversion, linearity improves slightly. For low input frequencies (fin fc), the circuit transfer characteristic depends only on the ratio of resistors. Therefore, the nonlinearity of the resistors is not significant as long as they are well matched. For higher frequencies, when both capacitors and resistors are participating in constructing the output signal, then the nonlinearity of the resistors become important.
The chip photomicrograph of the filter is shown in Fig.10. The proposed filter occupies a silicon area of
420 lm 9 210 lm while using MiM capacitors. As shown in Fig.10, the area of the proposed floating resistors can be compared with the size of other components in the circuit.
4.1 Frequency response
The measured frequency response of the filter versus input frequency controlling current (IC) is shown in Fig.11(a). In
this measurement, the bias current of all the resistors as well as the bias current of amplifiers are scaling with respect to IC. Depicted in this figure, the controlling current
can be as low as IC= 100 pA for fC’ 20 Hz. This low cutoff frequency has been achieved using 2 pF filter capacitors. As a result, this topology shows to be very suitable for implementing very low frequency filters, using limited silicon area.
Figure11(b) demonstrates the tunability of this filter in comparison to the simulation results. The measured cutoff frequency of the filter is fC= 20 Hz–184 kHz which is
slightly less than five decades. This very wide tuning range corresponds to the adjustability range of the proposed floating resistor which is shown in Fig. 12based on mea-surement results. The measured frequency response shows a very good agreement with the simulation results. The small difference that can be seen between measurement and simulation results which is a relatively constant ratio over the entire range is mainly due to the difference between the capacitor values in the simulations and mea-surements. The difference between measurements and simulation results becomes more evident (about 50%) in very low cutoff frequencies mainly because of difficulty of precisely adjusting the controlling current. An internal current divider circuit has been employed to divide and external controlling current and produce the controlling current of the filter which loses its precision below 100 pA.
+ -+ -+ -+ -VI+ VO+ R1 R2 R3 R4 C1 C2 VI- V O-R1 R2 R3 R4 C1 C2
Fig. 9 A second order MOSFET-C filter. All resistors are imple-mented using the proposed floating resistor topology shown in Fig.4(a). Quality factor of this filter can be tuned through R2 independent to the cutoff frequency. In this design, R1 = R3 = R4
Fig. 10 Chip photomicrograph of the filter implemented with 0.18 lm CMOS technology (inset: implementation of the floating tunable resistors)
The normalized power consumption of the proposed sec-ond order filter is 1,080 pW/Hz.
Depicted in Fig.11(c), it is possible to adjust the Q of the filter independent to the cutoff frequency through changing R2 in Fig.9. Measured output phase of the pro-posed second order MOSFET-C filter shows that there is negligible variation on filter cutoff frequency when the quality factor of the filter is changing. On the other hand, based on Fig.11(a) changing the cutoff frequency does not change the quality factor of the filter.
As shown in [18] and [19], an on-chip phase-locked loop (PLL) based tuning system will be employed in the final design to control the bandwidth of the filter. Figure 12 illustrated the tunability of the HVR based on experimental data. The tunability of the HVR corresponds to the tun-ability of the filter as shown in Fig.11.
4.2 Dynamic range
Figure13 shows the measured third harmonic distortion (HD3 = H1/H3) of the filter at different cutoff frequencies
versus input signal amplitude. The cutoff frequency of the filter is adjusted with changing the controlling current as IC = 1 nA to 10 lA. For each cutoff frequency, the input
voltage swing is swept from -35 to 5 dBm. In each measurement, the frequency of the input signal has been selected to be four times smaller than the cutoff frequency of the filter. As can be seen, the linearity performance of the filter remains almost unchanged for the entire tuning range where the difference of the first and the third har-monics (H1/H3) are approximately 60 dB, and it can be maintained over four decades, for Ain= -20 dB (as the
gain of filter is one, Aout = -20 dB).
The measured input referred third intercept point (IIP3) and noise of this filter are shown in Fig.14(a)–(c). By changing the controlling current, IC, the cutoff frequency
has been changed, and in each point noise and IIP3 of the filter are measured. As expected, the total noise power remains fairly constant over the entire tuning range. The total integrated noise for this filter is in the range of (a) (b) (c) 101 102 103 104 105 106 -40 -20 0 Frequency [Hz] A m p litude [d B ] 10-12 10-10 10-8 10-6 10-4 100 102 104 106 Cutoff frequency [Hz]
IC, Controlling Current [A] Simulation results
Measurement results
Fig. 11 Measured MOSFET-C
filter characteristics: afrequency transfer characteristics. b cutoff frequency versus tuning current in comparison to the simulation results. c Q tuning by changing R2 value value at IC= 1 nA 10-1 100 VC[V] RSD (0) [Ohm] 104 105 106 107 108 109 1010 Weak Inversion Strong inversion Measurement
Fig. 12 Measured absolute value of the proposed floating resistance in different source-gate voltage values
-40 -35 -30 -25 -20 -15 -10 -5 0 5 10 -100 -80 -60 -40 -20 0 20 Ain [dBm]
First and Third Harmonics [dBm]
IC= 1nA IC= 10nA IC= 100nA IC= 100nA IC= 1uA IC= 10uA Mainharm onic(H1) Third h armonic (H3)
Fig. 13 Measured third harmonic for different cutoff frequencies. Cutoff frequency has been adjusted through controlling current, IC.
45–55 lVrmswhen the cutoff frequency is changing from
about 80 Hz to 184 kHz.
Meanwhile, as long as the devices in the proposed floating resistors are in subthreshold regime, the filter exhibits a constant IIP3. When the devices enter into strong inversion, IIP3 improves by increasing the controlling current. This behavior can be seen in measurements as depicted in Fig.14(b). The IIP3 of the filter is slightly less than 8 dBm for low cutoff frequencies and starts to increase for frequencies above 10 kHz and finally reaches to 14 dBm for fC = 100 kHz.
4.3 Comparison and figure of merit
Table1 summarizes the specifications of the filter. This filter consumes 540 pW/Hz/pole and occupies 0.045 mm2/ pole area. As the comparison in Table1shows, using high-valued resistors and avoiding less power efficient tech-niques such as transconductance scaling, or current divi-sion [1, 2, 20, 21] has resulted in much less normalized power dissipation. The figure of merit (FoM) that is achieved based on this definition [22]:
FOM¼ 10 log IMFDRlin: Cf Pdiss=ðN fcÞ
ð11Þ
is 202. Here, IMFDRlin. stands for intermodulation free
dynamic range, and Cf indicates the ratio of the maximum to minimum filter cutoff frequencies. Figure15 compares the figure of merit of this filter with some other already published reports [22–39]. The improvement observed for this design is mainly due to the simple topologies that have been used to implement the circuits. This approach also results in a very area and power efficient filter. As the comparison in Table1 shows, using high-valued resistors and avoiding less power efficient techniques such as transconductance scaling, or current division has resulted in much higher power efficiency.
(b) (c) 102 103 104 105 6 8 10 12 14 fc [Hz] IP3 [dBm] 101 102 103 104 105 45 50 55 N o ise [u Vrm s] fc [Hz] Toward strong inversion (a)
Fig. 14 Measured results: a spectrum of the output signal, b third order intermodulation intercept point, and c noise, of the proposed MOSFET-C filter. Here, the reference voltage is 50 X
Table 1 Specifications of the proposed filter in comparison to some other works
Parameter This work [1] [2]
VDD(V) 1.8 ±1.5 ±1.5 Technology 0.18 lm 0.8 lm 0.8 lm Order 2 6 1 fc,min(Hz) 20 2.4 0.016 fc,Max(Hz) 184 k 0.8 fc,Max/fc,min(Hz/Hz) 9,200 50
Normalized Pdiss(pW/Hz/pole) 540 694 9 103 287 9 103
Area (mm2) 0.09 1 0.1
Normalized area (mm2/pole) 0.045 0.17 0.1
Noise (lVrms) 50 50 IIP3 (dBm) 9 IMFDR (dB) 70 FOM 202 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 130 140 150 160 170 180 190 200 210 Area/Filter Order [mm2] FOM CMOS 0.18um CMOS 0.25um BiCMOS 0.29um CMOS 0.35um CMOS 0.5um CMOS 0.8um CMOS 1.0um CMOS 1.2um
BiCMOS SiGe 0.25um
BiCMOS SiGe 0.25um
This work (MOSFET-C) [Tajalli, gm-C, 2007] [Yang, 1996] [Yodprist, 2003] [ca st ello , 1999] [Chamla, 2005] [Mensink, 1997] [Zele, 1996] [Rao, 1999] [Pavan, 2000] [De Lima, 2001] [bollati, 2001] [Hori, 2003] [Hori, 2004] [Lo, 2007] [Chamla, 2005]
Fig. 15 FOM comparison to some other reports versus normalized
filter area (area is normalized to the order of each filter). The data points used in this figure are extracted from [22–39]
5 Conclusions
Novel circuit techniques for implementing very high-val-ued and compact pseudoresistors ranging from few hun-dreds of MX to few hunhun-dreds of GX, have been introduced and analyzed. Using the proposed high-value resistance, a very low frequency and power-efficient MOSFET-C filter has been implemented. Consuming 540 pW/Hz/pole, the power dissipation of this filter changes linearly with the cutoff frequency of the filter which can be tuned over 20 Hz–184 kHz. Very low power dissipation, and small area occupation (0.045 mm2/pole), as well as simple design process, make this filter very suitable for implantable, battery-less biomedical applications.
Acknowledgments The authors would like to thank S. Hauser for
preparing the test setup. This work has been supported in part by the Nano-Tera research program (ULP-Logic) funded by the Swiss Confederation.
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Armin Tajalli received the
B.Sc. and M.Sc. degrees (Hons.) in Electrical Engineering from Sharif University of Technol-ogy, Tehran, and Tehran Poly-technic University in 1997 and
1999, respectively, and the
Ph.D. degree from Swiss Fed-eral Institute of Technology (EPFL) in 2010. From 1998 to 2006 he was with Emad Semi-con as a Senior Analog Design Engineer. From 2010 he has been with Kandou Technologies
developing architectures and
circuits for very high-speed serial data transceivers. His research
interests include broadband data communication circuits, wireless transceivers, phase-locked loops and synthesizers, A/D and D/A converters, and design of ultra-low power integrated circuits. He has received the Kharazmi Award on Research and Development, 2000, Outstanding Design Engineer, Emad Semicon, 2001, Presidential Award of the best Iranian researchers, 2003, AMD/CICC Student Award, 2009, and EPFL Prime Special Award, 2009. Dr. Tajalli is a coauthor of Extreme Low-Power Mixed Signal IC Design: Sub-threshold Source-Coupled Circuits (Springer, 2010). He has served as a technical program committee member in IEEE International Con-ference on Computer Design (ICCD), 2010.
Yusuf Leblebici received his
B.Sc. and M.Sc. degrees in
Electrical Engineering from
Istanbul Technical University, in 1984 and in 1986, respec-tively, and his Ph.D. degree in Electrical and Computer Engi-neering from the University of Illinois at Urbana-Champaign (UIUC) in 1990. Between 1991 and 2001, he worked as a fac-ulty member at UIUC, at Istan-bul Technical University, and at Worcester Polytechnic Institute (WPI). In 2000–2001, he also served as the Microelectronics Program Coordinator at Sabanci University. Since 2002, Dr. Leblebici has been a Chair Professor at the Swiss Federal Institute of Technology in Lausanne (EPFL), and director of Microelectronic Systems Laboratory. His research inter-ests include design of high-speed CMOS digital and mixed-signal integrated circuits, computer-aided design of VLSI systems, intelli-gent sensor interfaces, modeling and simulation of semiconductor devices, and VLSI reliability analysis. He is the coauthor of 5 text-books, namely, Hot-Carrier Reliability of MOS VLSI Circuits (Kluwer Academic Publishers, 1993), CMOS Digital Integrated Cir-cuits: Analysis and Design (McGraw Hill, 1st Edition 1996, 2nd Edition 1998, 3rd Edition 2002), CMOS Multichannel Single-Chip Receivers for Multi-Gigabit Optical Data Communications (Springer, 2007), Fundamentals of High Frequency CMOS Analog Integrated Circuits (Cambridge University Press, 2009), and Extreme Low-Power Mixed Signal IC Design: Subthreshold Source-Coupled Cir-cuits (Springer, 2010), as well as more than 200 articles published in various journals and conferences. He has served as an Associate Editor of IEEE Transactions on Circuits and Systems (II), and IEEE Transactions on Very Large Scale Integrated (VLSI) Systems. He has also served as the general co-chair of the 2006 European Solid-State Circuits Conference, and the 2006 European Solid State Device Research Conference (ESSCIRC/ESSDERC). He has been elected as Distinguished Lecturer of the IEEE Circuits and Systems Society for 2010–2011.
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