The Story of Picosecond Ultrasonics

The Story of Picosecond Ultrasonics

From “Lab”… …to “Fab”

Rudolph MetaPULSE™

Outline

 Technology Transfer – 1996 to 1998

 MetaPULSE product innovations &

development

 Applications – Memory & Logic

 Would MetaPULSE have succeeded today?

 Summary

TECHNOLOGY TRANSFER

1996 - 1998

Timeline Overview

• 1984 – 1995: Brown University

– Picosecond ultrasonics discovered & developed by Maris & Tauc groups

• 1995: Rudolph licenses Brown IP

• Jan - Oct `96: “Alpha” prototype

– Opto-mechanical: stability, packaging

– Electronics: signal processing, control systems – Software: numerical algorithms, “recipes”

– Compact laser development: Coherent Vitesse

• Oct `96 - Dec `97: automated Beta tool

– 200mm wafer handling, machine vision, multi- site measurements, automated calibrations – Tool shipped to Intel May ‘97

• Jan `98: Commercial introduction

– 10 tools shipped in first year

– “Scientists in the Box” trained and included with

MEASUREMENT TIME

5 yrs (PhD) 2 yrs (MS)

5 min

30 sec

15 sec

+

Work hard!

Picosecond Ultrasonics Benefits

• Non-contact, non-destructive technique

• Multi-layer metal film thickness capability

• Small spot for product wafer measurements

– <10 mm spot fits in 30x30mm test sites

• Excellent throughput and repeatability

• Film/process characterization – Density, roughness, phase

Picosecond Ultrasonic Laser

t = 0

t = t1

Photocell

t = t2

PUMP

PROBE

Key success factors for MetaPULSE

Ultrafast Laser Technology Rapid Advances 1980’s – 90’s

Picosecond Ultrasonics

Semiconductor Industry Rapid Growth 1970’s – 90’s

Rob Stoner

More than

breakthrough

Mira Ti:sapphire (1W, ~0.3% noise)

Innova Ar+ pump

+

Ultrafast Laser Breakthroughs of 1990s

Satori (100mW, ~0.5% noise)

1990 1994

Antares

Modelocked YAG Flash lamp pumped

+

1997

Vitesse (300mW, 0.1% noise) Ti: sapphire + Nd:YV04 pump

Verdi pump laser

Semiconductor Industry: 1980s – present

$0.50 $3

 <5% growth

 Cost reductions

 Consolidations

$60

$35

$15

 15-20% annual growth

 Large R&D investment

 High IPO rate

 Entrepreneurial culture

Semiconductor Technology Drivers

Economies of Scale Productivity

Interconnect speed

“RC delay”

SOURCE: INTEL

20 FinFET

Cu interconnect, low-k ILED, and 300mm wafer automation

became requirements shortly after the introduction of MetaPULSE

METAPULSE PRODUCT EVOLUTION

MetaPULSE Development: 1997 - 2010

MP - XCu (400nm l for copper) MetaPULSE

(200mm &

300mm)

`98 `99 2004-07 2010

CAPABILITY / THROUGHPUT

`97

MP Beta tool (Intel 180nm node)

MetaPULSE-II MetaPULSE-III (Cu CMP &

low-k ILD’s)

MetaPULSE-G (green

wavelength)

SHG

>$300M total revenue,

~$50M total R&D spend

Optical Schematic - simplified

15 mm ® 1 psec 1psec ~ 30Å

Pulsed Laser

(~100 fsec, 800nm 80 MHz)

Lens Splitter

photocell

Wafer

time (psec)

D R

0 10 20 30 40 50 60 70 80 90 100

SHG (option)

Recipe-based

wavelength selection (use 400nm for Cu)

Servo Delay

< 0.1 mm repeatability (<10 fsec or <0.03 Å)

System stability – time zero calibration

time (psec)

D R

-1.5e-05 -1e-05 -5e-06 0 5e-06 1e-05 1.5e-05 2e-05 2.5e-05 3e-05

0 10 20 30 40 50 60 70 80 90 100

Thickness determination: (v

x t

)/2 = (60Å/psec x 26.2 psec) / 2 = 786Å

t

2t

3t

Thickness error estimate: D Thickness = 1/2 v

Dt

Let Dt

= 0.1 psec => D Thickness = (60 A/psec)(0.1 psec)/2 = 3Å

Dt_{ERROR 786 Å TiN}

Si

786 Å film -> 0.4%

60 Å film -> 5.0% !!!

Finetune Calibration Short Time Fit

-2.00E-06 0.00E+00 2.00E-06 4.00E-06 6.00E-06 8.00E-06 1.00E-05 1.20E-05 1.40E-05 1.60E-05

-2 -1 0 1 2 3 4 5 6

Time (psec)

Change in Reflected Probe (mW)

Time Zero “Finetune” Calibration

Reference Data Curve System Measurement Curve

RESULTS: T_offset = 3.7e-2 psec A_effective = 6.71e-6 cm²

T_OFFSET

Pump / probe overlap

Self check results - time zero stability (5 days)

System Time Offset [ps]

0.00 0.05 0.10

1/5 1/6 1/7 1/8 1/9 1/10 1/11

Trend: temperature &

alignment drift (selfcheck corrects)

Scatter: Algorithm repeatability

~ 0.005 psec => 0.015 A

Same “golden” reference file on all tools for thickness matching

Tool Matching Example

tool average wiw std dev 1 2 3 4 5

Tool 1 Mean 43.9696 1.81956 47.0686 42.6183 43.8191 43.3486 42.9933

Tool 1 Sdt Dev 0.24 0.18 0.29 0.43 0.39 0.42 0.55

Tool 1 P/T 0.072 0.055 0.088 0.128 0.117 0.127 0.164

PASS PASS PASS PASS PASS PASS

Tool 2 Mean 44.0882 1.93826 47.3170 42.5546 44.1080 43.4429 43.0182

Tool 2 Sdt Dev 0.16 0.28 0.39 0.45 0.45 0.39 0.68

Tool 2 P/T 0.047 0.083 0.116 0.134 0.135 0.116 0.204

-0.12 -0.25 0.06 -0.29 -0.09 -0.02

UCI -0.01 0.00 -0.07 0.29 -0.07 0.12 0.30

LCI -0.23 -0.24 -0.43 -0.17 -0.51 -0.31 -0.35

30 < N, T-statistic > 2.042 PASS PASS PASS PASS PASS PASS

2X30 Ti

tool average wiw std dev 1 2 3 4 5

Tool 2 Mean 59.1365 3.94404 52.6965 59.6553 59.3786 60.5675 63.3847

Tool 2 Sdt Dev 0.18 0.14 0.29 0.46 0.25 0.28 0.38

Tool 2 P/T 0.053 0.042 0.086 0.138 0.074 0.083 0.115

PASS PASS PASS PASS PASS PASS

Tool 1 Mean 58.5981 3.88157 52.2590 59.1085 58.7302 60.1849 62.7079

Tool 1 Sdt Dev 0.19 0.17 0.25 0.48 0.34 0.32 0.44

Tool 1 P/T 0.056 0.050 0.074 0.145 0.103 0.095 0.133

0.54 0.44 0.55 0.65 0.38 0.68

UCI 0.63 0.14 0.58 0.80 0.81 0.54 0.90

LCI 0.44 -0.02 0.30 0.30 0.49 0.23 0.46

2X30 TiN

LAYER 1: 40 Angstroms Ti

LAYER 2: 60 Angstroms TiN

10-20 tools matched at each process node (Intel)

0.12 Å mean matching

0.54 Å mean matching

Automation Platform Overview

System Computer Power Box

Electronics Box X- Lower Axis

Chuck

FAN FILTER UNIT

Load Port FOUP

Robot

Vibration Isolation

Y- Upper Axis Metrology Head Metrology Electronics

Robot Controller Automation Computer

Front End Module Metrology Platform

Airflow

SEMICONDUCTOR APPLICATIONS

Memory Application Examples:

MetaPULSE-I

(800nm wavelength)

DRAM Cell and Metallization

Word line

– Access transistor gate control(on/off)

Bit line

– Data transfer line. Read/write

Transistor

– NMOS transistor as a switch

Capacitor

– Data storage

Plug, Metal1, Metal2, …

– Metal interconnect to external world

1 Transistor 1 Capacitor cell (1X, 1Y)

CAP

DRAM structure & applications (circa 2000)

W Bit Line

W / CVD-TiN / Ti

BEOL Metalization

Al stack: TiN/Ti/AlCu/Ti

Word Line

WSix / poly-Si

W plug

W/ TiN/ Ti

W-deposition, W CMP

Al Bond Pad Al/TiAlx/TiN/Ti ILD & TiN etch

W Bit Line

W deposition process

100Å Pulsed nucleation seed

400Å CVD W

MetaPULSE measurement

Total W thickness ~ 500Å

Occasionally W thickness

becomes too thin causing

chip malfunction

W Barrier Metal (Ti/TiN)

Barrier for both Bit Line and Blanket W TiCl4 CVD process

TiCl₄ + 2H₂  Ti + 4HCl

6TiCl₄ + 8NH₃  6TiN + 24HCl + N₂ Better step coverage than PVD Total Thickness and density are monitored

High density result is predictive of high electrical resistance

Electrical Test Data MP Density Data

Barrier Metal – TiSix Thickness

Application: Monitor TiSix

thickness at the bottom of W plug Measurement on test site whose substrate is Si

MP measures TiN and TiSix thickness

0.3㎛

075

BPSG

TiSix

Plug-W

Via fill process for Metal 1 or Metal 2 Good step coverage but high electrical resistivity

Typically 3 - 4kÅ CVD W is deposited

W(CVD) has adhesion problem with SiO

.

– Barrier as glue layer

– At the edge where there is no barrier, W film lifts up causing particle problem

– Edge profile monitoring is important

0.3㎛ 075

0.3㎛ 075

0.3㎛ 075

W Plug depth This thickness is measured

Barrier Depo W Depo W Etch/CMP

W Edge Thickness Monitoring

3mm

Si Si

Optimized film edge profile

W W

W film at wafer edge may break off

Tungsten Edge Scan

0 500 1000 1500 2000 2500 3000 3500 4000 4500 5000

96 96.5 97 97.5 98 98.5 99 99.5

Radial distance (m m )

W thickness (Ang)

Aluminum “CAP” layers – TiN / Ti

Anti-Reflection Layer for metal 1

Semi-transparent layers =>

reflectance depends on thickness

Measure individual TiN and Ti thickness

Reflective surface below PR causes notches at the side profile.

Metal 2: 5000 Å Al/ 800 Å TiAlx

TiAlx is used to prevent electro- migration failures (voiding)

Deposition sequence: Ti(PVD)400  Al(CVD)500  Al(PVD)5500  Re- flow.

Re-flow (RTP) to fill up the voids in metal 2 plug.

During RTP, Ti turns into TiAlx with very rough interface.

Modeling “EASy” script categorizes

various case of TiAlx formation, and

model it appropriately.

Monitoring TiAlx Thickness

Unreacted Ti TiAlx formed

Metal Bond Pad

Passivation layer etch monitoring Wire bond failure scenarios

Thin Al pad (over-etched)

Residual CAP2 or ILD above Al

Al ETCH

Metal Pad Etch – Misprocessing detection

Modeling

“script” used to identify

filmstack and seed forward model

Copper Application Examples -

MetaPULSE-III

Copper applications overview

Previous metallization levels

Low-k ILD

Cu liner/

barrier Seed Cu

ECD Cu

Electoplate Copper

• Pre-CMP Cu thickness

• Cu overburden

Low-k

dielectric

• Elastic Modulus

Post-CMP

Residual barrier

Post-CMP dishing structure - Cu pad thickness

Seed Cu (PVD)

• Cu thickness

• Ta/TaN barrier

Post-CMP erosion structure - Cu Line Thickness

Seed Cu/Ta(N) measurements

Cu Thickness Map Ta(N) Thickness Map PULSE Signal

D R

Underlying levels (Level N-1)

Cu seed Ta(N) 400nm

wavelength

(Cu piezo-reflectance is zero at 800nm!)

“Fast Deflector” Technology for Low-k processes

• Challenge: Low-k Dielectrics have low thermal conductivity

• Solution: AOD rapid beam dithering

No fast deflector

(P ~2 mW) Fast Deflector

(P ~20 mW)

EFFECTIVE

“THERMAL”

SPOT SIZE Range:

~10 spots

F (t) = F0 + F1 cos(wt)

LASER SPOT SIZE

w / 2p ~ 1 MHz

~30 mm

AOD

Cu Seed/Barrier Measurements with Low-k ILD

65nm node

Ta+TaN Cu seed

45nm node 32nm node

Av.Cu thickness 600A 470A 200A

Electroplate Cu: Superfilling of narrow lines

1

2

1

2 1

2

On narrow line structures, MetaPULSE measures both

MetaPULSE Vs SEM Correlation

Superfill Profile Impacts CMP Results

+450 Avg -450

+150

Avg

-150

Overburden Thickness (Å)

Pre-CMP Array Thickness (Å)

Post-CMP Thickness Thickness (Å)

+170

Avg

-170

Normal

Non uniform as-deposited film affects Post-CMP line thickness

Position Sensitive Detector Enables Erosion Measurements

PSD benefit: surface displacement signals are less sensitive to submicron line

patterning 50 mm

test site

Spot covers ~50 Cu Line & space pairs

Correlation to device performance (65nm process)

M. H. Hsieh^a, J. H. Yeh^a, M. S. Tsai^a, C. L. Yang^a, J.

Tan^b, S. P. Leary^b

aUnited Microelectronics Corporation, Science- Based Park, Hsinchu, Taiwan

bRudolph Technologies, Flanders, NJ 07836

 CMP polishing profiles for thickness and 1/R are

highly correlated

 PULSE offers inline measurement with

excellent correlation to

final performance

Correlation to E-Test and TEM Results

 Very good correlation with TEM thickness results

 Excellent correlation

with 1/R electrical test

results

PULSE Modulus Measurement Principle

Time [ps]

DR/R [normalized]

Air/Dielectric interface

Dielectric/Si interface

Amplitude decreases

after Dielectric/Siinterface Interference oscillation

 Period of interference oscillation  speed of sound

 Reflection(s) at interface(s) ＆ speed of sound  thickness

 Amplitude change ＆ speed of sound  density

density  elastic modulus

Modulus Measurements of Different ILD Films

Poisson’s ratio:

Fixed input

MetaPULSE Trends – 2011 to present

WOULD METAPULSE HAVE

SUCCEEDED TODAY?

Semiconductor Industry Investment Trends

M. Noonen et al, Solid State Technology Magazine – July 2014

Investment challenges today for the next MetaPULSE

Ultrafast Laser Technology

Picosecond Ultrasonics

Semiconductor Industry Slow Growth

More than breakthrough

technology is

Summary

 Picosecond ultrasonics was a highly successful transfer from “lab to fab”

 The 1990s offered a prime opportunity for commercialization and funding

 Semiconductor investments have slowed but there are is still opportunity!

 Biotech & medical devices remain attractive for VC funding and may be a better target market

 Acknowledgements…

Rudolph Acknowledgments

• Rudolph Research

– Greg Wolf, Rob Loiterman, Richard Spanier

• Development / Engineering team

– Guray Tas*, Mike Colgan, Jim Onderko, Mike Kotelyanskii, Andrei Vertikov*

• Applications Scientists (in a box)

– Jonathan Cohen (US accounts including Intel) – Cheolkyu Kim* (Korea)

– Joerg Schmal (Germany)

– Niall McCusker (Seagate)