TECHNICAL INFORMATION

HP 13255

CONTROL ^MEMO~Y WI BANK SELECT MODULF.

Manual Part No. 13255-91221 REVISED

OCT-10-18

DATA TERMINAL

TECHNICAL INFORMATION

HEWLETT~PACKARD

Printed in U.S.A.

13255

Control Memory WI 8ank Select Module

13255-91221/02 Rev OCT-lO-78

1.0 I~TRODUCTION.

The control MemorY wI Bank Sel. Module provides 256 bytes of RAM and 32K bytes of FOM. The module communicates with the processor oyer a top plane bus. This allows the processor to operate at its maximum rate by ellm1nating the bus contention and handshake protocol Of the bottom plane bus.

The ROMs contain the operatinq firmware fOr the terminal. The RAM proVides for a fast access scratchpad for stack operations and program variables.

2.0 OPERATING PARAMETERS.

A summary of operating parameters for the Control Memory wI Bank Sel.

ModUle is contained in tables 1.0 through 5.1.

Table 1.0 Physical Parameters

====:===========================================================================

Part

Number Nomenclature

Size (L x W x 0) +1-0.100 Inches

I Weight I (Pounds)

=============,=====:===============::=======1========:==============1=========

02640-60'-21 02640-60216

Control Memory PCA

Prom Control Memory

peA

12.5

x

4.0

x

0.5 0.56 12.5

x

4.0

x

0.5 0.56

==============================================================================

Number of Backplane Slots Required: t

======================================================::::::::=:=:==:::::=:::=::

HP 13255

CONTROL MEMORY WI BANK SELECT MODULE Manual Part NO. 13255-91221

REVISED OCT-10-78

---.---~--- NOTICE

The information contained In this document is subject to change without notice.

HEWL~TT-PACKARD MAKES NO WARRANTy OF ^A~Y KJND WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Hewlett-pac~ard

shall not be liable for errOrs contained herein Or for incidental or consequential damaqes in connection with t~e furnishing, performance, or use

of

this material.

This document eontains proprietary information which Is protected by copyright. All rights are reserved. NO part of this document may be Photocopied or reproduced without the prior written consent of Hewlett- Packard Company.

---~~~---~-~-~----.---~---Copyright c 1976 by HEWLETT-PACKARD COMPANY

NOTE: This document is part of the 264XX DATA TERMINAL product series Technical Information Packaqe (HP 13255).

13255

Control Memory WI Bank Select Module

13255-91221/02 Rev OCT-I0-78

1.0 INTRODUCTION.

The Control Memory wI Bank Sel. Module provides 256 bytes of RAM and 32K bytes of FOM. The module communicates with the processor over a top plane bus. This allows the processor to operate at its maximum rate by elimInating the bus contention and handshake protocol Of the bottom plane bus.

- ,

The ROMs contain the operatinq firmware fOr the terminal. The RAM provides for a fast access scratchpad for stack operations and program variables.

2.0 OPERATING PARAMETERS.

A summary of operating parameters for the Control Memory wI Bank Sel.

Module is contained in tables 1.0 through 5.1.

Table 1.0 Physical Parameters

================================================================================

Part

Number Nomenclature

Size (L x W x 0) +1-0.100 Inches

I weight I (Pounds)

=============1=====:========================1=======================1=========

02640-60'-21 02640-60216

Control Memory PCA

Prom control Memory PC~

12.5 x 4.0 x 0.5 12.5

x

4.0

x

0.5

0.56 0.56

==============-================================================================

Number of Backplane Slots Required: t

==========:==========,======:=========================:::::::::=:====:::=:::::::=

13255

Control Memory WI Bank Select Module 13255-91221/03

Rev OCT-lO-78

Table 2.0 Reliability and Environmental Information

=====:=:========================================================================

Environmental: ( X ) HP Class B ⁽ ) Other:

Restrictions: Type tested at product level

==============================================================================

Failure Rate: .8132

3.424 (percent per 1000 hours) (with 16 ROMs loaded on peA)

====================================~================= ==========================

Table 3.0 Power Supply and Clock Requirements - Measured (At +/-5% Unless Otherwise Specified)

====================================================:===========================

+5 volt Supply

fa P30 rnA

+12 volt Supply

fa 830 rnA

-12 volt Supply rnA NOT APPLICABLE

+42 volt Supply mA NOT APPLICABLE

====================================== =======================================

115 volts ac 220 volts ac

A

NOT APPLICABLE NOT APPLICABLE

=================================:==============:=============================

Clock Frequency: MHz NOT APPLICABLE

================================================================================

13255

Control ~emory WI Bank Select Module 13255-91221/04

Rev OCT-IO-78 Table 4.0 Switch Definitions

================================================================================

PCA Designation

Function

I---~---~---~-~--~~---~---I

_{CLOSE OPEN}

================

===~========================== ~--~-~---~---~~~--~~­---~~---~----~---~---

ROM OISAS (0,2,4, ••• ,30)

--

BS

-.

DR

---

A15

SSE

ORE

RAM DIS

LOW P~M

The corresponding 2K block of ROM is enabled.

Respond to BANK SF.L. line equa 1 to a ' 0' •

Respond to DlSS. ROM line equal to a '0'.

Respond to AODR15 line eQual to a '0'.

Enables BANK SEL. line.

Enables DISB. ROM line.

The RAM is disabled

The RAM start address is equal to the '36K' switch.

The corresDondinq 2K bloCK of ^ROM is disabled.

Respond to BANK SEL. line equal to a '1'.

Respond to DISB.ROM line equal to a 'I'.

Respont to ADoPtS equal to a 'I'.

Disahles RANK SEL. line.

Disables OISB. ROM line.

The RAM is enabled •

The RAM start address is equal to the '36K' switCh plus 256(declmal).

=============================:s=================================================

13255

Control Memory WI Bank Select Module 13255-91221/05

Rev OCT-IO-78

Table 4.0 Switch Definit10ns (continued)

========================================~============= ====a====================:

Function PCA

Designat10n --~----~---.~---~---~---~--- ---CLOSE

================ ==============================

36K The start address of the RAM is equal to 36K •

SLOW ROM or PROM memory .cycles are slower (SOO ns.) •

W1 Connects pin 21 of socket to AIO. This jumper must be in- stalled to use ROMS ..

W2 Connects pin 21 of socket to VCC. This jumper must be in- stalled to use PROMS.

W3 Connects pin 19 of socket to AIO This jumper must be installed to use PROMS.

W4 Connects pin 19 of socket to +12 volts. This jumper must installed to use ROMS.

OPEN

=========:=================~==

The start address of the RAM Is equal to 62K + 512 ,

ROM or PROM memory cycles are normal (400 ns.) •

Disconnects pin 21 from AIO. Jumper must be removed to use PROMS.

Disconnects pin 21 from VCC. Jumper must be removed to use ROMS.

Disconnects pin 19 from AIO. Jumper must be re- moved to use ROMS.

Disconnects pin 19 from

+12 volts. Jumper must be removed to use PROMS.

========================================~============= ===================,=======

13255

Control Memory WI Rank select Module

13255-91221/06 Rev OCT-tO-7S

5.0 Connector Information

================================================================================

Connector and Pin NO.

==============

Pt., Pin 1 -2 Pin -3 through

Pin -22

Signal Name

--~~--~--~-~-~~- --~---~~-

+5V GND

Signal Description

==============================================

+5 Volt Power Supply

Ground Common Return (Power and Signal)

}

} Not Used

}

--~---~--- ---~--- --.---~-~---~--- PI, Pin -~

-8

-C Pin -0 through

Pin -5 -T -U Pin

-v

thro\lgh Pin

-z

GND

+12V

PRIOR IN PRIOR OUT

Ground Common Return (power and Si~nal)

Not Used

+12 Volt power Supply

}

} Not Used

}

Bus Controller Priority In Bus Controller Priority out

}

} Not Used

}

======================================================:::=:=:=:::=::=:::::=:=:=:

13255

Control Memory WI Bank Select Module

13255-91'221/07 Rev OCT-t 0-7.8 Table 5.1 Connector InformatIon

=============~====================================:=== =========================c

Connector and PIn NO.

==============

P3, Pin 1 - 2 - 3 - 4 - 5

- 6 - 7 - 8 - 9 -10 -11

-12

-1 :3

-14 -15 -16 -17

-19 -20 -21 -22

SIgnal Name

================

GNO

ADoRO ADDRl ADDR2 ADoR3 AODR4 ADOR5 ADOR6 ADOR7 ADoRB ADDR9 ADDRI0 ADDR11 ADOR12 ADDR13 ADDR14 ADDR15 TOP ACTIVE

READ WRITE SYNC.PHASE1

GND

slqnal Descr1.ption

:::::=::=:::=::s==:=::==:::===:::=::=====::=:=

Ground

Addr~ss BIt 0 Address BIt 1 Address 8it 2 Address BIt 3 Address Bit 4 Address Bit 5 Address BIt 6 Address Bit 7 Address Bit 8 Address Bit 9 Address Bit 10 Address Bit 11 Address Bit 12

·Address Bit 13 Address BIt 14 Address BIt 15

Negative True, (Low) Indicates TOp Plane Module Address RecognItion. (High Causes a Bottom Plane Bus Cycle)

High Indicates TOp Plane Bus Data Should Be Gated On

Hioh Indicates TOp Plane Bus Data is Valid High indicates beginnIng of a memory cycle Ground

================================================================================

13255

Control Memory WI Bank Select Module

13255-91221/08 Rev OCT-I0-78

Table 5.1 connector Information (Cont-d.)

================================================================================

Connector I SiQnal and Pin NO. I Name

-- ^... - ^... - ^... ---

^{.... ~} ~---~---~~

--- ---

P3, Pin A GND

-8 DRITO

-C DBIT1

-0 DRIT~

-F DRIT3

-F OBIT4

-H OBITS

-,-l DB1T6

-K ^D~IT7

Pin, -L

PIn -M BANK SEL.

Pin -N

-p lIn

Pin -R ^SYNC

Pin _-~

-T

wn

-u

^{DISABLE ROM}

-v

-w

-X MEMR

-y

-z

^GNO

SiQl'1al Description

=============::===============================

}

Ground Data Bit 0

Data. Bit 1 Data Bit 2 Data Bit 3 Data Bit 4 Data Bit 5 Data Bit 6 Data Bit 7 Not Used

Bank select ,bit, used lik~ annother address line.

Not Used

Neqative True, (Low) Indicates (AtS A14 A13 A12)

=

(1000)

Sync signal from the processor (8080A-2)

"Jot Used

High Indicates Write or Output Cycle Used as annother bank select b i t .

} Not Used

}

Hiah Indicates Current Cycle Is a Memory Pead

~ot Used Ground

-~~---~---~---~---~-~---~---~---~~---~-~--- ----~---~---~--- ---

13255

Control Memory WI Bank Select Module

13255-91221/09 Rev OCT-I0-78

3.0 FUNCTIONAL DESCRIPTION. Refer to the block diagram (figure 1), schematic diagram (figure 2), timing diagram (figure 3), component location diagram (figure 4), and ~arts list (02640-60221) located

3.1

3.1.2

3.1.3

in the append~X. The 02640-60216 PROM control Memory PCA uses the same block, timinq, and component lOcation diagrams and parts list.

The control MemOry wI Bank Sel. Module provides proqram.storage in Read Only Memory (ROM) fOr the Processor (80ROA-2) Module which controls the functIons of the terminal. VIa its communication over a too plane bUS,

this module permits t~e processor to operate without any wait states during Instruction fetch and stac~ operations. The blOCK diagram shows the functional confIguration of the module.

PROMS may be used instead of the ROMS bv strapinq the board as listed in table 4.0. The mixing of PRO~S and ROMS is not nossible on the same peA.

DATA AND ADDRESS DRIVER LOGIC •

The data drivers are bidirectional buffers which present minimum load- ing to the CPU and synchronize the movement of data along a bidirec- tional bus on the PCA. The drivers are enabled only when the control logic determines that data is required at the CPU or at the local RAM.

There is one set of drivers for transferring information from the PCA to the Cpry and another for brinoing data from the CPU to the local RAM.

Data on the top plane bus (P3 connector)

Is

applied to the inputs Of U24 and U34, and driven onto the internal bidirectional data bus (DO throuQh 07). Data from the ROMs (16-2K by 8 bits) is driven onto this same internal bidirectional bus. Address infor-

mation 15 buffered on the processor (8080A-2) PCA, driven onto the top plane bUS, and then through U25,U35 & U44 to th~ ROM and RAM input pins.

The least significant 11 address lines distribute address infor-

mation throughout the ROM a"d RAM arrays. The highest order bits are examined by exclusive NOR gates to determin@ whether or not the peA is being addressed.

13255

Control Memory WI Bank Select Module

13255-91221/10 Rev OCT-IO-78

3.2

3.2.1

3.2.2

3.3

3.3.1

ROM OR PROM ARRAY AND RAM MEMORY.

The Control Memory PCA is designed to work with the Advanced Micro Devices 16K ROM (part number AM9216BDC), Which can be ordered with two programmable chip selects. In order to function proP,rly in this PCA, both orogrammable chip selects must be specified to be active low.

The ROM chips are mask orogrammed, 400 nanoseconds access time, 16K bits orqanized as 2K by 8 bits. The use of PRO~S (2K by 8

hits) may be used instead of ROMS by changinq the straps wt-W4 (Intel 2716 or TI ?516JL).

The speed of these parts is less than the ROMS , therefore , the SLOW switch should be closed (see tabl.e 4.0).

The PAM c~ips are N-channel MOS whiCh contain tK bits that are organized as 256 by 4 bits.

RAM ENABLF LOGIC •

The 256-byte RAM is made up of two 256 by 4 static N-channel mos chips.

An 8-bit comparator determines when the RAM block Is beinq addresssed.

The constant being applied to the comparator is set as per the description of the switCh. settings (see table 4.0) •

When the comparator recognizes the address applied to it , the RAMS are enabled and the ROMs are disabled • The comparator loqic also returns a TOP ACTIVE sianal thrOuqh the TOP ACTIVE logic.

The CPU provides all the set up and hold times reauired ^bv the memory chios • . Fiqure 3 shows the read and write timing r~lationships. The WO signal is used to disable the RJM outputs and to direct data trom the processor to the RAMs. The WRITE pulse causes the RA~s to memorize the current state of the data lines and store that information at the loca- tion addressed by the address lines.

13255

Control Memory WI Bank Select Module

13255-91221/11 Rev OCT-tO-78

3.4 3.4.1

3.4.3

3.5 3.5.1

3.5.2

ROM OR PROM ENABLE AND BA~K SELECT LOGIC •

Each of the 2K ROM Chips may be individually disabled. This feature permits sUbs~ltutlon of specialized firmware for specIfIc applications witnout requiring a complete new set of mask programmed ROMs. If a 2K ROM is de-sel@cted, the ROM ENABLE logic will not return a negative TOP ACTIVE signal when an access Is made to that 2K block.

It is possible with a PRO~ PCA for a PROM to resIde in the same address SDace as the disabled ROM, thus the substitution is accomplished.

The BANK SELECT LOGIC allows the placement of the 32K FOM array at 1 of 8 32K bloCKS • The block Is selected by lines A15 , DIS ROM , and BANK SELECT uselnq switches At5 , DR , B.S. , SSE , and ORE as descrIbed In table 4.0 •

The output of the 2K deeoders (U21 and U22 ) is NANO'ed with the BANK SELECT and READ logic (described in section 3.5 ) to enable the appropriate colUmn of ROMs • The fllp-tlOP ( U52 ) is used by th~

the row select decoder ( U45 ) to ensure that one ROM is off before annother ROM Is selected •

TOP ACTIVE , SLOW AND READ LOGIC •

The TOP ACTIVE LOGIC recieves enable signals from ROM and RAM enable logic and returns a negitlve true TOP ACTIVE sIgnal to the processor ( 8080A-2 ) PCA •

The READ LOGIC examines the status from the processor ( 80S0A-2 ) PCA to determine if the cycle Is gOing to be a read.

ThiS allows the TOP ACTIVE LOGIC to return a TOP ACTIVE signal In time to prevent a bottom plane memory CYCle •

The SLOW logic when enabled, allows slower parts to be used in the board. This slower memory cycle is 500 instead of 400ns.

13255

C~ntrol Memory WI Ba~k Select "Module 13255-9.Nn/12 Rev OCT-1 0,-78

4.0 4.0.1

4.0.2

4.0.3

TIMING CONSIDERATIONS.

The 8080A-2 ProcessOr is driven by a ClOCK which has a basic period of 400 nanoseconds. There are two clock signals which drive the CPU and are generated on the Processor (8080A-2) peA. These ClOCK signals govern the timing of addresses eominQ from th~ CPU and determine the set up times required for information that is returned from the memory to the processor. The timing diagram (figure 3), showS the timing for PHASEt and PHASE2 and the resultant access time that is availabe at the pins of the CPU.

Addresses become valid at the pins of the processor a maximum of 195 nanoseconds after the rising edge of PHASE2. Data must be valid at the processor 145 nanos~conds before the leadina edge of the 12 PHASE2. The time required from output of the address until the data must be valid at the CPU is 457 nanoseconds.

The time reouired to return the TOP ACTIVE signal is also shown in figure 3 • the TOP ACTIVE siqnal prevents a bottom plane memory cycle • The timinq required for the return Of this signal Is

105 nanoseconds.

Co .... trol

L"ut'lO '3

D .. ta

D!IIT_-7

t _Drl~e'5

~----~---~«_+---,~.~---~---4---~~~ ~~ o~t

'tl

-

Rom

A RR RY

s

(AfJ-Ai)

Leol.

1

r---t---~---~---+---~l SeleL~

(IW',','I) J

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,- - -,

'- - - -!

r'1u""<JI~,.it 0-0 ~o ....

"~IC.

(,," .1I1'f) L.----+---___ ....t]

'n---_--4---I'

^{1 - - - - -}

~-~J~-/~ ~~~:---4 _{I ...}

trOth EIllIt"c..f l...--_ _ _ _ _ ^{- - J}

1-06-/(.... I

=r~o..,..,..."/IC...,.,n.,,..,-r I

- - - - I

E.,,,iva/eNt

Figure 1

Control Memory Block Diagram OCT-10-78 13255-91221

P3-T

P3-1S P3-- C ' 1 -D

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ToP JIIC.TIVE 1-'3-1 g

Control Memory peA Schematic Diaqram

OCT-tO-7S 13255-91221

I

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Figure 3

Control Memory Timing Diagram OCT-10-78 13255-91221

Figure 4

control Memory PCA Component Location Diagram

OCT-I0-7S 13255-91221

02640-60216 32K CONTROL MEMORY C-1835-42

I

^SW1

II

^SW2

II

^SW3

Ie

iRl I iR2 I

®

I

^U21

5 ill ^I

^U22

5

^U23

5

B®B ^{I U335®1}

iR3 I

B ^{B@I U435 I}

U52

5

U24

U34

U44

C15

5

^{~ ~ IR.}

^I

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iR5

5 I

^U35

5 ~1U45

iR6

G ^[:]®[:]

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5 I

^U26

L:]®[:]@[:]

5 ~I

^U36

S

5 I

^XU46

@L:]@c:J B

L:] c:J@[=::J

Figure 5

Control Memory PCA Components Locat1on Diagram

OCT-IO-78 13255-91221

Replaceable Parts Reference HP Part

Qty Description Mfr Mfr Part Number

Designation Number Code

02640-60221 1 32K B/s CONTROL MEMORY DATE CODE: C - 1835 - 42

C1, C2 0160-2055 21 CAPACITOR .01UF +80

C3 0150-0121 4 CAPACI TOR O. 1UF

C4,5,6,7,8 0160-2055 CAPACITOR .01UF +80

C9, C10 0150-0121 CAPACITOR O.lUF

C11,12,13,14,15, 0160-2055 CAPACITOR .01UF +80

C16, c17 0160-2055 CAPACITOR .01UF +80

C18 0180-0393 1 CAPACITOR 39UF 10V

C19 0180-1746 1 CAPACITOR 15UF 10% 20V

C20 0150-0121 CAPACITOR O.lUF

C21,22,23,24,25 0160-2055 CAPACITOR .01UF +80

C26, C27 0160-2055 CAPACITOR .01UF +80

R1, R2 1810-0279 2 NETWORK-RESISTOR SIP

R3 1810-0121 1 RESISTOR NETWORK 8X1K

R4,5,6 1810-0350 3 NETWORK-RESISTOR

SW1, SW2 3101-1983 2 SWITCH-TOGGLE 8-1A NS

SW3 3101-2102 1 SWITCH ROCKER

U21, u22 1820-1302 2 IC SN74S251N

U23 1820-1297 3 IC SN74LS266N

U24 1820-1828 2 IC DIGITAL SIG 8T28

U25 1820-1049 3 IC DM80 97N

U26 1818-0197 2 IC AM91L11BDC

U31 1820-0685 1 IC SN75S10N

U32 1820-1197 1 IC SN74LSOON

U33 1820-1297 IC SN74LS266N

U34 1820-1828 IC DIGITAL SIG 8T28

U35 1820-1049 IC DM80 97N

U36 1818-0197 IC AM91L11BDC

U41 1820-1209 1 IC SN74LS38N

U42 1820-1199 1 IC SN74LS04N

U43 1820-1297 IC SN74LS266N

U44 1820-1049 IC DMBO 97N

U45 1820-1281 1 IC 74LS139

U52 1820-1212 1 IC SN74LS112N

XU17-19, 27-29 1200-0541 16 SOCKET 24 PIN 37-39, 46-49

57-59

0360-0124 1 STUD SOLDER TERMINAL

1200-0614 1 SOCKET IC

8159-0005 2 WIRE JUMPERS

Replaceable Parts

Reference HP Part _Oty Description Mfr Mfr Part Number

Designation Number Code

02640-60216 1 32K PROM CONTROL MEMORY DATE CODE: C - ¹⁸³⁵ - ⁴²

C1, C2 0160-2055 14 CAPACITOR .01UF +80

C3 0150-0121 4 CAPACITOR O.lUF

C4,5,6 0160-2055 CAPACITOR .01UF +80

C7, C8 0150-0121 CAPACITOR O.lUF

C9,10,11,12,13 0160-2055 CAPACITOR .01UF +80

C14 0180-0393 1 CAPACITOR 39UF 10V

CIS 0180-1746 1 CAPACITOR 15UF 10% 20v

C16 0150-0121 CAPACI TOR O. lUF

C17,18,19,20 0160-2055 CAPACITOR .01UF +80

R1, R2 1810-0279 2 NETWORK-RESISTOR SIP

R3 1810-0121 1 RESISTOR NETWORK 8X1K

R4,5,6 1810-0350 3 NETWORK-RESISTOR

SW1, SW2 3101-1983 2 SWITCH-TOGGLE 8-lA NS

SW3 3101-2102 1 SWITCH-ROCKER

u21, U22 1820-1302 2 IC SN74S251N

U23 1820-1297 3 IC SN74LS266N

U24 1820-1828 2 IC DIGITAL SIG 8T28

U25 1820-1049 3 IC DM80 97N

U26 1818-0197 2 IC AM91LllBDC

U31 1820-0685 1 IC SN75S10N

U32 1820-1197 1 IC SN74LSOON

U33 1820-1297 IC SN74LS266N

U34 1820-1828 IC DIGITAL SIG 8T28

U35 1820-1049 IC DM80 97N

U36 1818-0197 IC AM91L11BDC

U41 1820-1209 1 IC SN74LS38N

U42 1820-1199 1 IC SN74LS04N

U43 1820-1297 IC SN74LS266N

U44 1820-1049 IC rlM80 97N

U45 1820-1281 1 IC 74LS139

U52 1820-1212 1 IC SN74LS112N

XU17-19, 27-29 1200-0541 16 SOCKET 24 PIN 37-39, 46-49

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0360-0124 1 STUD SOLDER TERMINAL

1200-0614 1 SOCKET IC

8159-0005 2 WIRE JUMPERS

See introduction to this section for ordering information

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