System/360 Model 50 2050 Processing Unit

System/360 Model 50 2050 Processing Unit

dr) ^g 5 ~ Field Engineering

Maintenance Manual

SY22-2832-4

PREFACE

To obtain the most benefit from this manual. the reader fhould have a basic knowledge of System/360 concepts and general programming. and a working knowledge of the logical and physical operation of the 2050 Processing Unit. The manual includes diagnostic aids ^t maintenance features ^I and maintenance pro- cedures along with reference material that will aid in troubleshooting and maintaining the System/360 Model 50.

Other Field Engineering Manuals written for the System/360 Model 50 include:

Comprehensive I:atroduction, FETOM Functional Units, FETOM

Capacitor Read-Only Storage, FETOM RR, RX Instructiops, . FETOM RS, SI, SS Instructions, FETOM

Selector Channel, Common Channel, FETOM Multiplexor Channel, FETOM

Main Storage, Local Storage., Storage Protection, FETOM

Power Distribution and Control, FETOM Features, FETOM

2050 Procestling Unit, FEMDM 2050 Processing Uni t, FEIM

Fifth Edition (March 19i1l

SY22-2B21 SY22-2B22 SY22-2B23 SY22-2B24 SY22-2B25 SY22-2B26 SY22-2B27 SY22-282B SY22-2B29 SY22-2B30 SY22-2B33 SY22-9501

This is a major revision of, and obsoletes, SY22-2B32-3. Maintenance strategy diagrams have been revised, expanded, and placed in the 2050 FEMDM. All CPU timing information has been removed from this manual and placed in the ALD's, Volume 1, Page AAOOO. Other changes or additions to text and illUltrations are indicated by a vertical line to the left of the chang~.

Changes are periodically made to the specifications hereinj any such changes will be reported in subsequent revisions or FE Supplements.

This manual has been prepared by the IBM Systems Development Division, Product Publications, Dept. 896, PO Box 390, Poughkeepsie, N. Y. 12602. A form is pro- vided at the back of this publication for reader's comments. If the form has been removed, comments may be sent to the above address.

© Copyright International Business Machine. Corporation 1966

DIAGNOSTIC TECHNIQUES.

Maintenance Philosophy.

Failure Detection . Deferred Maintenance Troubleshooting F10wcharts .

Power Faults Loading Faults .

Programming Faults and Error Stops • Other Maintenance Documentation

Error Check Analysis Diagrams.

Service Aids.

ALD Page Key .

CAS Logic Diagram Page Key.

Optional Feature Version Codes Diagnostic Mode Codes • Selector Channel Error Handling .

Interface Control Check.

Channel Control Check--Channel Detected Channel Control Check--CPU Detected.

Program, Storage-Protect, and Chaining Check Data Check.

SIM Check.

Incorrect Length Indication (IU) Error Priority.

MAINTENANCE FEATURES.

CPU Control Modes Sequence Counter Mode.

Main Store Mode . ROS Mode . FUNCTIONAL UNITS.

Sequence Counter.

Sequence Sta1:s • FLT Op Reg.

Scan/Log Decoder ROS Kernels Log Trigger.

Supervisory Stat Progressive Scan Stat.

Supervisory Enable Storage Stat Binary Trigger •

Scan Test Counter Pass/Fail Triggers.

SUPERVISORY CONTROLS.

Clock Gating Control Circuits • CPU Control Status .Circuits.

Changing CPU Control Status Supervisory Interrupts.

LINKAGE CONTROL WORD.

DIAGNOSE INSTRUCTION • FAULT LOCATING TESTS (FL T's) FLT Load

Load from Tape Load from Disk.

Unsuccessful Load •

Completion of Successful Load.

Main Store Mode FL T's • MS Mode Hardcore Tests

.11 11 .11 .11 11 12 12

· 12

• 12

• 12

• 12

• 12 .13

13 .13 15 15 15 15 15 16 16 16 17 18 18 18 20 20 21 21 21 21 21 21 32 32 32 32 32 32 32 35 35 35 35 35 40 40 41 42 42 45 45 45 45 46

FL T Load Checking Program

Test Methods (Mask and Expected Response) MS Mode ROS Bit Tests •

ROS Mode FL T's •

ROS Mode Hardcore Tests ROS Mode Zero/One-Cycle Tests Zero/One-Cycle Test Methods.

FL T Operating/Repair Procedures Main Storage Ripple Test • Skipping Bad FL T Records • Disk (FL T) Operating Procedures • Cycle Test Repair Procedures (Tape/Disk) Checkout After Repair

FL T Documentation . PROGRESSIVE SCAN.

Test Descriptions • Test Patterns

Selector Channel Tape or Disk Selector Channel Clock Control

Selector Channel Operating Procedure Example Selector Channel Test Documentation Selector Scan Monitor

Multiplexor Channel Tape or Disk Multiplexor Channel Operating Procedure Multiplexor Channel Test Documentation • DIAGNOSTIC PROGRAMS •

MIDAS Sense Switches MIDAS Display Codes MARGINAL CHECKING.

Nominal Voltages Marginal Voltage Limits Marginal Checking Procedure Error Checking

Identification •

Failure Detection Facilities PREVENTIVE MAINTENANCE

Lamp Test Diagnostics .

SERVICE CHECKS, ADJUSTMENT AND REMOVAL PROCEDURES .

CPU AND CHANNEL SERVICE CHECKS Waveform Measurem ents

2050 Clock.

MAIN STORAGE (MS) SERVICE CHECKS Storage Test

Main Storage Test Points Main Storage Addressing

Main Storage Temperature and Humidity Main Storage Power Information • Exercise Bump Storage

Continually Address One MS Location Scan MS for Bad Parity •

Bit Arrangement of MS Word Check Strobe of Main Storage

Checking MS Drivers and Terminating Diodes.

CONTENI:S

46 46 47 48 48 51 51 53 56 57 57 58 61 61 63 63 71 71 71 72 72 74 74 74 74 74 74 74 75 76 76 76 76 76 76 79 79 79

80 80 80 80 80 80 80 81 81 81 82 82 82 82 82 83

iii

Delay Line Clock • 83 Switch and Indicator Check 112

Delay Line Driver. 84 EMULATOR SERVICE AIDS 114

Layout of M9/M9A Planes 84 1410/7010 Emulator Delays 114

X Drive Current 84 1410/7010 Disk Conversion 114

Y Drive Current 85 2302 Disk Storage Map 114

Shorted X Dri ve Line • 85 2302 Track Correspondence 114

Open X Drive Line 85 2314 Disk Storage Map 114

Drive Line Shorted to Ground 86 2314 Track Correspondence 114

Sense Inhibit 87 1410/7010 Diagnose Instruction Addresses 115

Storage Waveforms (Voltage Probe) 88 Start I/O Diagnose Instruction 115

Sense Amplifier Output (M9) 88 7070/7074 Operation Codes 115

M9A Differences 89

LOCAL STORAGE (LS) SERVICE CHECKS 90 POWER SYSTEM SERVICE CHECKS 120

Local Storage Timings 90 Con'verter-Inverter 120

LS Read Operations 90 SCR Gate Signals • 121

LS Write Operation 90 Types of Failures 123

LS Functional Packaging 90 Converter-Inverter Fuse Replacement 123

Local Storage Word Selection 92 Converter-Inverter Troubleshooting 123

LS Temperature Control Unit Check. 92 Voltage Regulator Test Points 123

Local Storage Waveforms 92 Changing Voltage Regulators 123

Optimize LS Drive Currents (Shmoo) • 93 Voltage Sequence Problems 124

LS Strobe Driver Identification. 95 Plus 18 Volt Sequence Down 124

ROS 201--Cycle One Sector of Local Storage • 95 Overcurrent Problems 125

Array Temperature 95 Voltage Regulator Problems 125

Local Storage Heater. 95 Overvoltage Unit Adjustment 125

Checking Drivers and Terminating Diodes. 95 Low Voltage AC Supplies 126

READ ONLY STORAGE (ROS) SERVICE CHECKS. 95 Power Sequencing Relays 126

Ros Retry Adjustment. 95 Dual or Multi System Emergency Power Off 126

ROS Waveforms 96

ROS Parity Errors 96 LOCATIONS. 127

ROS FOO-F03--ROSDR Test All Ones 97 Power Distribution Frame Locations 127

ROS FOl-f'02--ROSDR Test All Zeros 97 Frame and Qate Locations 127

ROS Address 000 97 Relay and Contactor Locations . 127

Extra or Missing Bits 97 Circuit Breaker Locations 127

Sense Latch and Strobe 98 Fuse Locations • 127

ROS Ripple Test 98 Voltage Regulator Locations 127

ROS BIT PLANE REMOVALS AND ADJUSTMENTS • 100 Overvoltage Assembly Locations 127

ROS Bit Plane Adjustments • • 100 I/O Tailgate Locations 127

ROS Bit Plane Removal • • 100 I/O Address Cards. 127

ROS Bit Plane Cleaning • 100

ROS Bit Plane Installation • 101

Connector Installation 102 APPENDIX A - SYSTf}..1 CHARACTERISTICS 138

STORAGE PROTECT (SP) SERVICE CHECKS 102 Physical Data 138

Reference Voltage and Sense Level Adjustments 102 Frame Specifications. 139

Checking SP Drivers and Terminating Diodes 102 Cabling 139

Inhibit Drivers and Sense Amplifiers 102 Power Requirements 139

SP Sense Windings • 102

Termination Diodes • 103

X and Y Dri vers 103 APPENDIX B - SYSTEM CONTROL PANEL 140

Storage Protect Test Points 103 Controls and Indicators 140

CHANNEL SERVICE CHECKS 103 Section A - Power Display 140

Selector Channel 103 Section B - Storage Test. 142

C Reg Set and IF Service Out Delays 103 Section C - Emergency Off . 142

Channel Reset • 103 Section D 142

A-Clock Check. 107 Section F - Channel Control 142

Cycle Counter Check. 107 Sections G and K - Status Indicators 143

B-Clock Check 107 Selector Channel Roller Analysis 144

Tag Generator and Manual Stop Controls 107 Section H - Blank • 149

Indicator Check 108 Section J -Local Store Chart 149

A--<:lock Manual Controls 108 Section L - MC, SDR, IAR Indicators; Data and Address

Operation Control Check 109 Keys 150

DTC Hold Check 109 Section M - Intervention and Maintenance Switches. 150

Singleshot Adjustment 109 Section N - Operator Controls 154

Selector Channel Clock-Stepping Procedure 109 Operating Instructions 155

1052 Adapter/Printer-Keyboard 112 System Initialization 155

Singleshot Adjustment 112 Initial Program Load 155

iv

Display and Store Operations ISS Initial Program Load • 158

Miscellaneous Operations 156 Start, Stop 159

Theory of Operation 157 Halt Loop Operations • 159

Power On, Power Off • 157

System Reset 157 INDEX 189

v

ILLUSTRATIONS

Figure Title Page Figure Title Page

DIAGNOSTIC TECHNIQUES 50 Model 50 Diagnostics. 75

Status of Indicators after System Reset 11

2 ECAD Block Key 12 PREVENTIVE MAINTENANCE

3 ALD Page Key. 13 51 Model 50 Preventive Maintenance Schedule 79

4 CAS Logic Diagram Page Key 14

SERVICE CHECKS, ADJUSTMENT AND REMOVAL PROCEDURES

MAINTENANCE FEATURES

Service Checks--CPU and ChalUle1 5 Controls, Latches, Etc., Used in

52 Waveform Measurements 80

Maintenance Operations. 18

53 Main Storage Test Points 81

6 Basic Operations and CPU Control Modes 19

54 Main and Bump Storage Addressing 82

7 CPU Control Modes for Maintenance Operations 19

55 Main Storage Strobe 83

8 MS Mode Instructions and Data Paths. 20

56 Card Extender Jumper Wire 83

9 Sequence Counter Logic Chart • 21

57 Delay Line Clock 83

10 FL T Op Reg Instructions. 22

58 Input to Delay Line Driver 84

11 Scan/Log Decoder. 22

59 M9/M9A Drive System 84

12 Scan-Out/Logout: Locations and Data (4 Parts) 23

60 Physical Layout of M9/M9A Planes 85

13 Scan-Out/Logout: Logic and Indicators 27

61 X Drive Current 85

14 ROS Kernels (Maintenance Routines) 28

62 Y Drive Current 85

15 ROS Kernels F1owchart: Diagnose/Fl. T /

63 Shorted X Drive Line 85

Log Trigger Entries (2 Parts) 29

64 Open X Drive Line 86

16 Hardware Addresses No. 1 and 2 31

65 Possible Shorted Drive Line 86

17 Storage Locations and Bit~ for L Register Logout 31

66 Possible Open Drive Line 86

18 Logout Under Sequence Counter and Main Store

67 Dri ve Line Shorted to Ground 86

Mode (2 Parts} • 33

68 Current Turned Off by Terminator Gate. 87

19 Supervisory Controls (2 Parts) 37

69 Blue-White Sense Lines, Sense-Inhibit 87

20 Clock Distri bution . 39

70 Inhi bi t Pulse 87

21 Changing CPU Control Status 39

71 Inhibit Pulse with Open Leg 87

22 Diagnose Usage (Scope Bump Word) 41

72 Inhibit Pulse with Grounded Sense-Inhibit Line or

23 Fl.T Tapes: Model 50. 41 Shorted Inhibit Driver 88

24 FLT Disk Packs: Model 50 41

73 Output of Good Sense f\mplifier (M9 Only) 88

25 FLT Load via Tape 43 74 Main Storage Select--Waveform 88

26 Fl T Load via Disk 44

75 Main Storage Terminator--Waveforms 88

27 MaSh and Expected Response Examples 47

76 Main Storage Gate and Driver Patterns--Waveforms 89

2b l'vlS rv10de ROS Bit Test 48 77 Main Storage Driver Failures--Waveforms 89

29 HarJcore Test Sample: ROS Mode (2 Parts) 49

78 Strobe for L.lch Segment and Bit 89

30 FLT Load to Cycle Tests 51 79 M9A Strobe and Sense Circuits 90

31 FL T Cycle Tests: Word Format 52 80 M9A Preamplifier Outputs--Waveforms 91

32 Fl,T Zero/One-Cycle Tests. 53

81 Local Storage Address Bit Functions 92

33 FL T Compare and Branch Kernel 54

82 Extender Card Wiring: LS Temperature Check. 93

34 FLT Run ilno Repair Procedure. 55

83 LS Write Driver 94

35 C>'cle Test Repair Procedure 56

84 LS Bit Driver 94

36 FL T Scan-In, Parity Generation, and Scan-Out 60 85 LS Gate Driver. 94

37 Zero-Cycle Test Documentation 61 86 LS Sense Amplifier 94

38 One·Cycle Test Documentation (Scopex) 62 87 LS Read Driver. 94

39 One-Cycle Test Scope Timings 62 88 Module Side of 5801515 Card 95

40 Sensitive Net Examples 62

ROS Waveforms 97

41 Interface Register and Functions 64 89

ROS Drive Line Tests 98

42 Multiplexor Channel Progressive Scan Run and 90

91 ROS Select Line Tests 99

Repair Procedure 65

ROS Strobe and Sense Latch Test Points 99 43 Selector Channel Progressive Scan Run and 92

93 ROS Sense Amplifier and Latch Card Locations 99

Repair Procedures (3 Parts) • 66

Setscrew Torque Sequence (ROS Bit Planes) 100 44 Test Series 110. 1 Test 01 94

(Diagnose Section--Start I/O Write Series) • 69 95 SP Reference Voltage Tracking 102

4S Typical Test Series (Series 110) 69 96 SP Inhibit Driver and Sense Amp Locations. 102

46 Scan Test Timing Procedure 69 97 SP Sense Winding Test Points 103

47 Start I/O Write Timing 70 98 Storage Protect Driver Locations 103

48 Selector Channel A Clock: Signal Sequences 72 99 Selector Channel Maintenance Approach 105

49 Progressive Scan Printout (Sel Ch). 73 100 Reset Pulses (Clock Not RUlUling) 107

vi

Figure Title Page Figure Title Page 101 Reset Pulses (Clock Running~ 107 APPENDIX B - SYSTEM OPERATION

102 A Clock. 107 136 System Control Panel. 141

103 Cycle Counter 108 137 Common Channel Roller - Position 1. 162

104 B Clock. 108 138 Common Channel Roller - Position 2. 162

105 Tag Generator • 108 139 Common Channel Roller - Position 3. 163

106 Singleshot Timing Procedure 109 140 Multiplex Channel Roller - Position 4. 163

107 Selector Channel Clock-Stepping Block Diagram • 110 141 Multiple~ Channel Roller - Position 5 164

108 1052 Singleshot Timing Procedure 112 142 Multiplex Channel Roller - Position 6 164

109 1052 Read Sequence • 113 143 Multiplex Channel Roller - Position 7 165

110 1410/7010 Emulator Delays 115 144 Multiplex Channel Roller - Position 8 165

111 Emulated 7070/74 Operation Code~ (4 Parts) 116 145 Selector Channel Roller - Position 1 • 165

112 Power On Sequence 120 146 Selector Channel Roller - Position 2 • 166

113 Power/DC Off Sequence. 121 147 Selector Channel Roller - Position 3 • 167

114 Converter-Inverter Testpoints and Waveforms. 121 148 Selector Channel Roller - Position 4 • 168 115 Converter-Inverter (Cover Off) 122 149 Selector Channel Roller - Position 5 • 169 116 Converter-Inverter Test Points 123 15,0 Selector Channel Roller - Position 6 • 170 117 Voltage Regulator Test Points 124 151 Selector Channel Roller - Position 7 • 170

118 Overvoltage Adjustment • 125 152 Selector Channel Roller - Position 8 • 171

153 CPU 1 Roller - Position 1 171

154 CPU 1 Roller - Position 2 172

LOCATIONS 155 CPU 1 Roller - Position 3 173

119 PDU CB and Switch Layout 127 156 CPU 1 Roller - Position 4 174

120 Model 50 Frame and Gate Locations • 128 157 CPU 1 Roller - Position 5 175

121 Power Distribution Frames (2 Parts) 129 158 CPU 1 Roller - Position 6 176

122 Relay and Contactor Location Chart • 131 159 CPU 1 Roller - Position 7 177

123 Circuit Breaker Location Chart 132 160 CPU 1 Roller - Position 8 177

124 Fuse Location Chart 132 161 CPU 2 Roller - Position 1 178

125 Voltage Regulator Location Chart 133 162 CPU 2 Roller - Position 2 178

126 Voltage Divider Assembly 134 163 CPU 2 Roller - Position 3 179

127 Overvoltage Assembly 134 164 CPU 2 Roller - Position 4 180

128 I/O Gate Terminators 135 165 CPU 2 Roller - Position 5 181

129 I/O Interface Connections 136 166 CPU 2 Roller - Position 6 181

130 1442 Address Card Locations and Plugging 136 167 CPU 2 Roller - Position 7 182

131 1443 Address Card Locations and Plugging • 136 168 CPU 2 Roller - Posi tion 8 182 132 2821 Address Card Locations and Plugging 137 169 Maintenance Control Indicators 183

133 TAU (2400) Address Cards Locatiollls and Plugging 137 170 SDR Indicators • 184

171 IAR Indicators • 184

172 ROS Function Check • 184

173 System Reset 185

APPENDIX A - SYSTEM CHARACTERISTICS 174 Initial Program Load 186

134 IBM 2050 Processing Unit 138 175 Start, Stop, Exception Logic 187

135 IBM 2050 Frame and Gate Layout. 138 176 Control Panel Stat Setting 188

vii

ABBREVIATION~

Adr Address MC Maintenance Console

ALCH Adder Latches to Channel Mpx Multiplexor

ALD Automated Logic Diagram MS Main Storage

Blk Block Op Operation

BT Binary Tgr

p Parity

CC Command Chain PB Pushbutton

CFC Control Field Chart PCI Program Controlled Interrupt

Ch Channel P/F Pass/Fail

CHAL Channel to Adder Latches PL Program Load

Chk Check Pri Priority

CLF Condensed Logic Flowchart PSS Progressive Scan Stat

Clk Clock PSW Program Status Word

Cnt Count

Com Common ^Rd Read

Ctr Counter Reg Register

Ctrl Control Req Request

Cyl Cylinder ROAR Read Only Storage Address Register

ROS Read Only Storage

DTC Data Transfer and Control ROSDR Read Only Storage Data Register

Rst Reset

ECAD Error Check Analysis Diagram Rtne Routine

R/W Read/Write,

FLT Fault Lo~ating Test

S Stat

G/F Good/Fail SAR Storage Address Register

GP General Purpose (Stats 0-7) SCR Silicon-Controlled Rectifier

Gr Group SDR Storage Data Reglster

at Gate Seg Segment

Sel Selector

HA Hardware Address Seq Sequence

Hdw Hardware SESS Supervisory Enable Storage Stat

SIll Suppress Incorrect Length Indication

IAR Instruction Address Register SIM Simulated Check

IF Interface Register SP Storage Protect

IIC Inhibit IAR Count SS Supervisory Stat

ILl Incorrect Length Indication Sto Storage

Inh Inhibit Sw Switch

Insn Instruction

I/O Input/Output TD Time Delay

IPL Initial Program Load Term Termination

Irpt Interrupt Tg. Trigger

TIM Timing Chart

LCS Large Capacity Storage UA Unit Address

LCW Linkage Control Word UCW Unit Control Word

Loc Location

LS Local Storage Wr Write

viii

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SAFETY PROCEDURES

Safety cannot be overemphasized. To insure per- sonal safety and the safety of co-workers, each CE should make it an everyday practice to observe safety precautions at all times. All CE's should be familiar with the general safety practices and pro- cedures for performing artificial respiration that

resistors to drain off capacitor charges when power is dropped, it is wise to check all capacitors with a meter before attempting maintenance. A defective bleeder resistor could create an unexpected hazard.

are outlined in CE Safety Procedures, S229-1264. For convenience, this form is duplicated below.

CAUTION

Before changing SLT cards in main storage, storage protect, and local storage, drop power to the unit.

Dropping power is the only sure way to prevent card damage from voltage surges during card replacement.

Always use a reliable voltmeter to verify that power is actually off after using power off switches. Al- though all power supplies are provided with bleeder

CE SAFETY PRACTICES

All Customer Engineers are expected to toke every safety pre- caution possible and observe 'he following safety practices while maintaining IBM equipment:

1. You should not work alone und4H hazardous conditions or around equipment with dangerous voltage. Always advise your manager if you MUST work alone.

2. Remove all power AC and DC when removing or assem·

bling major com'ponenls, working in immediate area of power supplies, performing mechanical inspection of power supplies and installing changes in machine circuitry.

3. Wall box power switch when turned off should be locked or tagged in off position. "Do not Operate" tags, form 229·1266, affixed whton applicable. Pull power supply cord whenever possible.

4. When it is absolutely necessary to work an equipment hav- ing exposed operating mechanical paris or exposed liv.

electrical circuitry anywhere in 'he machine, the following precautions must be followed:

a. Another person familiar with power off controls must be in immediate vicinity.

b. Rings, wrist watches, chains, braceleh, metal cuff links.

shall not be worn.

c. Only insulated pliers and screwdrivers shall be used.

d. Keep one hand in pocket.

e. When using test instruments be certain controls are set correctly and proper capacity, insulated probes are utld.

f. Avoid contacting ground potential (metal floor strips, machine frames, etc. - use suitable rubber mah pur·

chased locally if necessary).

5. Safety Glasses must be worn when:

a. Using a hammer to drive pins, riveting, staking, etc.

b. Power hand drilling, reaming, grinding, etc.

c. Using spring hooks, attaching springl.

d. Soldering, wire cutting, removing ste.1 bands.

e. Parts cleaning, using solvents, sprays, clean.rs, chemicals, etc.

f. All other conditions that may be hazardous to your eyes. REMEMBER. THEY ARE YOUR EYES.

6. Special safety instructions such as handling Cathode Ray Tubes and extreme high voltages, must be followed as outlined in CEM's and Safety Section of the Maintenance Manuals.

7. Do not use solvents, chemicals, greases or oils that hay.

not been approved by IBM.

•. Avoid using tools or test equipm.nt that have not b •• n approved by IBM.

9. Replace worn or broken tools and test equipm.nt.

10. Lift by standing or pushing up with stronger leg muscles - this takes strain off bock muscles. Do not lift any equip.

ment or ports weighing over 60 poundl.

11. All safety devices such as guards, shi.lds, lignl. ground wires, etc. shall be restored after maintenance.

KNOWING SAFETY RULES IS NOT ENOUGH AN UNSAFE ACT Will INEVITABLY LEAD TO AN ACCIDENT

USE GOOD JUDGMENT - ELIMINATE UNSAFE ACTS 5229·1264-1

12. Each Customer Engineer is responsible to be certain that no action on his part renders product unsafe or e/Cposes hazards to customer personnel.

13. Place removed machine covers in a safe out-of-the-way place where no one con trip over them.

14. All machine covers must be in place before machine is re- turned to customer.

15. Always place CE tool kit away from walk areas where no one can trip over it (i.e., under desk or table).

16. Avoid tOl./ching mechanical moving parts (i.e., when lubri·

cating, checking for play, etc.).

17. When using stroboscope - do not touch ANYTHING - it may be moving.

18. Avoid wearing loose clothing that may be caught in machin·

ery. Shirt sleeves must be left buttoned or rolled above the elbow.

19. Ties must be tucked in shirt or have a tie clasp (preferably nonconductive) approximately 3 inches from end. Tie chains are not recommended.

20. Before starting equipment, make certain fellow CE's and customer personnel are not in a hazardous position.

21. Maintain good housekeeping in area of machines while per·

forming and after completing maintenance.

Artificial Respiration

GENERAL CONSIDERATIONS 1. Start Imm.diat.ly, Second. Count

Do not move victim unleu abso- lutely neceuary to remove from danger. Do not wait or look for h.lp or stop to loosen clothing, warm the victim or apply stimu·

lants.

Rllcu. Breathing for Adults Victim on His Bacle Immediately

2. Ched, Mouth for Obstructions Remove foreign objects - Pull tongue forward.

3. Loo"n Clothing - K.ep Warm Take care of these items after vic- tim is breathing by himself or when help is available.

4. Remain in Position

After victim rtvivII, b. ready to resume respiration if nec.nary.

5. Call a Doctor

Hav. someone summon medical aid.

6. Don't Giv. Up

Continu. without interruption until victim is breathing without help or is certainly dead.

It.prlnt Courtesy Min. Saf.ty Appliances Co.

1. Clear throat of water, food, or foreign matter.

2. Tilt h.ad back to open air passage.

3. Lift jaw up to keep tongue out of air passage.

4. Pinch nOltrils to prevent air leak- age when you blow.

S. Blow until you see chest rise.

6. Remove your lips and allow lungs to empty.

7. List.n for snoring and gurgling"

sign. of throat ob.truction.

S. R.peat mouth to mouth breathlngs 10-20 times a minute.

Continue 'IICU. breathing until he breathes for himself.

Thumb and

finoe, positions

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^inalmouth

MAINTENANCE PHILOSOPHY

The system provides facilities that assist the CE in:

Failure Detection Fault Location

Deferred Maintenance Rapid Repair

Failure Detection

Error detection is accomplished by hardware parity checking, fault locating tests (FLT's), ,and functional diagnostic programs. Not all failures can be detected however.

Failure Detection By Hardware

The central processing unit (CPU) is parity checked. All data transfers between registers and main storage are checked by byte. Good parity is always written into main storage by design (except FLT's).

Parity checking is also used on the read-only storage (ROS) at the output.

Any multiplexor and selector channel circuitry not used by the CPU has its own parity checking circuitry.

Each error check is indi viduaUy indicated on the C E-operator' s console. To provide a high diagnos- tic resolution, the individual checks are OR'ed in groups by timing and function and are also indicated on the console.

Fault Locating Tests (FLT's)

FLT's are semi-automatic diagnostic procedures used in the Model 50 CPU. The procedure involves a battery of diagnostic tests, each performed by forcing the CPU to a predetermined state (scan-in), running the CPU for a specified number of machine cycles (clock advance), logging the resulting state into storage (scan-out), and then comparing the resulting state of the selected machine area upder test (compare) with a pre-computed result.

Functional Diagnostics

The functional diagnostic programs are the highest level of testing a system. They are system pro- grams that check for correct system operation.

Functional diagnostics have been written for aU areas of the Model 50.

DIAGNOSTIC TECHNIQUES Deferred Maintenance

The logout facility allows maintenance activity to be deferred. Certain intermittent failures will be such that long time periods elapse between interruptions.

Troubleshooting this type of fault is time-consuming.

The failure environment is difficult to reproduce.

The customer will often prefer to continue system operation and postpone maintenance activity under these circumstances. The logout feature allows the customer to continue system operation while pro- viding the CE with information on the system state at the time of the error.

TROUBLESHOOTING FLOWCHART

Flowcharts for troubleshooting the 2050 Processing Unit are now in the Maintenance Diagrams Manual for the 2050.

Figure 1 shows the status of indicators after sys- tem reset.

Roller Indicators

Common Chan 2 SBCR unpredictable

Common Chan 3 BUFFER 1 and BUFFER 3 reset BUFFER 2 set to previous contents of BUFFER 1

Mpx Chan 4 BUFFER 1 and BUFFER 2 unpredi ctable Mpx Chan 5 BUS OUT unpredictable

Mpx Chan 6 POLL on, MPX I/o STATS unpredictable Selector Chon 1 B-REGISTER P-bits on

Selector Chan 2 C-REGISTER P-bits on Selector Chan 3 BYTE COUNTER P-bits on Selector Chan 4 CYCLE COUNTER stepping

Selector Chon 5 POS REG TRF, SP-D2, and INSN SCAN on;

A-CLOCK stepping Selector Chon 6 FIN on

CPU 1 1 L-REGISTER = PSW Backup CPU 1 2 R-REGISTER P-bits on CPU 1 3 M-REGISTER P-bits on CPU 1 4 H-REGISTER P-bits on

CPU 1 ₅ SAR bit 17 on, BYTE STATS unchanged, BYTE STORE STATS set to 1

CPU 1 6 RaSDR = Halt Loop CPU 2 1 ROSDR = Halt Loop

CPU 2 2 ROSDR = Halt Loop, MOVER FUNCTION unpredi ctablo

CPU 2 3 ONE SYL OP on, REFETCH unpredictable. NEXT

CPU 2 4

ROS ADDRESS = Halt Loop, ILC unpredictable I/O REGISTER P-bit, L BYTE CNTR, and M BYTE CNTR oni F-REG, EDIT STATS, and CARRY unchanged

CPU 2 5 LSAR = Hex 17, LSFN = I, J-REG = 7, MD = 3, Gl and G2 have S- and P-bits on

CPU 2 7 CURRENT ROS ADDRESS = Halt Loop CPU 2 8 PREVIOUS ROS ADDRESS = Halt Loop

Most other indicators are off, but for definite status refer to machine logic.

FIGURE 1. STATUS OF INDICATORS AFTER SYSTEM RESET

Diagnostic Technique. (3/71) 11

Power Faults

See the section, Power System Service Checks, in this manual.

Loading Faults

See the section on FLTs in this manual. Remember that none of the central processing unit and very little of the channel circuitry is used to load FLTs.

Programming Faults and Error Stops

Programming faults and error stop approaches to troubleshooting are shown. Note that:

1. The machine status is logged out before begin- ning a troubleshooting sequence.

2. FLT's are run before functional tests.

OTHER MAINTENANCE DOCUMENTATION Error Check Analysis Diagrams

Error check analysis diagrams (ECAD's) are com- puter-drawn, engineering controlled, schematic representations of the error register and the cir- cuitry behind each possible error indication.

AL6

1~TR20 ---

H RH001- RH071

46-47 CPU Roller 1

_ _ _ _ _ 2

5

Position 4 ~6

ECAD's are in Volume 1 Reference of Systems Diagrams. To use ECAD's, turn to page UCA101 and find your particular error in the error register block diagram. The numbers to the left of the error register lead you to an ECAD specifically tailored for that error. Further to the left is the ALD page number of the parity checker for that error.

Each ECAD contains a block diagram simplified to show the basic logic of the error checking circuit and a list of ROS functions that pertain to the circuit.

In addition, basic timings, scope points, pertinent notes, and the complete logic for at least one bit position of the error circuit are shown wherever necessary.

Figure 2 shows how to read an ECAD block.

SER VIC E AIDS

This section is for Customer Engineering Memoran- dums (C EM's) and other aids helpful in servicing the Model 50. CEM's are generated and distributed by Field Engineering Technical Operations as the need for them arises.

ALD Page Key

Figure 3 is a key to the Model 50 ALD pages showing the basic content of each section of the ALD's.

1. ROS Functions: Specifies the gating into the register. Enough of the control field specificatiom are reproduced to permit interpretation of the function. In this example, AL6 would be shown as IAR H(8-31), and TR 20 would be shown a~ Latch H(0-31). Thus the two sources of input to the H register ore the latch and IAR. By examining the ROS word in control during the error cycle, the source of the data in the H register can be pinpointed.

2. Nome of Register: Self explanatory.

3. ALD Pages: Self explanatory.

4. Scoping Point: Refers to on entry in a testpoint table, from which scoping information can be obtained.

5. Logout Location: Refers to the storage word(s) into which the register is logged on on error log out. This is a decimal word address.

6. Indication: Specifies where in the switchable indicators the register is displayed.

FIGURE 2. ECAD BLOCK KEY

12 (3/71) Model SO FEMM