The Following Application Notes Are Available From Zilog / Z80~ Family Interrupt Structure o· Using the Z80 SIO in Async Communications Using the Z80 SIO with SDLC Binary Synchronous Communications Using the Z80 SIO Serial Communications with the Z80A DART Interfacing Z8500 Peripherals to the Z80 Serial Clock Generation Using the Z8536 CIO Timing in Interrupt-Based System with Z80 CTC A Z80-Based System USing the DMA with the SIO Interfacing Z80 CPUs to the Z8500 Peripheral Family ~ Z180~/SCC Serial Communication Controller Interface at10 MHz Local Talk Link Access Protocol Using the Z80181 Z80 Using the Z84C11/C13/C15 in Place of the Z84011/013/015 /" Using SCC with the Z80OO~ in SDLC Protocol ,../ SCC in Binary Synchronous Communications On-Chip Oscillator Design Interfacing the Z8500 Peripherals to the 68000 ESCC~ Enhancements over the SCC . / Design a Serial Board to Handle Multiple Protocols Using the Z16C30 USC Universal Serial Controller with Mil-STD-1553B Datacommunications IUSCN/MUSC^N Time Slot Assigner .~ Integrating Serial Data and SCSI Peripheral Control on One Chip Additional Information ... 1227

Z80~ Development Support ... : ... 1229

SuperintegrationN Products Guide ... 1232

Support Products Summary ... 1239

Z80~/Z180N/Z280~ Hardware and Software Support ... 1299

Military Qualified Products ... , ... 1301

Package Information ... 1303

Ordering Information ... ~ ... 1311

Quality and Reliability ... 13t5 Literature Guide ... 1319

ii

(4)

INTRODUCTION

Zilog is an innovator in the development, design and manufacture of Application Specific Standard Products (ASSPs) for the datacommunications, intelligent peripheral controllers and consumer-product controllers market.

ASSPs are very large-scale integrated circuits designed for a particular market application rather than a single customer. Zilog supplies ASSPs utilizing its Superintegration~ design technology to combine cores and cells from the Company's extensive library of customer familiar microprocessors, microcontrollers, memory and logic circuits to meet the design, cost and time-to- market requirements of its customers.

Zilog was an innovator in the addition of intelligence to computer peripheral chips using its popular line of Z80⁸8- bit and Z280⁸ 16-bit microprocessors and peripheral circuits. Adding intelligence to computer peripherals frees the central processor from micromanagement tasks and upgrades the performance of the system. Based on the powerful Z8⁸ 8-bit microcontroller, Zilog's family of controllers is used in such diverse products as cellular phones, answering machines, televisions, educational products, and a wide range of computer-related products such as mice, keyboards and mass storage products.

VOLUME I DATABOOK

DISCRETE Z80® FAMILY EMBEDDED CONTROLLERS

SERIAL COMMUNICATIONS CONTROLLERS

Zilog is rapidly expanding its product offering with more than 19 new products announced in the first three quarters of 1991, yielding more than 40 variations. Zilog's extensive library of cores and cells includes serial communications controllers, 8-bitmicrocontrollers, 8-, 16- and 32-bit microprocessors and peripheral circuits. The Superintegration library and diverse product portfolio of over 850 items serve three distinct markets. In datacommunications, Zilog holds a leadership pOSition in general purpose, multiprotocol controllers for the local area network markets. The Company offers a range of controllers from the industry standard, medium-speed SCC to the high-performance USC~. Complete families of products are based on these cores.

Included in these introductions is the Z86C94, the industry's first 8-bit microcontroller to add a digital signal processor on Chip. The device is used for efficient digital control of servo functions in disk drives. In the consumer area, Zilog introduced a new single-chip closed-caption controller which will position the Company to capture a significant share of the television market.

(5)

cu

Co:»

c m

E ...

-

Q

^...

^CU

A.

2

l80 Product Evolution

16-BK 4DMAs Z80CPU

MMU UART

Cache 3 CntrfTmrs Z801ZBUS WSG

Z280

1- - - -I I

CPU+ 2DMAs CPU + 2DMAs ^I

SCC I

(1 Ch_) I

2 UARTs 2 UARTs 16 I

MMU MMU I -^I/O ^I_I

211rners ClocklSerial _{2 TImers} Clock/Serial CTC I

>

Z180 Z181

2KSRAM 40110

~

^CPU ^SIO

CPU

I

^CTC ^PIO ^SIO ^CPU

I~ ~

^CPU ^Power^Down ^CPU ^Power^Down ^{t - -}^PIA ^I^CTC Enhancements ^CTC Enhancements ^PIO ^CTC

Z84C01 Z84C50 Z84011/C11 Z84C90 Z84013/C13 Z84015/C15

I

Z844X SIO

I ₁

^Z84C4XS10

J

I

^{Z8430 CTC}

r---- ^I

Z84C30 CTC

I

^Z8420P10

r- I

Z84C20 PIO

~

I

^{Z8410 DMA}

r

^Z84Cl0DMA

r

I

Z8400 Z80 CPU

r

NMOS Discrete

I

Z84COO Z80 CPU

r

CMOS Discrete

Integration

(6)

DISCRETE Z80® FAMILY

3

(7)

4

(8)

~ ZiLlJl3 Product Specification

FEATURES

The extensive instruction set contains 158 instructions, including the 8080A instruction set as a subset.

• NMOS version for low cost high performance solutions, CMOS version for high performance low power de- signs.

• NMOS Z0840004 - 4 MHz, Z0840006 - 6.17 MHz, Z0840008 - 8 MHz.

• CMOS Z84C0006 - DC to 6.17 MHz, Z84C008 - DC to 8 MHz, Z84C0010 - DC to 10 MHz, Z84C0020 - DC- 20 MHz

• 6 MHz version can be operated at 6.144 MHz clock.

Mi _As

A,

MiiEti A2

SYSTEM ^IciiiQ ^A,

CONTROL AD 110

Viii As

As

RFsii A7 ADDRESS

As BUS

iiAi:i' _As

A,.

A11

CPU zaocPu ^Z8400 A'2

CONTROL _A"

A,.

A"

CPU { BUS CONTROL

DATA BUS

Figure 1. Pin Functions

Z8400/Z84COO NMOS/CMOS Z8(}'l1 CPU

Central Processing Unit

• The Z80 microprocessors and associated family of peripherals can be linked by a vectored interrupt system. This system can be daisy-chained to allow implem- entation of a priority interrupt scheme.

• Duplicate set of both general·purpose and flag registers.

• Two sixteen-bit index registers.

• Three modes of maskable interrupts:

Mode 0-8080A similar;

Mode 1-Non·Z80 environment, location 38H;

Mode 2-Z80 family peripherals, vectored interrupts.

• On·chip dynamic memory refresh counter.

A11 A,.

A'2 A,

A" As

A,. A7

A,s A,

ClK A,

D. 110

D, A,

D, A2

D. A,

+sv As

D2 GND

D7 RFSH

D. M1

D, RESET

INT BUSREO

NMI WAIT

HALT BUSACK

MREO iNA

IORO iiD

Figure 2.1 40-pin Dual-In-Llne (DIP), Pin Assignments

(9)

"'",4'

"'.r"

"''''.i1",~ "f",,,,,,,,("

"''''0 "'11

"'cf' "f.,> "f.,.

41 34

33

elK Ne

04 AS

03 A4

05 A3

06 A2

+SV Z80 CPU ^Al

02 AO

07 GNO

DO RFSH

01 Mi

Ne RESET

11 23

12 22

~1-~~\~~~J,.,?~)..~ _p_P .':'q?~"'-!'>p.

44 pin Quad Flat Pack (QFP), Pin Assignments (Only available for 84COO)

GENERAL DESCRIPTION

The. CPUs are fourth-generation enhanced microprocessors with exceptional computational power. They offer higher system throughput and more efficient memory utilization than comparable second- and third-generation microprocessors. The internal registers contain 208 bits of readlwrite memory that are accessible to the programmer.

These registers include two sets of six general-purpose registers which may be used individually as either 8-bit registers or as 16-bit register pairs. In addition, there are two sets of accumulator and flag registers. A group of

"Exchange" instructions makes either set of main or alternate registers accessible to the programmer. The alternate set allows operation in foreground-background mode or it may be reserved for very fast interrupt response ..

+5V ...

GND ...

CLOCK ...

~CJ 'fo ... Io)'fo"'~'fo"''!>'fo''''\.'fo'''''' 'fo ... t)'fo~ 'fo'b 'fo'\ 'fob 6 5 4 3 2 1 44 43 42 41 40

ClK 7 3' As

0, 8 38 A,

0,

•

^{37 A,}

0 5 10 36 A,

06 11 35 A,

NC 12 Z80CPU 34 Ao

+5V 13 33 GNO

0, 14 32 AFSH

0 7 15 31 M1

Do 16 30 RESET

0 , 17 2. BUSREQ

18 19 20 21 22 23 24 25 26 27 28

Fiaure 2b. 44-Pin ChiD Carrier Pin Assianments

The CPU also contains a Stack Pointer, Program Counter, two index registers, a Refresh register (counter), and an Interrupt register. The CPU is easy to incorporate into a system since it requires only a single + 5V power source. All output signals are fully decoded and timed to control standard memory or peripheral circuits; the' CPU is supported by an extensive family of peripheral controllers.

The internal block diagram (Figure 3) shows the primary functions of the processors. Subsequent text provides more detail on the

ilo

controller family, registers, instruction set, interrupts and daisy chaining, and CPU timing.

Figure 3. Z80C CPU Block Diagram 6

(10)

zso

Table 1.

zaoc

CPU Registers

Register Size (Bits)

A,A' Accumulator 8

F, F' Flags 8

B, B' General Purpose 8

C,C' General Purpose 8

0,0' General Purpose 8

E, E' General Purpose 8

H,H' General Purpose 8

L, L' General Purpose 8

Interrupt Register 8

R Refresh Register 8

IX Index Register 16

IY Index Register 16

SP Stack Pointer 16

PC Program Counter 16

IFF1-IFF2 Interrupt Enable Flip-Flops IMFa-IMFb Interrupt Mode Flip-Flops

failure has been detected. After recognition of the NMI signal (providing BUSREO is not active), the CPU jumps to restart location 0066H. Normally, software starting at this address contains the interrupt service routine.

Maskable Interrupt (INT). Regardless of the interrupt mode set by the user, the CPU response to a maskable interrupt input follows a common timing cycle. After the interrupt has been detected by the CPU (provided that interrupts are enabled and BUSREO is not active) a special interrupt processing cycle begins. This is a special fetch (M1) cycle in which IORO becomes active rather than MREO, as in a normal M1 cycle. In addition, this special M1 cycle is automatically extended by two WAIT states, to allow for the time required to acknowledge the interrupt request.

Mode 0 Interrupt Operation. This mode is similar to the SO SO microprocessor interrupt service procedures. The interrupting device places an instruction on the data bus.

This is normally a Restart instruction, which will initiate a call

Remarks Stores an operand or the results of an operation.

See Instruction Set.

Can be used separately or as a 16·bit register with C.

Can be used separately or as a 16-bit register with C.

Can be used separately or as a 16-bit register with E.

Can be used separately or as a 16-bit register with L.

Note: The (B,C), (O,E), and (H,L) sets are combined as follows:

B - High byte C - Low byte 0 -High byte E - Low byte H - High byte L - Low byte

Stores upper eight bits of memory address for vectored interrupt processing.

Provides user-transparent dynamic memory refresh. Automatically incremented and placed on the address bus during each instruction fetch cycle.

Used for indexed addressing.

Used for indexed addressing

Holds address of the top of the stack. See Push or Pop in instruction set.

Holds address of next instruction.

Set or reset to indicate interrupt status (see Figure 4).

Reflect Interrupt mode (see Figure 4).

to the selected one of eight restart locations in page zero of memory. Unlike the 80S0, the Z80 CPU responds to the Call instruction with only one interrupt acknowledge cycle followed by two memory read cycles.

Mode 1 Interrupt Operation. Mode 1 operation is very similar to that for the NMI. The principal difference is that the Mode 1 interrupt has only one restart location, 003SH.

Mode 2 Interrupt Operation: This interrupt mode has been designed to most effectively utilize the capabilities of the Z80 microprocessor and its associated peripheral family.The interrupting peripheral device selects the starting address of the interrupt service routine. It does this by placing an 8- bit vector on the data bus during the interrupt acknowledge cycle. The CPU forms a pOinter using this byte as the lower 8 bits and the contents of the I register as the upper 8 bits.

This points to an entry in a table of addresses for interrupt service routines. The CPU then jumps to the routine at that

7

(11)

address. This flexibility in selecting the interrupt service routine address allows the peripheral device to use several different types of service routines. These routines may be located at any available location in memory. Since the interrupting device supplies the low-order byte of the 2-byte vector, bit 0 (Aol must be a zero.

I Interrupt Enable/Disable Operation. Two flip·flops, IFF1 and IFF2, referred to in the register description, are used to signal the CPU interrupt status. Operation of the two flip·flops is described in Table 2. For more details, refer to the Z80 CPU Technical Manual (03-0029·01) and Z80 Assembly Language Programming Manual (03·0002-01).

Table 2. State of Flip·Flops Action

CPU Reset

01 instruction execution EI instruction execution LO A, I instruction execution LO A,R instruction execution Accept NMI

RETN instruction execution

INSTRUCTION SET

The microprocessor has one of the most powerful and versatile instruction sets available in any S·bit micro·

processor. It includes such unique operations as a block move for fast, efficient data transfers within memory, or between memory and 110. It also allows operations on any bit in any location in memory.

The following is a summary of the instruction set which shows the assembly language mnemonic, the operation, the flag status, and gives comments on each instruction. For an explanation of flag notations and symbols for mnemonic tables, see the Symbolic Notations section which follows these tables. The Z80 CPU Technical Manual (03-0029·01), the Programmer's Reference Guide (03·0012·03), and Assembly Language Programming Manual (03·0002·01) contain significantly more details for programming use.

The instructions are divided into the following categories:

o S·bit loads o 16·bit loads

o Exchanges, block transfers, and searches o S·bit arithmetic and logic operations o General·purpose arithmetic and CPU control o 16·bit arithmetic operations

o Rotates and shifts

8

IFF1 IFF2 Comments 0 0 Maskable interrupt

. INT disabled 0 0 Maskable interrupt

INT disabled Maskable interrupt

INT enabled I FF2 -+ Parity flag I FF2 -+ Parity flag 0 Maskable interrupt

INT disabled IFF2 IFF2 -+ IFF1 at

completion of an NMI service

routil)e.

o Bit set, reset, and test operations o Jumps

o Calls, returns, and restarts o Input and output operations

A variety of addressing modes are implemented to permit efficient and fast data transfer between various registers, memory locations, and input/output devices. These addressing modes include:

o Immediate

o Immediate extended o Modified page zero o Relative

o Extended o Indexed o Register o Register indirect o Implied oBit

(12)

8-BIT LOAD GROUP

Symbolic Flags Opcode No. of No. of M No. ofT

Mnemonic Operation S Z H PNN C 76 543 210 Hex Bytes Cyclea States Comments

LOr. r' r-r'

· ·

^X

·

^X

·

⁰¹ ^r' ⁴ ^{r, ('} ^Reg.

LOr, n r .... n

· ·

^X

·

^X

·

⁰⁰^{.... n-+}¹¹⁰ ² ² ⁷ ⁰⁰⁰001 ^BC

LOr, (HL) r .... (HL)

· ·

^X

·

^X

·

⁰¹ ¹¹⁰ ¹ ² ⁷ ⁰¹⁰ ⁰

LOr, (IX+d) r .... (IX+d)

· ·

^X

·

^X

· · ·

¹¹01 ⁰¹¹ ¹⁰¹110 ^DO ³ ⁵ ¹⁹ ⁰¹¹100 ^EH

.... d-+ 101 L

LO r, (IY +d) r .... (IY+d)

· ·

^X

·

^X

· · ·

01 ¹¹ ¹¹¹ ¹⁰¹110 ^FO ³ ⁵ ¹⁹ ¹¹¹ ^A .... d-+

LO(HL), r (HL) .... r

· ·

^X

^·

^X

·

⁰¹ ¹¹⁰ ² ⁷

LO(IX+d), r (IX+d) .... r

· ·

^X

·

^X

·

¹¹01 ⁰¹¹110 ¹⁰¹ ^DO ³ ⁵ ¹⁹ .... d-+

LO (IY +d), r (IY+d) .... r

· ·

X • . X

· · ·

₀₁¹¹ ¹¹¹₁₁₀ ¹⁰¹ ^FD ³ ⁵ ¹⁹

.... d-+

LO(HL), n (HL) .... n

• ·

^X

·

^X

^• · ^•

⁰⁰^{.... n-+}^{110 110} ³⁶ ² ³ ¹⁰

LO(IX+d), n (IX+d) .... n

· ·

^X

·

^X

·

¹¹00 ⁰¹¹110 110 ¹⁰¹ ^DO36 ⁴ ⁵ ¹⁹ .... d-+

.... n-+

(13)

8·BIT LOAD GROUP

(Continued)

Symbolic Flags Opcode No.ot No.ofM No. ofT

Mnemonic Operation S Z H PNN C 76 543 210 Hex Bytes Cycles States Comments LO(IY+d), n (IY+d)-n

• •

^X

•

^X

• • •

¹¹ ¹¹¹ ¹⁰¹ ^FD ⁴ ⁵ ¹⁹

00 110 110 36 - d - - n -

LOA, (BC) A-(BC)

•

• ,X

·

^X

· ^{• •}

⁰⁰ ⁰⁰¹ ⁰¹⁰ ^OA ² ⁷

LDA, (DE) A+-(DE)

• ·

^X

^•

^X

^{• • •}

⁰⁰ ⁰¹¹ ⁰¹⁰ ^lA ¹ ² ⁷

LD A. (nn) A-(nn)

• •

^X

•

^X

• • ·

⁰⁰- n -^{111 010} ^3A ³ ⁴ ¹³ - n -

LO(BC),A (BC)+-A

• ·

^X

·

^X

·

⁰⁰ ^{000 010} ⁰² ² ⁷

LD(DE),A (DE)-A

• ·

^X

^•

^X

· ^{• •}

⁰⁰ ^{010 010} ¹² ² ⁷

LD(nn),A (nn)-A

· ^•

^X

^•

^X

^{• • •}

⁰⁰- n -^{110 010} ³² ³ ⁴ ¹³ - n -

LDA,I A-I X 0 X IFF 0

·

01 ¹¹ 010 111 ¹⁰¹ ¹⁰¹ ^ED57 ^.2 ² ⁹

LDA,R A-R X 0 X IFF 0

•

¹¹ ¹⁰¹ ¹⁰¹ ^ED ² ² ⁹

01 011 111 5F

LDI,A I-A

• ·

^X

^•

^X

^{• • •}

¹¹01 000 111 ¹⁰¹ ¹⁰¹ ^ED47 ² ² ⁹ LDR,A R-A

• ·

^X

·

^X

· ^• ·

¹¹01 001 ¹⁰¹ ¹⁰¹111 ^ED4F ² ² ⁹ NOTE: IFF, the content of the interrupt enable flip·flop, (IFF2l, is copied into the PN flag.

16·BIT LOAD GROUP

Symbolic Flags Opcode No. of No. of M No. ofT

Mnemonic Operation S Z H PNN C 76 543 210 Hex Bytes Cycles States Comments

LDdd, nn dd +- nn

• •

^X

•

^X

• • •

⁰⁰ ^{ddO 001} ³ ³ ¹⁰ ^dd ^Pair

+-n- 00 BC

+-n- 01 DE

LD IX, nn IX+-nn

• •

^X

•

^X

• • •

¹¹ ⁰¹¹ ¹⁰¹ ^DD ⁴ ⁴ ¹⁴ ¹⁰ ^HL

00 100 001 21 11 SP

- n - .... n;+

LD IY, nn IY +- nn

• •

^X

•

^X

· ^{• •}

¹¹00 ¹¹¹100 001 ¹⁰¹ ^FD21 ⁴ ⁴ ¹⁴ - n -

+-n-

LD HL, (nn) H +-(nn+ 1) L +-(nn)

· ·

^X

^•

^X

^{• •} ·

⁰⁰+-n-^{101 010} ^2A ³ ⁵ ¹⁶ +-n-

LDdd, (nn) ddH +-(nn+ 1) ddl +- (nn)

• •

^X

•

^X

• · ^•

01 ¹¹ ¹⁰¹ddl 011 ¹⁰¹ ^ED ⁴ ⁶ ²⁰ +-n-

+-n-

NOTE: (PAIR)H, (PAIR)l refer to high order and low order eight bits ofthe register pair respectively. e.g., BCl = C, AFH = A.

10

(14)

16-BIT LOAD GROUP

(Continued)

Symbolic Flags Opcode No. of No. of M No. of T

Mnemonic Operation S Z H PNN C 76 543 210 Hex Bytes Cycles States Comments LD IX, (nn) IXH -(nn+l) IXL -(nn)

• ·

^X

·

^X

^{• • •}

00 ¹¹ ⁰¹¹101 010 ¹⁰¹ ^DO2A ⁴ ⁶ ²⁰

- n - - n -

LD IY,(nn) IYH -(nn+l) IYL -(nn)

· ·

^X

^•

^X

· ^{• •}

¹¹00 ¹¹¹101 010 ¹⁰¹ ^FD2A ⁴ ⁶ ²⁰ - n -

- n -

LD(nn), HL (nn+l)-H

• •

^X

•

^X

• • •

⁰⁰ ^{100 010} ²² ³ ⁵ ¹⁶

(nn)-L - n -

- n -

LD(nn), dd (nn+l)-ddH (nn)-ddL

· ^•

^X

^•

^X

^{• • •}

¹¹01 ddO 011 ¹⁰¹ ¹⁰¹ ^ED ⁴ ⁶ ²⁰ - n -

- n -

LD(nn), IX (nn+l)-IXH (nn)-IXL

· ·

^X

^•

^X

^{• •} ·

¹¹00 ⁰¹¹100 010 ¹⁰¹ ^DO22 ⁴ ⁶ ²⁰ .... n-+

- n -

LD(nn),IY (nn+l)-IYH (nn)-IYL

· ^•

^X

^•

^X

^{• • •}

¹¹00 100 010 ¹¹¹ ¹⁰¹ ^FD22 ⁴ ⁶ ²⁰ - n -

- n -

LDSP, HL SP-HL

• •

^X

•

^X

• · ^•

¹¹ ¹¹¹ ⁰⁰¹ ^F9 ⁶

LDSP,IX ,SP-IX

• •

^X

•

^X

• • •

¹¹ ⁰¹¹ ¹⁰¹ ^DO ² ² ¹⁰

11 111 001 F9

LDSP,IY SP-IY

• •

^X

•

^X

• • •

¹¹ ¹¹¹ ¹⁰¹ ^FD ² ² ¹⁰

11 111 001 F9 qq Pair

PUSHqq (SP-2)-qqL •

•

^X

•

^X

• • •

¹¹ ^{qqO 101} ³ ¹¹ ⁰⁰

Be

(SP-l)-qqH 01 DE

SP-SP -2 10 HL

PUSH IX (SP-2)-IXL

• •

^X

•

^X

• • •

¹¹ ⁰¹¹ ¹⁰¹ ^DO ² ⁴ ¹⁵ ¹¹ ^AF

(SP-l)-IXH 11 100 101 E5

SP-SP -2

PUSH IY (SP-2)-IYL (SP-l)-IYH

· ^•

^X

^•

^X

^{• • •}

¹¹11 ¹¹¹100 101 ¹⁰¹ ^FDE5 ² ⁴ ¹⁵ SP-SP -2

POPqq qqH-(SP+l) • qqL-(SP)

•

^X

•

^X

• · ^•

¹¹ ^{qqO 001} ³ ¹⁰

SP-SP +2

POP IX IXH-(SP+l) •

•

^X

•

^X

• • •

¹¹ ⁰¹¹ ¹⁰¹ ^DO ² ⁴ ¹⁴

IXL -(SP) 11 100 001 El

SP-SP +2

POPIY IYH -(SP+l) IYL -(SP)

· ^•

^X

^•

^X··

^{• •}

¹¹11 ¹¹¹100 001 ¹⁰¹ ^FDEl ² ⁴ ¹⁴ SP-SP +2

NOTE: {PAIR)H' {PAIR)L reterto high order and low order eight bitsotthe register pair respectively, e.g., BCL = C, AFH = A.

(15)

EXCHANGE, BLOCK TRANSFER, BLOCK SEARCH GROUPS

Symbolic Flags Opcocle No. of No. of M No. ofT

EX DE, HL DE-HL

• •

^X

•

^X

• • •

¹¹ ^{101 011} ^EB ⁴

EXAF,AF' AF-AF'

• •

^X

•

^X

• • •

⁰⁰ ⁰⁰¹ ⁰⁰⁰ ⁰⁸ ⁴

EXX BC-BC'

• •

^X

•

^X

• • •

¹¹ ^{011 001} ^D9 ⁴ Register bank

DE-DE' and auxiliary

HL-HL' register bank

exchange EX (SP), HL H-(SP+l)

• •

^X

•

^X

• • •

¹¹ ^{100 011} ^E3 ⁵ ¹⁹

L-(SP)

EX (SP), IX IXH-(SP+l) •

•

^X

•

^X

• • •

¹¹ ⁰¹¹ ¹⁰¹ ^DD ² ⁶ ²³

IXL -(SP) 11 100 011 E3

EX (SP), IY IYH-(SP+l) • IYL-(SP)

·

^X

^•

^X

^• ^{• •}

¹¹11 ¹¹¹100 011 ¹⁰¹ ^FDE3 ² ⁶ ²³

<D

LDI (DE)-(HL)

• •

^{X 0 X}

*

⁰

^•

¹¹ ¹⁰¹ ¹⁰¹ ^ED ² ⁴ ¹⁶ Load (HL) into

DE -DE+l 10 100 000 AO (DE), increment

HL-HL+l the pointers and

BC-BC-l decrement the

byte counter

®

^(BC)

LDIR (DE)-(HL)

• •

X 0 X 0 0

•

¹¹ ¹⁰¹ ¹⁰¹ ^ED ² ⁵ ²¹ IfBC""O

DE -DE+l 10 110 000 BO 2 4 16 IfBC = 0

HL-HL+l BC-BC-l Repeat until BC

=

0

<D

LDD (DE)-(HL)

• •

^{X 0 X}

*

⁰

^•

¹¹ ¹⁰¹ ¹⁰¹ ^ED ² ⁴ ¹⁶

DE-DE-l 10 101 000 A8

HL-HL-l BC-BC-l

®

LDDR (DE)-(HL)

• •

X 0 X 0 0

•

¹¹ ¹⁰¹ ¹⁰¹ ^ED ² ⁵ ²¹ IfBC;&O

DE-DE-l 10 111 000 B8 2 4 16 IfBC

=

0

HL-HL-l BC-BC-l Repeat until BC

=

0

® <D

CPI A - (HL)

* *

^X ^X

*

¹

^•

¹¹ ¹⁰¹ ¹⁰¹ ^ED ² ⁴ ¹⁶

HL-HL+l 10 100 001 Al

BC-BC-l

NOTE:

CD

PN flag is 0 if the result of Be -1 = 0, otherwise PN =. 1.

(2) PN flag is 0 only at completion of instruction.

CID Z flag is 1 if A = HL , otherwise Z = o.

12

(16)

EXCHANGE, BLOCK TRANSFER, BLOCK SEARCH GROUPS (Continued)

Symbolic Flags Opcode No. of No. of M No. of T

Mnemonic Operation S Z H PIV N C 76 543 210 Hex Bytes Cycles States Comments

® <D

CPIR A - (HL)

t t

X X

t

1

·

¹¹ ¹⁰¹ ¹⁰¹ ^ED ² ⁵ ²¹ ^IfBC*OandA*(HL)

HL+-HL+1 10 110 001 B1 2 4 16 IfBC =Oor

BC+-BC-1 A = (HL)

Repeat until A = (HL) or BC = 0

® <D

CPD A - (HL) HL +- HL-1

t

^X ^X

t

¹

·

¹¹10 ¹⁰¹101 ¹⁰¹001 ^EDA9 ² ⁴ ¹⁶ BC+-BC-1

® <D

CPDR A - (HL)

t

^X ^X

t

¹

·

¹¹ ¹⁰¹ ¹⁰¹ ^ED ² ⁵ ²¹ IfBCi'Oand

A*(HL)

HL+-HL-1 10 111 001 B9 2 4 16 If BC = Oor

BC+- BC-1 'A = (HL)

Repeat until A = (HL) or BC = 0

NOTE: (j) PIV flag is 0 if the result of Be -1 = 0, otherwise PIV = 1.

®

PIV flag is 0 only at completion of instruction.

@ Z flag is 1 if A = (HL), otherwise Z = o.

8-BIT ARITHMETIC AND LOGICAL GROUP

Mnemonic Operation S Z H PIV N C 76 543 210 Hex Bytes Cycles States Comments

ADD A, r A+-A+r X X V 0 10 10001 r 1 1 4 Reg.

ADD A, n A+-A+n X X V 0 11 10001 110 2 2 7 000 B

+-n- 001 C

010 D

ADDA,(HL) A+-A+(HL) X X V 0 10 10001 110 2 7 011 E

ADD A, (IX + d) A+-A + (IX + d) X X V 0 11 011 101 DD 3 5 19 100 H

10 10001 110 101 L

+-d- 111 A

ADD A, (IY + d)A+-A+ (IY +d)

t

^; X ; X V 0 ; 11 111 101 FD 3 5 19 10 10001 110

+-d-

ADCA, s A+-A+s+CY

t

X X V 0 )0011 s is any of r, n,

SUBs A+-A-s

t

^X ^X ^V ¹⁰¹⁰¹ (HL),(IX+d),

SBCA, s A+-A-s-CY

t

X X V 1 lQTI] (IY+d)as

ANDs A+-A>s ; X 1 X P 0 0 11001 shown for ADD

ORs A+-A>s ; X 0 X P 0 0 [D]J instruction. The

XORs A +-Aes X 0 X P 0 0

ITQD

indicated bits

CPs A-s X ; X V 1 ;

[lli]

replace the

10001 inthe ADD set above.

13

(17)

8-BIT ARITHMETIC AND LOGICAL GROUP

(Continued)

Symbolic Flags Opcode No. of No.ofM No. ofT

INCr r-r+1 X X V 0

•

⁰⁰ ^r ¹¹⁰⁰¹ ⁴

INC (HL) (HL)-

(HL) + 1 X X V 0

•

⁰⁰ 110 11001 3 11

INC (IX + d) (IX+d)- X X V 0

•

¹¹ ⁰¹¹ ¹⁰¹ ^DD ³ ⁶ ²³

(IX+d)+1 00 110 11001

- d -

INC (IY+d) (IY+d)- t t X t X V 0

•

¹¹ ¹¹¹ ¹⁰¹ ^FD ³ ⁶ ²³

(IY+d)+1 00 110 11001

- d -

DECm m-m-1 t t X t X V 1

• IIQD

I

NOfE: m is any of r. (HL), (IX + d), (IY + d) as shown for INC. DEC same format and states as INC. Replace

[]]Q]

w~h

DQ!]

in opcode.

GENERAL-PURPOSE ARITHMETIC AND CPU CONTROL GROUPS 9

Symbolic Flags Opcode No. of No.ofM No.ofT

DAA @ X X P

•

⁰⁰ ^{100 111} ²⁷ ⁴ Decimal adjust

accumulator.

CPL A-A

• •

^X ^X

•

¹

•

⁰⁰ ^{101 111} ^2F ⁴ Complement

accumulator (one's complement).

NEG A-O-A t t X t X V 1 t 11 101 101 ED 2 2 8 Negateacc.

01 000 100 44 (two's

complement).

CCF CY-CY

• •

^{X X X}

•

⁰ ⁰⁰ ^{111 111} ^3F ^{• 1} ⁴ Complement

carry flag.

SCF CY-1

• •

^{X 0 X}

•

⁰ ⁰⁰ ^{110 111} ³⁷ ⁴ Set carry flag.

NOP No operation

• •

^X

•

^X

• • •

⁰⁰ ^{000 000} ⁰⁰ ⁴

HALT CPU halted

• •

^X

•

^X

• • •

⁰¹ ^{110 110} ⁷⁶ ⁴

DI* IFF-O

• •

^X

•

^X

• • •

¹¹ ^{110 011} ^F3 ⁴

EI* IFF-1

• •

^X

•

^X

• · ^•

¹¹ ^{111 011} ^FB ¹ ⁴

IMO Set interrupt

• • ^X •

^X

• • •

¹¹ ^{101 101} ^ED ² ² ⁸

mode 0 01 000 110 46

IM1 Set interrupt

• •

^X

•

^X

• • •

¹¹ ^{101 101} ^ED ² ² ⁸

mode 1 01 010 110 56

1M2 Set interru pt

• •

^X

•

^X

• • •

¹¹ ^{101 101} ^ED ² ² ⁸

mode 2 01 011 110 5E

NOfES: @ converts accumUlator content into packed BCD following add or subtract with packed BCD operands.

IFF indicates the interrupt enable flip-flop.

eY indicates the carry flip-flop.

*

indicates interrupts are not sampled at the end of EI or 01.

14

(18)

16-BIT ARITHMETIC GROUP

Mnemonic Opemtion S Z H PNN C 76 543 210 Hex Bytes Cycles States Comments

ADDHL, ss HL - HL+ss

· ·

^{X X X}

·

⁰ ⁰⁰ ^ssl ⁰⁰¹ ³ ¹¹ ^ss00 ^Reg.BC

ADC HL, ss HL- 01 DE

HL+ss+CY

: :

^{X X X} V 0

:

¹¹ ¹⁰¹ ¹⁰¹ ED 2 4 15 10 HL

01 ss1 010 11 SP

SBC HL, ss HL-

HL-ss-CY X X X V 11 101 101 ED 2 4 15

01 ssO 010

ADD IX, pp IX-IX+pp

· ·

^{X X X}

·

⁰ 01 ¹¹ ⁰¹¹pp1 001 ¹⁰¹ ^DD ² ⁴ ¹⁵ ^pp00 BC ^Reg.

01 DE 10 IX 11 SP ADD IY, rr IY -IY+rr X X X

·

⁰ ¹¹00 ¹¹¹rr1 001 ¹⁰¹ ^FD ² ⁴ ¹⁵ ^rr00 ^Reg.BC

INCss ss-ss+1

· ·

^X

^·

^X

·

⁰⁰ ^ssO ⁰¹¹ ¹ ⁶ ⁰¹ ^DE

INCIX IX-IX+1

· ·

^X

·

^X

·

00 ¹¹ ⁰¹¹100 011 ¹⁰¹ ^DO23 ² ² ¹⁰ ¹⁰11 ^IYSP INCIY IY-IY+1

· ·

^X

·

^X

·

00 ¹¹ ¹¹¹100 011 ¹⁰¹ ^FD23 ² ² ¹⁰

DECss ss-ss-1

· ·

^X

·

^X

·

⁰⁰ ^ss1 ⁰¹¹ ¹ ⁶

DEC IX IX-IX-1

· ·

^X

·

^X

·

00 ¹¹ ⁰¹¹101 011 ¹⁰¹ ^DD2B ² ² ¹⁰ DECIY IY-IY-1

· ·

^X

·

^X

·

¹¹00 ¹¹¹101 011 ¹⁰¹ ^FD2B ² ² ¹⁰

ROTATE AND SHIFT GROUP

Mnemonic Opemtion S Z H PNN C 76 543 210 Hex Bytes Cycles States Comments

RLCA

§]~J · ·

^{X 0 X}

·

⁰

^:

⁰⁰ ^{000 111} ⁰⁷ ⁴ Rotate left

A

circular accumulator.

RLA

L§]=EJ=J · ·

^{X 0 X}

·

⁰

^:

⁰⁰ ^{010 111} ¹⁷ ⁴ Rotate left

A accumulator.

RRCA

~~ · ·

^{X 0 X}

·

⁰

^:

⁰⁰ ⁰⁰¹ ¹¹¹ ^OF ⁴ Rotate right

A

circular accumulator.

RRA

L~@ · ·

^{X 0 X}

^•

⁰

^:

⁰⁰ ⁰¹¹ ¹¹¹ ^1F ⁴ Rotate right

A

accumulator.

15

(19)

ROTATE AND SHIFT GROUP

(Continued)

Symbolic Flags Opcode No. of No.ofM No.ofT

Mnemonic Operation S Z H PNN C 76 543 210 Hex Bytes Cycles States Commenta

RLCr ; ; X 0 X P O· ; 11 001 011 CB 2 2 8 Rotate left

00 10001 circular

register r.

RLC(HL) ; X 0 X P 0

*

¹¹₀₀ ^{001 011}_{000 110} ^CB ² ⁴ ¹⁵ ₀₀₀ ^Reg.B

Cill~:J

001 C

RLC(IX+d) ; ; X 0 X P 0 ; 11 011 101 DD 4 6 23 010 D

r,(HL),(IX + d),(IY + d) 11 001 011 CB 011 E

- d - 001 H

00 10001 110 101 L

111 A

RLC(IY+d) ; ; X 0 X p 0 ; 11 111 101 FD 4 6 23

11 001 011 CB

- d - Instruction

00 10001 110 format and

RLm

~t

^X ⁰ ^{X P} ⁰ ^; 10101 states are as

m = r,(HL,(IX + d),(IY + d) shown for

RLCs. To form

RRCm

LE:i}lCill

; ; X 0 X P 0 ; 10011 newopcode

m = r,(HL),(IX + d),(lY + d) replace

I

0001,

orRLCswith shown code.

RRm

LED=[§J

; ; X 0 X p 0 ; [QIT]

m = r,(HL),(IX + d),(IY + d)

SLAm ~

... o*

^; ^X 0 X ^p 0 ; 11001 m = r,(HL),(IX + d),(IY + d)

SRAm

~

^{; ;} ^X ⁰ ^X ^p ⁰ ^;

^IlQI]

m = r,(HL),(IX + d),(IY + d)

SRLm o+~Cill ; ; X 0 X p 0 ;

ITill

m = r,(HL),(IX + d),(IY + d)

RLD I

7~4

I 3;0 I I

~-[lio

I ^{; ;} ^X 0 X p 0

•

¹¹ ¹⁰¹ ¹⁰¹ ^ED ² ⁵ ¹⁸ Rotate digit

(HlJ 01 101 111 6F left and

right between theaccumu- latorand

~

location (HL).

RRD ; ; X 0 X P 0

•

¹¹ ¹⁰¹ ¹⁰¹ ^ED ² ⁵ ¹⁸ The content

(HL) 01 100 111 67 of the upper

half of the accumulator is unaffected.

16

(20)

BIT SET, RESET AND TEST GROUP

Symbolic Flag. Opcode No. of No. of M No. ofT

Mnemonic Opel'8tloll S Z H PNN C 78 543 210 Hex Byte. Cycle. State. eommenta

BITb,r Z-rb X X X X 0

•

¹¹ ^{001 011} ^CB ² ² ⁸ ^Reg.

01 b r 000 B

BIT b, (HL) Z-(HL)b X X X X 0

•

¹¹ ^{001 011} ^CB ² ³ ¹² ^{001 C}

01 b 110 010 0

BITb,(IX+d)b Z-(IX+d)b X X X X 0

•

¹¹ ⁰¹¹ ¹⁰¹ ^DO ⁴ ⁵ ²⁰ ⁰¹¹ ^E

11 001 011 CB 100 H

- d - 101 L

01 b 110 111 A

b Bit Tested BIT b, (IY + d)b Z - (IY + d)b X

*

X 1 X X 0

·

¹¹11 ^{111 101}001 011 ^FOCB ⁴ ⁵ ²⁰ ^{000 0}001

- d - 010 2

01 b 110 011 3

SETb,r rb- 1

• •

^X

•

^X

• · ..

¹¹ ⁰⁰¹ ⁰¹¹ ^CB ² ² ⁸ ¹⁰⁰ ⁴

!ITI

^b ^r ^{101 5}

SETb,(HL) (HL)b- 1

• •

^X

•

^X

• • •

¹¹ ⁰⁰¹ ⁰¹¹ ^CB ² ⁴ ¹⁵ ¹¹⁰ ⁶

!ITI

^b ¹¹⁰ ¹¹¹ ⁷

SET b, (IX + d) (IX + d)b -1

• •

^X

•

^X

• • •

¹¹ ⁰¹¹ ¹⁰¹ ^DO ⁴ ⁶ ²³

11 001 011 CB - d -

!ITI

^b ¹¹⁰

SETb, (IY+d) (IY+d)b-1

• •

^X

•

^X

• • •

¹¹ ^{111 101} ^FO ⁴ ⁶ ²³

11 001 011 CB - d -

!ITI

^b ¹¹⁰

RESb,m mb- O

• •

^X

•

^X

• • • ^[lQ]

To form new

m=r,(HL), opcode replace

(IX + d), (IY + d)

!TIl

of SET b, s

withlIID Flags and time states for SET instruction.

NOTE: The notation mb indicates location m. bit b (0 107).

17

(21)

JUMP GROUP

Mnemonic Operation S Z H PNN C 76 543 210 Hex Bytes ,Cycles States Comments JP nn PC-nn

• •

^X

•

^X

• • ·

¹¹ - n -^{000 011} ^C3 ³ ³ ¹⁰ ^cc000 NZ (non-zero) ^Condition

- n - 001 Z(zero)

JPcc, nn II condition cc •

•

^X

•

^X

• • •

¹¹ ^cc ⁰¹⁰ ³ ³ ¹⁰ 010 NC (non-carry)

is true PC-nn, - n - 011 C(carry)

otherwise - n - 100 PO (parity odd)

continue 101 PE (parity even)

JRe PC-PC+e

• •

^X

•

^X

• • •

⁰⁰ ⁰¹¹ ⁰⁰⁰ ¹⁸ ² ³ ¹² 110 P (sign positive)

- e - 2 - 111 M (sign negative)

JRC,e IIC=O,

• •

^X

•

^X

• • •

⁰⁰ ^{111 000} ³⁸ ² ² ⁷ II condition not met.

continue - e - 2 -

IIC=1, 2 3 12 II condition is met.

PC":PC+e

JRNC, e IFC=1,

• •

^X

•

^X

• • •

⁰⁰ ^{110 000} ³⁰ ² ² ⁷ II condition not met.

continue - e - 2 -

IIC=O, 2 3 12 II condition is met.

PC-PC+e

JPZ,e IIZ=O

• •

^X

•

^X

• • •

⁰⁰ ^{101 000} ²⁸ ² ² ⁷ II condition not met.

continue - e - 2 -

IIZ=1, 2 3 12 II condition is met.

PC-PC+e

JRNZ,e IIZ=1,

• •

^X

•

^X

• • •

⁰⁰ ^{100 000} ²⁰ ² ² ⁷ II condition not met.

continue - e - 2 -

IIZ=O, 2 3 12 II condition is met.

PC-PC+e

JP(HL) PC-HL

• •

^X

•

^X

• • •

¹¹ ^{101 001} ^E9 ⁴

JP(IX) PC-IX

• •

^X

•

^X

• • •

¹¹ ⁰¹¹ ¹⁰¹ ^DD ² ² ⁸

11 101 001 E9

JP(IY) PC-IV

• •

^X

•

^X

• • •

¹¹ ¹¹¹ ¹⁰¹ ^FD ² ² ⁸

11 101 001 E9

DJNZ,e 8-8-1

• •

^X

•

^X

• • •

⁰⁰ ^{010 000} ¹⁰ ² ² ⁸ ¹¹⁸⁼⁰

118=0, - e - 2 -

continue

118;60, 2 3 13 118;60.

PC-PC+e

NOTES: e represents the extension in the relative addressing mode, e is a signal two's complement number inthe range < -126,129>,

e - 2 in the opcode provides an effective address of pc + e as PC is incremented by 2 prior to the addition of e,

18

(22)

CALL AND RETURN GROUP

Mnemonic Operation S Z H PNN C 76 543 210 Hex Bytes Cycles States Comments CALLnn (SP-1) .... PCH • (SP-2) .... PCl

•

^X

•

^X

• • ·

¹¹ .... n .... ⁰⁰¹ ¹⁰¹ ^CD ³ ⁵ ¹⁷

PC .... nn, .... n ....

CALL cC,nn If condition

· ·

^X

^·

^X

· · ·

¹¹ ^cc ¹⁰⁰ ³ ³ ¹⁰ II cc is false.

cc is false .... n ....

continue, .... n .... 3 5 17 IIcc is true.

otherwise same as CALLnn

RET PCl .... (SP) PCH .... (SP+1)

· ^•

^X

·

^X

·

¹¹ ^{001 001} ^C9 ³ ¹⁰

RETcc II condition

• •

^X _{• X}

• • •

¹¹ ^cc ⁰⁰⁰ ⁵ II cc is false.

cc is false

continue, 3 11 IIcc is true.

otherwise

same as RET cc Condition

000 NZ (non·zero) 001 Z(zero) 010 NC (non·carry) RETI Return from

• •

X • X

• • ·

¹¹ ^{101 101} ^ED ² ⁴ ¹⁴ 011 C(carry)

interrupt 01 001 101 4D 100 PO (parity odd)

RETNl Return from

• •

^X

·

^X

^{• • •}

¹¹ ^{101 101} ^ED ² ⁴ ¹⁴ 101 PE (parity even)

non·maskable 01 000 101 45 110 P (sign positive)

interrupt 111 M (sign negative)

RSTp (SP-1)-PCH

•

• X • X

• • •

¹¹ ¹¹¹ ³ ¹¹ ^t ^P

(SP-2) .... PCl 000 OOH

PCH .... O 001 OBH

PCl .... p 010 10H

011 1BH 100 20H 101 2BH 110 30H 111 3BH NOTE: 1 RETN loads IFF2 .... IFFl

(23)

INPUT AND OUTPUT GROUP

Mnemonic Operation S Z H PNN C 76 543 210 Hex Bytes Cycles States Comments INA,(n) A-(n) • • X • X •

• •

¹¹ ⁰¹¹ ⁰¹ ^DB ² ³ ¹¹ ntoAo"'A7

- n - flee;to,Ae"'AI5

IN r, (e) r-(C) X X P

o •

¹¹ ^{101 101} ^ED ² ³ ¹² etoAo"'A7

il r= 1100nly 01 000 BtoAs"'A15

thellagswill be affected

<D

INI (HL)-(C) X

*

X X X X 1 X 11 101 101 ED 2 4 16 etoAo"'A7

B-B-1 10 100 010 A2 BtoAs"'AI5

HL-HL+1

®

INIR (HL)-(C) X 1 X X X X 1 X 11 101 101 ED 2 5 21 eto,Ao"'A7

B-B-1 10 110 010 B2 (IIB;'O) BtoAe"'A15

HL-HL+1 2 4 16

Repeat until (IIB=O)

B=O

<D

IND (HL)-(C) X

*

X X X X 1 X 11 101 101 ED 2 4 16 etoAo"'A7

B-B-1 10 101 010 AA BtoAs"'A15

HL-HL-1

®

INDR (HL)-(C) X 1 X X X X 1 X 11 101 101 ED 2 5 21 etoAo"'A7

B-B-1 10 111 010 BA ,IIB;'O) BtoAe"'A15

HL-HL-1 2 4 16

Rapeatuntil (IIB=O)

B=O

OUT (n), A (n) - A

•

• X • X •

• •

¹¹ ^{010 011} ^D3 ² ³ ¹¹ ntoAo"'A7

- n - flee. to

As '"

A15

OUT (e), r (C) - r

•

• X • X •

• •

¹¹ ^{101 101} ^ED ² ³ ¹² etoAo"'A7

01 001 BtoAe"'A15

<D

OUTI (C)-(HL) X t X X X X 1 X 11 101 101 ED 2 4 16 etoAo"'A7

8-B-1 10 100 011 A3 BtoAe"'A15

HL-HL+1

®

anR (C)-(HL) X 1 X X X X 1 X 11 101 101 ED 2 5 21 CtoAo"'A7

B-B-1 10 110 011 B3 (IIB;'O) BtoAa"'A15

HL-HL+.1 2 4 16

Rapaatuntil (IIB=O)

8=0

aUTO (C)-(HL) X

CD *

X X X X 1 X 11 101 101 ED 2 4 16 CtoAo"'A7

B-B-1 10 101 011 AB BtoAa"'A15

HL-HL-l

OTDR (C)-(HL) X 1 X X X X 1 X 11

®

101 101 ED 2 5 21 CtoAo"'A7

B-B-l 10 111 011 (IIB;'O) BtoAs"'AI5

HL-HL-1 2 4 16

Repeat until (IIB=O)

8=0

NOTES:

CD

II the result of B-1 is zero, the'Z flag is set; otherwise it is reset.

<?J

Z flag is set upon instruction completion only.

20

Table of Contents