HAL Id: tel-03132510
https://tel.archives-ouvertes.fr/tel-03132510
Submitted on 5 Feb 2021
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Investigation of electrostatic doping devices and applications in FD-SOI technologies
Kyunghwa Lee
To cite this version:
Kyunghwa Lee. Investigation of electrostatic doping devices and applications in FD-SOI technologies.
Micro and nanotechnologies/Microelectronics. Université Grenoble Alpes, 2019. English. �NNT : 2019GREAT041�. �tel-03132510�
THÈSE
Pour obtenir le grade de
DOCTEUR DE LA COMMUNAUTE UNIVERSITE GRENOBLE ALPES
Spécialité : NANO ELECTRONIQUE ET NANO TECHNOLOGIES
Arrêté ministériel : 25 mai 2016
Présentée par
Kyunghwa LEE
Thèse dirigée par Maryline BAWEDIN, Maître de conférences, Grenoble INP et codirigée par Sorin CRISTOLOVEANU, Directeur de Recherche, CNRS
préparée au sein du Laboratoire Institut de Microélectronique, Electromagnétisme et Photonique - Laboratoire
d'Hyperfréquences et de Caractérisation
dans l'École Doctorale Electronique, Electrotechnique, Automatique, Traitement du Signal (EEATS)
Étude des dispositifs à dopage
électrostatique et des applications dans les technologies FD-SOI
Investigation of electrostatic doping devices and applications in FD-SOI technologies
Thèse soutenue publiquement le 10 juillet 2019, devant le jury composé de :
Monsieur, Gérard GHIBAUDO
Directeur de Recherche, CNRS, Président
Monsieur, Olivier BONNAUD
Professeur Emérite, Université de Rennes 1, Rapporteur
Monsieur, Ray HUETING
Associate professor, University of Twente, Rapporteur
Monsieur, Carlos SAMPEDRO
Professeur, University of Granada, Examinateur
Madame, Maryline BAWEDIN
Maître de conférences, Grenoble INP, Directeur de thèse
Monsieur, Sorin CRISTOLOVEANU
Directeur de Recherche, CNRS, Co-encadrant de thèse
Acknowledgements
This 3 years journey would not have been possible without the dedicated support of such wonderful people around me. First or foremost, I would like to thank the members of the jury for the time spent to evaluate this work and attend my Ph.D. defense. Thank you, Prof. Olivier Bonnaud, Prof.
Ray Hueting, Prof. Carlos Sampedro and Prof. Gérard Ghibaudo.
I would like to express my deepest sense of gratitude to my supervisors, for their patient guidance, enthusiastic encouragement and useful critiques of this research work. My flourishing three year Ph.D. life had begun thanks to you, Maryline. During the project, not only the knowledge I acquired but also lots of skills in professional meetings are very precious. I learned how to deal with the problem and I could have never met various people in academia and industry without this opportunity. Words like thank you are not enough to say how I feel to you, Sorin. Your support in many aspects of my life and studies encouraged me a lot during my stay in France. I would not have finished successfully my Ph.D. without you.
I am happy and deeply grateful for spending cool and funny moments in the office 217 with Mukta, my best chatty friend, I could never forget the time we spent in our office next to each other.
Hyung-jin has been always there encouraging me as a Korean mafia colleague. The life and soul of our office -Dimitris, Lici, Miltos and Namanu- the long hours in the lab were always delightful and fun thanks to you guys. Thank you, Elodie for your kindness to clumsy new-comer 3 years back. There are lots of more friends who shared my great time in IMEP-LAHC. Thank you all. Also, many thanks are due to Xavier and Martine for their valuable technical support and patience throughout the whole years.
Furthermore, I kindly thank for the help that I received from all the HR team members.
To all of my awesome friends in Grenoble: life here without you would not have been worth it. I cherish all the great memories with you all. Thank you for being with me whenever I was happy or sad. To my best friends who encouraged and cared about me long away from Korea or even visited me here: you were my drives and motivators of my life and it will always be.
Last but not least, I love my family who keeps supporting me and watching over by my side.
Mom and Dad, you have always tried to help and encourage me as if you got through 3 years in France with me. My sister and brother, thanks for cheering me up during my career. Photos of Coco sent from you were like rain for a drought.
Thank you all for being part of my life in France.
Contents
Abbreviations and Main Symbols ∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙ 6 Abstract/Résumé ∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙ 11 Introduction ∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙ 13 1. SOI technology ∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙ 15
1.1. State-of-arts and trends: MOSFETs ∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙ 15 1.2. Migration to FD-SOI ∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙ 16 1.3. FD-SOI technology ∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙ 17 2. Physical doping vs. Electrostatic doping ∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙ 19 2.1. Physical doping: Ion implantation ∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙ 19 2.2. Electrostatic doping ∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙ 20 3. Sharp-switching devices ∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙ 21 3.1. Tunnel FET (TFET) ∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙ 21 3.2. Impact ionization-MOSFET (I-MOS) ∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙ 22 3.3.Nano-electro-mechanical FET (NEM-FET) ∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙ 23 3.4. Ferroelectric-FET (Fe-FET) ∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙ 23 3.5. Band-modulation device: Z2-FET ∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙ 24 4. 1T-DRAM: Capacitorless Dynamic Random Access Memory ∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙ 25 4.1. State-of-the art: the need for new memory for Internet of Things (IoT) ∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙ 25 4.2. Conventional 1T+1C DRAM ∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙ 26 4.3. Resistive RAM (ReRAM) ∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙ 26 4.4. Spin Torque Transfer-RAM (STT-RAM) ∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙ 27
4.5. Floating-Body DRAMs (FB-DRAMs) ∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙ 28 4.5.1. Meta-stable DRAM (MSDRAM) ∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙ 28 4.5.2. A2RAM ∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙ 29 4.5.3. Z2 RAM (Z2-FET RAM) ∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙ 30 5. References ∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙ 31 Chapter 1. Electrostatic doping: The concept and related devices ∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙ 39 1.1. Introduction ∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙ 41 1.2. Electrostatic doping ∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙ 41 1.3. Why electrostatic doping? ∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙ 43 1.3.1. Semiconductor technology ∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙ 43 1.3.2. Electrostatic doping in FD-SOI technology ∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙ 44 1.4. Emerging material devices with electrostatic doping ∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙ 45 1.4.1. Carbon nanotube ∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙ 45 1.4.2. Graphene ∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙ 46 1.4.3. Silicon (Si) nanowires ∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙ 47 1.4.4. Two Dimensional (2D) materials ∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙ 48 1.5. FD-SOI devices with electrostatic doping ∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙ 48 1.5.1. Tunneling Field Effect Transistor (TFET) ∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙ 49 1.5.2. Lateral Double-diffused Metal Oxide Silicon (LDMOS) ∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙ 52 1.5.3. Impact ionization Metal Oxide Silicon (IMOS) ∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙ 53 1.5.4. Gated Diode merged NMOS (GDNMOS) ∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙ 53 1.5.5. Charge Plasma Diode ∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙ 54 1.5.6. Bipolar Charge Plasma Transistor ∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙ 54 1.6. Conclusion ∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙ 55
1.7. References ∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙ 55 Chapter 2. The Hocus-Pocus diode: Fabrication, device operation and applications ∙∙∙∙ 60 2.1. Introduction ∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙ 63 2.2. The Hocus-Pocus (HP) diode ∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙ 63 2.2.1 Device fabrication ∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙ 63 2.2.2 Principle of operation ∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙ 64 2.3. The virtual P-N diode ∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙ 65 2.3.1. Reverse current characteristics ∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙ 66 2.3.2. Forward current characteristics ∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙ 69 2.3.3. TCAD Simulation ∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙ 70 2.3.4. Asymmetric characteristics ∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙ 71 2.3.5. Semi-virtual P-N diode ∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙ 72 2.3.6. Esaki diode characteristics ∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙ 73 2.4. The virtual P-I-N diode ∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙ 79 2.4.1. Characteristics ∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙ 79 2.5 Other metamorphosis in HP diode ∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙ 80 2.5.1 TFET and Z2-FET ∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙ 80 2.6. Lifetime extraction in ultrathin film ∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙ 80 2.6.1. Lifetime extraction methods ∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙ 80 2.6.1.1. Deep depletion technique ∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙ 81 2.6.1.2. Photo-conductance decay technique ∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙ 82 2.6.2. Lifetime extraction method using HP diode ∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙ 83 2.6.2.1. Forward I-V characteristic ∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙ 83 2.6.2.2. Recombination and diffusion current ∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙ 86
2.6.2.3. Reverse Recovery Transient (RRT) Method ∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙ 87 2.6.2.3.1. The virtual P-N diode ∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙ 88 2.6.2.3.2. The virtual P-I-N diode ∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙ 91 2.6.2.4 Double gated P-I-N diode ∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙ 92 2.7. Conclusion ∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙ 93 2.8. References ∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙ 94 Chapter 3. Z2-FET: capacitorless 1T-DRAM and logic switch ∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙ 100 3.1. Introduction ∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙ 102 3.2. Physics in capacitorless 1T-DRAM Z2-FET operation ∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙ 102 3.2.1. DC operation ∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙ 102 3.2.2. Transition between DC and pulse mode ∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙ 106 3.2.3. Transient characteristics ∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙ 108 3.3. Experimental validation of Z2-FET memory operation ∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙ 113 3.3.1. DC operation ∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙ 113 3.3.2. Transient mode operation ∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙ 114 3.3.2.1. Standard memory operation ∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙ 115 3.3.2.2. Retention ∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙ 118 3.3.2.3. High temperature measurement ∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙ 121 3.4. Advanced Z2-FET memory ∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙ 123 3.4.1. Advanced Z2-FET structure: dual ground-plane ∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙ 123 3.4.2. Selection-transistor-free Z2-FET memory array ∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙ 126 3.5. Z2-FET as a logic switch ∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙ 129 3.5.1. Z2-FET with single ground-plane ∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙ 130 3.5.2. Novel Z2-FET with dual ground-plane ∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙ 133
3.6. Conclusion ∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙ 135 3.7. References ∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙ 136 Conclusion and perspectives ∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙ 138 Publications ∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙ 140 Résumé du manuscrit ∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙ 143
Abbreviations
Acronym Nomination 1D One Dimensional 1T-DRAM Single Transistor DRAM 1T, 1C One Transistor, One Capacitor 2D Two Dimensional
3D Three Dimensional Al2O3 Aluminum Oxide
AlTiN Aluminum Titanium Nitride ARAM Advanced RAM
A2RAM Advanced 2 RAM BET-FET Bipolar-Enhanced TFET BiFeO3 Bismuth Ferrite
BJT Bipolar Junction Transistor
BL Bit Line
BTBT Band-To-Band Tunneling BOX Buried Oxide
CBRAM Conductive Bridge RAM CG Control Gate
CP Charge Plasma CPU Central Processing Unit CMOS Complementary MOS CN, CNT Carbon Nanotube
D Drain
DC Steady-state condition
DGP Dual Ground Plane
DIBL Drain-Induced Barrier Lowering DRAM Dynamic Random Access Memory EHB-TFET Electron-Hole Bilayer TFET ED Electrostatic Doping eDRAM Embedded DRAM ESD Electro-Static Discharge EOT Equivalent Oxide Thickness FB-DRAM Floating Body DRAM FBE Floating Body Effects
FD-SOI Fully Depleted Silicon-On-Insulator
Fe-FET Ferroelectric FET FED Field Effect Diode FET Field Effect Transistor G4-FET Four Gate Transistor GDNMOS Gated Diode merged NMOS
GF Front Gate
GIDL Gate-Induced Drain Leakage GP Ground Plane
GP-N N-type Ground Plane GP-P P-type Ground Plane GPU Graphic Processing Unit
GO1 Thin Gate Oxide
GO2 Thick Gate Oxide
G-R Generation-Recombination
H Hold
H0 Hold ‘0’ operation H1 Hold ‘1’ operation HfO2 Hafnium dioxide HKMG High-K Metal Gate HP Hocus-Pocus diode IC Integrated Circuit I-V Current-Voltage IMOS Impact Ionization MOS IoT Internet of Things
ITRS International Technology Roadmap for Semiconductors LDD Lightly Doped Drain
LDMOS Lateral Double-diffused MOS MOS Metal Oxide Semiconductor MCP Multi-Chip Package MIM Metal-Insulator-Metal MTJ Magnetic Tunneling Junction MRAM Magnetic RAM
MSD Meta Stable Dip
MSDRAM Meta Stable Dip Random Access Memory NDR Negative Differential Resistance
NEMS Nano-Electro Mechanical System nMOS n-type MOS
NVM Non Volatile Memories
NW Nanowire
P0 Programing ‘0’-state P1 Programing ‘1’-state PCD Photo Conductance Decay PCRAM Phase Change RAM
PG Program Gate
pMOS p-type MOS
PVCR Peak-to-Valley Current Ratio RAM Random Access Memory
RCA Removal of metallic and organic Contaminations with surface Activation ReRAM Resistive RAM
RF Radio Frequency
RRT Reverse Recovery Transient R0 Read ‘0’-state
R1 Read ‘1’-state
S Source
SEM Scanning Electron Microscopy SCE Short Channel Effects
SIMOX Separation by Implanted Oxygen SiO2 Silicon Dioxide
SOI Silicon-On-Insulator SOS Silicon-On-Sapphire SRAM Static RAM SRH Shockley-Read-Hall SS Subthreshold Swing STT-RAM Spin Torque Transfer-RAM TCAD Technology Computer-Aided Design TEM Transmission Electron Microscopy TFET Tunnel FET
TG Top Gate
TiN Titanium Nitride
TMD Transition Metal Dichalcogenide
WL Word Line
Z2-FET Zero subthreshold slope and Zero impact ionization FET Z2-FET SGP Z2-FET Single Ground Plane
Z2-FET DGP Z2-FET Dual Ground Plane Z2-RAM Z2-FET RAM
Z3-FET Zero SS, Zero impact ionization and Zero front-gate FET
Main Symbols
Symbol Description Unit
Aj Junction area cm2
C Capacitance F⋅cm−2
CBOX Buried oxide capacitance F⋅cm−2
Cox Gate oxide capacitance F⋅cm−2
Cp Parasitic capacitance F⋅cm−2
Dn, Dp Diffusion lengths of electron and hole nm
Ec, Ev Conduction band energy, Valence band energy J
EFn, EFp Fermi level of electrons and holes J
I1, I0 ‘1’- and ‘0’-state current A
IA Anode current A
Id Diffusion current A
ID Drain current A
IF Forward current A
Ig Generation current A
Imeas Measured current A
ION, IOFF ON- and OFF-state current A
IR Recombination current, Reverse current A
k Boltzmann constant J⋅K−1
Lg Gate length nm
Lin Intrinsic part of Z2-FET nm
Ln Gated part of Z2-FET nm
Ln, Lp Diffusion lengths of electron and hole nm
N+ N-type doping concentration cm-3
N* Virtual N-type doping concentration cm-3
NA, ND Concentration of ionized acceptors/donors cm-3
n Ideality factor
ni Intrinsic carrier density cm-3
P+ P-type doping concentration cm-3
P* Virtual P-type doping concentration cm-3
QG Gate charge cm-2
Qox Oxide charge cm-2
q Electron charge C
Rmax Maximum recombination rate cm-3⋅s-1
S1,2 Surface generation-recombination velocities cm/s
t Time s
td Storage delay time s
tRamp Ramp time s
T Temperature °C, K
tBOX BOX thickness nm
tepi Epitaxy layer thickness nm
tox Oxide thickness nm
tSi Silicon thickness nm
VA Anode voltage V
VAprog Programing anode voltage V
VAread Reading anode voltage V
VE Emitter voltage V
VG Gate voltage V
VG1, VG2 Front- and back-gate voltages in MSDRAM V
VGF Front-gate voltage V
VGB Back-gate voltage V
VGbN Ground-plane N voltage V
VGbP Ground-plane P voltage V
VK Cathode voltage V
VON Turn-ON voltage V
VR Reverse voltage V
VS Source voltage V
Vtb,n Threshold voltage for back electron channel V
Vtf,p Threshold voltage for front hole channel V
Vth Threshold voltage V
W Channel width nm
WD Depletion width nm
τ Lifetime s
τeff Effective carrier lifetime s
τv Volume lifetime s
ΦB Barrier height V
Abstract
Fully Depleted SOI (FD-SOI) is an excellent alternative of conventional Complementary Metal Oxide Semiconductor (CMOS) technology which is leading the semiconductor industry. FD-SOI offers low-power consumption and improved electrostatic control for MOS transistors even in very advanced nodes (14 nm and 28 nm). FD-SOI transistors feature nanometer thickness and length which bring rather particular operation mechanisms and characteristics. This work describes the state-of-the- art and assets of FD-SOI components. The Hocus-Pocus (HP) diode is one example of the innovative devices made possible by the unrivaled flexibility of FD-SOI technology. By modifying the type of electrostatic doping, N or P, a single device can be reconfigured as a virtual P-N diode, a virtual Esaki diode, a semi-virtual diode, a P-I-N diode, a TFET or a band-modulation FET. Each configuration works as a physically doped device with peculiar behavior induced by the dynamic change of doping concentration. Original applications such as lifetime extraction and virtual Esaki diode are explored.
The Z2-FET (Zero subthreshold slope and Zero impact ionization) is a striking application of HP diode thanks to attractive characteristics (sharp switch, low leakage current, adjustable triggering voltage and high current ratio ION/IOFF). In this work, we focus on a capacitorless Dynamic Random Access Memory (1T-DRAM) and a fast logic switch. The DC and transient operation mechanisms as well as the device performance are investigated in detail with TCAD simulations and validated with systematic experimental results.
Keywords
FD-SOI, ultrathin film, electrostatic doping, virtual diode, Esaki diode, carrier lifetime, band- modulation devices, 1T-DRAM, logic switch, Z2-FET.
Résumé
La récente technologie Fully Depleted SOI (FD-SOI) est une excellente alternative à la technologie conventionnelle CMOS (Complementary Metal Oxide Semiconductor) qui a mené le développement incessant des circuits intégrés. FD-SOI offre une faible consommation d'énergie et un contrôle électrostatique amélioré pour les transistors MOS, même dans les nœuds très avancés (14 et 28 nm). En raison de leurs dimensions nanométriques, aussi bien en épaisseur qu’en longueur, les transistors FD-SOI présentent des mécanismes de fonctionnement et des caractéristiques très spécifiques. L’état de l’art du FD-SOI est décrit en insistant sur les atouts des composants, les effets physiques particuliers et les techniques de caractérisations dédiées. La diode Hocus-Pocus (HP) est un exemple de dispositif innovant rendu possible par la flexibilité sans égal de la technologie FD-SOI. En modifiant le type de dopage électrostatique, N ou P, un dispositif peut être reconfiguré en diode P-N virtuelle, diode Esaki virtuelle, diode semi-virtuelle, diode P-I-N, TFET ou FET à modulation de bande.
Chaque configuration fonctionne comme un dispositif physiquement dopé. Les aspects inédits découlent d'un changement dynamique de la concentration des porteurs. Des applications originales telles que l'extraction de la durée de vie des porteurs et la diode virtuelle Esaki sont explorées. Le Z2- FET (Zero subthreshold slope and Zero impact ionization) est un dispositif particulièrement prometteur en raison de ses caractéristiques attrayantes (commutation abrupte, faible courant de fuite, tension de déclenchement réglable et rapport de courant élevé ION/IOFF). Dans ce travail, nous nous concentrons sur une mémoire dynamique sans capacité (1T-DRAM) et un interrupteur logique rapide. Les mécanismes de fonctionnement en courant continu et transitoire ainsi que les performances du dispositif sont étudiés en utilisant de simulation TCAD et validés à l'aide de résultats expérimentaux systématiques.
Mots clés
FD-SOI, film ultra-fin, dopage électrostatique, diode virtuelle, diode Esaki, durée de vie des porteurs, dispositifs à modulation de bandes, 1T-DRAM, interrupteur logique, Z2-FET.
Introduction
FD-SOI
Electrostatic doping vs. physical doping Sharp-switching device
1T-DRAM
Contents
1. SOI technology ∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙ 15 1.1. State-of-arts and trends: MOSFETs ∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙ 15 1.2. Migration to FD-SOI ∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙ 16 1.3. FD-SOI technology ∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙ 17 2. Physical doping vs. Electrostatic doping ∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙ 19 2.1. Physical doping: Ion implantation ∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙ 19 2.2. Electrostatic doping ∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙ 20 3. Sharp-switching devices ∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙ 21 3.1. Tunnel FET (TFET) ∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙ 21 3.2. Impact ionization-MOSFET (I-MOS) ∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙ 22 3.3.Nano-electro-mechanical FET (NEM-FET) ∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙ 23 3.4. Ferroelectric-FET (Fe-FET) ∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙ 23 3.5. Band-modulation device: Z2-FET ∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙ 24 4. 1T-DRAM: Capacitorless Dynamic Random Access Memory ∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙ 25 4.1. State-of-the art: the need for new memory for Internet of Things (IoT) ∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙ 25 4.2. Conventional 1T+1C DRAM ∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙ 26 4.3. Resistive RAM (ReRAM) ∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙ 26 4.4. Spin Torque Transfer-RAM (STT-RAM) ∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙ 27 4.5. Floating-Body DRAMs (FB-DRAMs) ∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙ 28 4.5.1. Meta-stable DRAM (MSDRAM) ∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙ 28 4.5.2. A2RAM ∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙ 29 4.5.3. Z2 RAM (Z2-FET RAM) ∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙ 30 5. References ∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙ 31
1. SOI technology
1.1. State-of-art and trends: MOSFETs
Ever since the invention of the Field-Effect-Transistor (FET) at Bell laboratories by W.
Shockley [1], J. Bardeen and W. Brattain [2] (Nobel Prize 1956) in 1948, and the first Integrated Circuit (IC) created by J. Kilby [3] (Nobel Prize 2000) following, the CMOS technology emerged as the dominant fabrication method for semiconductor integrated circuits [4]. As the CMOS technology is a driving force, the MOS transistor (Fig. 1.1) was exclusively fabricated on Bulk silicon substrate (P-type for nMOS and N-type for pMOS). The source and the drain are realized by implantation of donor/acceptor dopants next to the conduction channel. Considering the p-type silicon substrate, the source and the drain contacts are N+ type. The gate is separated from the substrate by a dielectric layer.
The down scaling increases the on-chip transistor density. Nowadays, a chip can contain a few billion transistors. However, the fast downscaling puts almost an end to Moore’s law [5].
Until roughly 2012, transistor fabrication costs continued falling at rapid rates. At the 22/20 nm techn- ology node, which went into volume production around 2012 at Intel, the cost of transistor is no longer decreasing as fast as before while the equipment investment increases aggressively (Figure 1.2) [6].
The bulk planar silicon MOSFET is facing severe problems as miniaturization continues particularly with respect to power consumption [7], [8]. When the gate length shrinks, the depletion regions of source (S) and drain (D) can overlap affecting the channel electrostatic control induced by the gate bias. The potential distribution in the channel therefore depends on both transverse electric field (controlled by the gate) and longitudinal electric field (induced by the drain bias) which results in many forms of undesirable electrical characteristics [4]. Short-channel effects [9] (SCE) which are critical issues in low-power operation devices, such as threshold voltage roll-off, subthreshold swing
Figure 1.1. Schematic cross-section of N-type MOSFET transistor on 28 nm Bulk technology.
(SS) degradation, mobility degradation and drain induced barrier lowering (DIBL) have been on the rise. Although there have been new technologies and architectures (Metal Gate, LDD implant, Halo implant, etc.) proposed to solve the SCE, the improvements are still insufficient for harsh scaling-down.
1.2. Migration to FD-SOI
The MOS transistor implementation became more and more complex. In order to address this challenge and improve the device performance, adoption of new technologies, new materials and new architectures is required. One candidate, SOI has traditional merits: total insulation of devices, thin junctions to reduce leakage currents and parasitic capacitances, robustness to irradiation, etc. [10].
However, they were not enough to disrupt the conventional CMOS technology. When the miniaturization of transistors has been blocked, it has been shown that the only way to keep moving forward on Moore's law is to reduce their thickness. This argument was decisive not only to re-establish the SOI technology, but also to give birth to FinFET technology.
A thin MOS transistor is by nature completely depleted, which gave the FD-SOI name. The Figure 1.2. (a) Transistor manufacturing cost and (b) minimum scaling cost at recent technology nodes (GlobalFoundries 2015).
(a)
(b)
concept of full depletion has been long known, already at the time of the SOS (1970s) and SIMOX (1980s) technologies [11], [12]. Numerous models and techniques of characterization have been developed [10], [13] with commitments of French researchers (CNRS, LETI). The great value of the contributions of IBM, Sematech and the SOI Consortium [14] led by Soitec is noteworthy. Following multiple technology developments and design tools in the 2000s, STMicroelectronics decided to launch its FD-SOI pipeline.
1.3. FD-SOI technology
The dynamic adjustment of the threshold voltage Vth of the transistor by biasing the back gate represents a unique virtue of FD-SOI which is absent in competing FinFET technology. An increase of 200 mV in Vth reduces the consumption in OFF-state by three orders of magnitude. In ON-state, on the other hand, the performance is optimized by lowering the Vth and improving carrier mobility through strain engineering and/or replacing Si with SiGe. This is the determining reason for the advantageous position of the FD-SOI circuits in the market for low-voltage and low-power components for the Internet of Things (IoT). The variability of the Vth is a critical problem for low-power operating transistors. Since FD-SOI MOSFETs are undoped, the main source of variability (random fluctuations in dopants) disappears. Although fluctuations in layer thicknesses are a priori a source of additional variability, SRAM FD-SOI memories show splendid performance [15]. The RF-SOI circuits are also ranked in the most prominent position in silicon industry. They benefit from much lower parasitic capacitances than FinFET, as well as from high-resistivity substrates designed and manufactured by SOITEC. The general consensus is that the FD-SOI is economic (cost-effective) and complementary to FinFET.
Figure 1.3. Schematic of SOI wafers fabrication using SmartCut® technique supported by SOITEC [16].
The SmartCut® technique (UNIBOND) is being continuously updated by SOITEC [16], the world’s first SOI wafers provider. The main processing steps are shown in Fig. 1.3.
1. Formation of an oxide layer on a silicon substrate (wafer A in Figure 1.3) followed by hydrogen ions implantation.
2. Hydrophilic bonding at room temperature of wafer A to a wafer B. Both wafers are previously cleaned using a modified RCA process.
3. Two-phase treatment of the stack in order to split it into two parts at hydrogen ions level.
4. In order to get a uniform and clean surface, a final touch-polishing of SOI wafer is performed.
The typical configuration of a FD-SOI MOS transistor is shown in Fig. 1.4.
FD-SOI MOS transistor has typical characteristics and features outstanding advantages [17], [18]:
i. Ultrathin and undoped body of the transistor for better electrostatic control, reduction of short- channel effects (SCE), and minimum subthreshold swing (SS);
ii. Thin BOX for reduction of parasitic capacitances between source/drain contacts and the substrate;
iii. Ground plane (N+ or P+), located under the BOX, is used as a back gate (with contact brought back to the surface);
iv. Gate dielectric with high permittivity;
Figure 1.4. (a) Schematic of FD-SOI MOS transistor [17] and (b) TEM cross-section of nMOS device (Lg
= 24 nm) with 7 nm ultrathin SOI [18].
(a) (b)
Gate
v. The metal gate allows the symmetry of the threshold voltages of the N- and P-channel MOSFETs.
In contrast, SOI technology presents some drawbacks such as self-heating and floating-body effects (FBE). However, the FBE is a key principle for dynamic memory applications developed in this dissertation.
2. Electrostatic doping vs. Physical doping
As a result of pursuing Moore’s law for the last 40 years [5], major technical challenges were encountered in achieving today’s small feature sizes. The number and difficulty of the technical challenges are continuing to increase. One of the important processes in device fabrication which suffers from film thinning is the doping technique. In this section, we address the conventional doping method and its limits which bring up a new doping concept: electrostatic doping.
2.1. Physical doping: Ion Implantation
Ion implantation is the introduction of dopant atoms into a substrate by bombardment with ions in the keV to MeV energy range [19]. Implantation is the most popular chemical doping method known for precise control of dose/depth profile, low-temp process, and excellent lateral dose uniformity compared to thermal diffusion, or in-situ growth of dopants. Ion implantation equipment (Fig. 2.1) [20]
Figure 2.1. Schematic of ion implanter [20].