Boot Logic

(1)

Boot Logic

I

8284

I

8086

I I I

I

IntAck

Pa ritY'E r ro r VertSvnc Systlntrpt

I I

' - -

I

Interrupt Cont rolle r

8259A

J 1

I ^Data

Datal Address Bus

r---~--~Input

-

I

Addres!

Registe"

SelectMainMem

Addr

SelectinterruDt SelectENetCtI

Decode r

SelectENetData

~~~

----

LS313's

1 K

X

16

SeiectLocaJRAM

RAM

I ^I

ControlBus

I I ^Function

Ethernet Decoder

I - - -

Logic

Buffers

I

Bus Addr.

and Output Data Latches

I

I ^I

I I I

Load

=

.4ma

I I

Bus I

Timine Logic

I

I I I

~ I I

U

I I

System I

Bus

Tol From Transceiver

Loss of Carrier Collision

XEROX

^Project

Ethernet Processor

^File ^Designer ^Rev ^Date ^Page

SPG NoteTaker Block Diagram ENETBLOCK.si Ron Freeman A 11/1/79 1

- - - -

1

i

(2)

_~esH;tReac,i t:::NetW riteReady ECMemReady

XtalConnect CaoConnect ECSysReady ECSel M Mo rENet Data'

P2 P2

VPull GND

24

ill:)

GND

GND ECReset' VPull VPull1

1~·rrNK PCLK~

17 Xi ... 12

16 X2 OSC

4 i8284

3 RDY1 6 AEN1'

RDY2 #e29 7 AEN2'

~

¹³₁₁^CSYNC^EFI^~/C' ^RESET^READ ⁵¹⁰

RES' CLK 8

ECRst ECRdv ECSvsClock

40 LUSFIVE

.:::g:.::g:""'--2~ROUND1i8086m

n

~~~~r,ROUND2 #aib

1 LSO ... 2 ECSvsClock'

#c44a

BHE' 34 AD1"- 39 AD1 2 AD13 3 21 RESET AD12 4 22 READY AD11 5 19 CLK AD1~ 6 7

33 AD09

MX' ADO::; 8 A16/S3 38 A17/S4 37 A18/S5 36 A19/S6 35

9

ECCou BusHiEn ECCpuBus.OO ECCouBus.01 ECCouBus.02 ECCouBus.03 ECCpuBus.04 ECCpuBus.05 ECCpuBus.06 ECCouBus.07 ECSeq.03 ECSeq.02 ECSeq.01 ECSeq.OO ECCpu Bus.08

[IQJ I

^IMIP' ₂₃^{17 NMI}_TEST' ^ADO?¹⁰ ECCouBus.09

!

²⁰

I I

30

VPull _E=-C=-I=,n:.:.t~A~' ~ ____ --=2::..;:6~INT A' SP 16 lEN'

~E=-C=-R~eo=-a:::::;d=-'-:--_____ ~3~R D' _E=-C=-W~r~it.;::.e:-' ~-:-__ --=2=-tW R'

~E=-C=-S~e~I,-:,1 n",-,t~r~C..:..;tl..:....r'_~:-::1:-1CS' ECAddr.18 27 AO

J .~ ___ • 18 J~£O~A

~---~~~~:---~1~9~IRO

DO 11 ECC uBus.08 D1 10 ECC uBus.09 D2~9 ___ ~E~C~C~U::..:B::..:u;;.;.s~.~10~

__ ~1=8 ____ ~E~C~C~u::..;B::..:u;;.;.s~.~1~1 U,j 7 ECC uBus.12 D4~6~--~~::":::";;:;';;';~~

D5~ _ _ ~E~C~C~U::..;B::..:u;;.;.s~.~13~

20 IR1 21 IR2 22 IR3 23 IR4 24 IR5

D6~5 ____ ~E~C~C~U::..;B::..:u;;.;.s~.~14~

# d 14 D 7 ~4....:-____ -=E::..:C::..:C~p::..:u::..:B::..:u;;.;.s~.~15~

INT 17 EClntr 25 IR6

IR?

CO

[§iJ

VSync' 3

~,....4:...-' _~V:,,::S::..Iy~n:..::c~

~44b

96 Reset'

76 ProcReset'

MData.12 MData.13 13 MData.14 2 MData.15

8 ^ProcBoot'

C[J

Proclnt'

XEROX

^Project

NoteTaker E-Net Controller

SPG

_Designer

_FREEMAN 8086 6JlQL&..Ra,SMet Logic

AUU

#a1a

ADO~~1~1 ______ ~E~C~C~P~U~B~u~s~.~1~0

ADO~

¹² ECCⁿuBus.11 A

D03l~-~1~3

^______

-...;;E~C;,,:C:;JP::..:U::..;:B::..:U:.:::S:.:...

1.:....:2;- AD02Ir~14~ ______ ~E~C~C~p~u~B~u~s~.~1~3 AD01~15~ ______ ~E~C~C~u~B~u~s::..:.~1~4 16 ECC uBus.15 /sb A DO~3::-'2~---~E~C;":C:;r.:::";R;:;';;';;;';'d";";:;"

RD,~~ ______ ~~~p~u~e~a~~

Boot

i8086min

18 INTR HOLD 31

GND

GND 12

11

VPull

ECS slntr

File

ENET01.sil

---.

WR' ^{} - o l}~29~ _____ .-;E=-C~C~p~uw~r;..:.it.;::.e_'

DEN' 1²⁶ ECDEn' DT/R,~~2~7 ______ ~E~C~D~T~/~R~' __ _

M!.'9K~

^ECALE

II:-t-~'~I ;24~========E~C;I~n~tA::'

- - - HLDA

30

9 ECReset

ECReset'

Date Drawing No. Rev

12/04/79 217737 A

Page

01

(3)

LS373 Prom

~

^DO^D1 ⁰⁰⁰¹

~

^GND ^'5

f

^S'

^I

-,-e-ou-B-usHiEn-'-

---8~

^D2_D3---- _-03⁰²-9--- ---EGH-i€nL- --- - ---S4+-2--+-

ECSeQ.OO 13 12 ECAddr.OO 19

ECSeQ.01 14 D4 04

15 ECAddr.01 18 AOO

01 6 ECSelMM

D5 05 A01 7 ECSeli nt rCt! r'

ECSeQ.02 17 16 ECAddr.02 17 02

D6 06 A02 8 ECSeIENetCtI'

ECSeg.03 18 19 ECAddr.03 16 03

D7 07 A03 9 ECSelENetData'

5 04

A04 11 ECSelENet Data

EN OC' #a35 4 !A05 05 12 ECSelMMo rENet Data'

11

I

¹ ³^A06 ⁰⁶ ¹³ ECSelLocalRam'

~ A07 ⁰⁷ 14 ECSelLocalRam

ECALE ~ A08 08

~~

GND #c63 LSOO 6 RAMOutEn'

5 U # e 5 5 b

LS155

~

00' ECDEn' 5

LS04 6 ECDEn 1 01'

5

I

00 02' c44c

03'

r-

⁴

15 DR' RO'

~O

ECSeIENetCtI' 3

S2 R1' ECSelENetData' 13 R2' 11

LS373 51 ... 12

ECCpuBus.OO 3 2 ECAddr.04 R3' ECCpuBus.01 4 DO 00 5 ECAddr.05 EO' ER' #a65 ECCpuBus.02 _7 D1 01 6 ECAddr.06 21 141 no", 1'"\'" OJ"'-

"'''"

ECCpu Bus.03 81 F9 ECAdd r.07 ECCnu RlIs.04 13 D3 03 12 ECAdd r 08 ECCpuBus.05 14 D4 Q4 15 ECAddr.09 ECCpuBus.06 17 05 05 16 ECAddr.10 ECCpuBus.07 18 D6 Q6 19 ECAddr.11 ~~~~~~----~~D7 07~~--~~~~--~ ECRead' ECWrite' EN OC' #a46 L.-:;;:.r--=r~ ECWrite' 1 ,...~

"1'

t\LE GND ~~~--~~~~ILS32~~3~--~ ECHiEn' 2

~[Ag33a I

^lK^x8 Static RAM's RAMOutEn'

W:1-

20 ECSelLocalRam' 18 D VPull 19 B 8 7 ECCpu Bus.08 3 LS373 2 ECAdd r.12

~

-E~C~C~:~P1U~B~U~S~.O~9~---~4~DO 00~5----~E~C~A~d7d7r~.~13~---~-r~+---~4-

-E~C~C~:~D1U~B~U~S~.~10~---~7~D1 01~6~--~E~C~A~d~d~r~.1~4~---~-+~+-~---~3-

-E~C~C~P1U~B~u~s.~1~1~---~8~D2 02~9~--~E~C~A~d~d~r~.1~5~---~~-+~+-~---~2-

-E~C~C~:~P1U~B~u~s~.~12~----~1~3~D3 03~12----~E~C~A~d~d~r~.1~6~---~~-+~+-~---~1-

~E~C~C~:P~U~B~U~S~.~13~----~1~4~D4 04~1~5~--~E~C~A~d~d~r~.1~7~----~~~-+~+-~---~23~

-E~C~C~:p~u~B~u~s~.~14~----~1~7~D5 05~1~6~--~E~C~A~d~d~r~.1~8~--~+-~~-+~+-~---2~2~

-E~C~C~:p~u~B~u~s~.~15~----~1~8~D6 06~19~--~E~C~A~d~d~r~.~19~-T~~+-~-+~+-+---~-

~~~~~~----~~D7 07~~--~~~~~-+~~+-~-+~+-~

EN OC' #c52

ECALE 11 / '

ECWrite' 4 5

'"':z:: =

^LS32 ⁶

L---~

...

^:JI

#g33' GND

-=R~A~M~O~u~t=E~n~~'~~ __ ~ =2~0~D -,E;;;,C::::,S=el:..:L;,;:;o.::;.c.:::,a;.;,.1 R~a::.:m~' __ ~1 ~8~ B

VPull 19 8 7 6 5 4 3 2 23 22

o

9 10 11 13 14 15 16 17

MK4118 #d1

Or

9 10 11 13 14 15 16 17

MK4i18 #a22

ReadPortOata' ReadStatusReg'

WritePortOata' Load(;tl Reg'

ECCpuBus.OO ECCpuBus.01 ECCpu Bus.02 ECCpuBus.03 ECCpuBuS.04 ECCpuBuS.05 ECCpuBus.06 ECCpuBus.07

ECCpuBus.08 ECCpuBus.09 ECCpuBus.10 ECCpuBus.11 ECCpu Bus.12 ECCpu Bus.i3 ECCpu Bus.14 ECCpuBuS.15

XEROX

^Project

NoteTaker E-Net Controller

^File ^Date Drawing No. Rev Page

SPG

Designe,r;..

FREEMAN

A~~r~!~~~_loca

I RA M ENET02.sil 12/04/79 217737 A 02

eEJiIiiUiJJIfJG!JA!iIJIibEJ'~~!&\·~_ ~-. - ~

(4)

BusSync

ECALE 9

ECBT.02

ECReset 8

ECBT.08 ECWrtReset 95 BusClock

7 11

VPull _cr,ProcLock 12

ECBT.02

MData.OO 3 31 MOata.01 4 32 MData.02 7 33

-

MData.03 8 34 MData.04 13 35 MData.05 14 36 MData.06 17 37 MData.07 18 38

InDataClock ECRead'

39

^MData.08_MData.09 ₄³

41

_MData.10 ₇

42 43

^MData.11 ⁸

44

^MData.12 ¹³

~ ^MData.13_MData.14 _-17¹⁴

~ _MData.15 ₁₈

'7

_-'--

!nDataCiock ECRead'

VPull VPull

ECSelMM 2

8 3

10

---4- D S' 0

S74 C 0'

R' 5

#g1a

----oro

^l

12

11

OKtoSet

--:E~C~B=-T;;..;.~0=-=1:-' _--::1~ D A _...;E;;;.,;C::;..;B;;;.,;u;;;.,;s;..,:T..;:;E;.:.,;n_-.;;;;2-t DB

H 3

ECMemRead

H1 4 H2 5 H3 6 LS164 H4 "10

H5 :11 H6 12 H7 13

ECBT.01 2 lAO OO~3 ^ECBT.01'

LS373 00 00 2 D1 01 5 D2 02 6 D3 03 9 04 04 12 D5 05 15 06 06 16 19 07 07

#i1 11

LS373 DO 00 2 D1 01 5 D2 02 6 D3 03 9 D4 04 12 D5 05 15 D6 06 16 D7 07 19

EN ~C' #k1

. . ! .1

11

I

1

I

4 1\1

01-

5

6 02 7

10 A2

03 9 A3

ECSlock 12 LS368

11 BusLock' 14 BO

B1 GND :1 AEN'

15 BEN'

ECSe

ECC uBus.OO ECC uBus.01 ECC uBus.02 ECC uSus.03 ECC uSus.04 ECC uBus.05 ECC uBus.06 ECC uSus.07

ECCpuBus.O 8 ECCpuBus.09 ECCpuBus.1

o

ECCpuBus.11 ECCpuBus.1 2 ECCpu Bus.13 ECCpuBus.1 ECCpuBus.1 4 5

04 "13 05

#m21

ECAddr.19 ECHiEn'

ECWrtDataEn 4

ECALE 5

12 11

XEROX I

^Project

NoteTaker E-Net Controller

^File

ECBusTEn

BusRe

ECBT.01

ECBT.02

13 LoDataAdrOut'

ECWrtDataEn ECWrite

ECBT.03

ECBT.04 10

ECWrtReset ECWrite 9

ECBT.07 ECBT.08

InDataClock ,4/k58d

ECBlock

3 OKtoSet 2

6

3 LS373

2 MData.08 4 DO 00 5 MData.09 7 D1 Q1

6 MOata.10 D2 02

9 MData.11 13 D3 03 12 MData.12 14 D4 04

15 MData.13 ECSe .02 17 D5 05 16 MData.14 ECSe .03 18 D6 06 19 MOata.15

D7 07

#k23 ECALE

ECBT.01 '

ECC uBus.OO 3 LS373

2 MOata.OO ECC uBus.01 4 DO 00 5 MOata.01 ECC uSus.02 7 D1 01

6 MOata.('~

ECC uBus.03 8 D2 02

9 MData.03 ECC uSus.04 13 D3 03

12 MData.04 ECC uSus.05 14 04 04

15 MData.05 ECC uBus.06 17 D5 05

19 MOata.07 07 07

11 DaAddEn

Hi OataAd rOut'

ECC uSus.08 3 LS373

2 MData.08 ECC uSus.09 4 DO 00

5 MOata.09 ECCouSus.10 7 D1 01

9 MData.11 ECC U Bus. 12 13 D3 03

12 MOata.12 ECC uSus.13 14 04 04

15 MData.13 ECC uBus.14 17 05 05

16 MOata.14 ECC uSus.15 18 D6 06

19 MOata.15 D7 07

EN ~C' #k12

~ -4 I 1

"I

^"

LoDataAd rOut'

Date Drawing No. Rev Page

SPG

IDesigner

'~:REEMAN

_~9JJLJ

... ogic ENET03.sil 1.1 /19/79 217737 A 03

' - - - - . _ - - ' - - - " ' - -

--.

^~lrI _-"'-

(5)

P3 105r _____ T~RTD~a~t~a~---~--~

PLAT

1 XO 16 VCC

2 X1 15 GND

Jum 1 3 OX 14 XtalConnect 4 X2 13 CaeConnect

5. X3 J2

VCC 6 11 Jump2

RDataDela:t:ed 7

E

GND 8

#c35

CaoTie1

CapTie2

ResTie1 ResTie2

7 6 R C

RDataDela ed

Transition RData

ResTie1 PLAT

XO X1 X2 OX ResTie2

X3

16 VCC 15 CaeTie1 J4

1

3 ^VCC 12 CaeTie2

VCC

~6

GND

P3

<IQL>

^TROther

~ I

³

~~4.:...---..:0~t~h:.:::::e.:..r'

^{____ _}

~50b

RClk 13

Q

i

VPull1 Transition

~

^Q^,1-⁴^-'--__^--4^__.;..;R..;::;C=lk'

CL' #o57a

~

^GND ⁹ ^b^a'

I

^'LOC' ^3'

ILOC

ISRFull 9 IMI?'

ReadOverride 10 VPull1

ISR.0014

Carrier' 12

VPull1 13

InOn

ISRFull'

XEROX I

^Project

NoteTaker E-Net Controller SPG ~esigner FREEMAN

D~t~~,.U\,Logic

LS12 Q' CL'

12 13

12

#o57b

IMIP

IMIP'

1 13 2

Carrier' 5

2 J S'~ 6 InOn u

ECS sClock' 4

~SlOf

3 7 InOn'

K' Q' R' #m48a 1

RcvOn

·-VPuIl1

14 leteXmission

# k42a ECSysClock' 12 VPull1 13 Q'

":":"=-:"'-'-=-:::.-.j K' R' # m48b 15

ENReset'

File

I

^Dale D,awing No. Rev

I

^Page

I

ENET04.sil _. 11/21/79- 217737 A 04

~'~~~'..--

22W j L.?J9hIR!3iIfSF9 .. ~~ .

(6)

C0115 ISRFull R D a t a d D A HOI 3 ISR.15 VPull 6

~~ -~1ti- f

I ⁵

_______ ~_ -'26_

H2

^{H1 4}r-5---tS-R-:-"'IJ--^ISR.14 -1---4-

H3 6 ISR.12 I ^{3 B2}_B3

H2~4

_H3

L$164 H4 10 ISR.11 LS161

H5 11 ISR.10 IMIP 7

H6 12 ISR.09 IMIP 10 EP

H7 13 ISR.08 ET

CL'CKLD' #q23

9

~~8::...-_-...:.IS:::::.R:..:.:...FU::.:I:.:.I'

^{_ _}^_

~50d

CK CL' #012

'IT

^ISR.1

8

1

InOn 9

RClk RClk

5 F9401

~--' ... D

a

²

--~CK'

InOn

IMIP' VPull

InOn'

I

¹ DA HO 3 ISR.07

L-2..

_DB H1 ⁴ ^ISR.06

5 ISR.05

H2 6 ISR.04 H3 10 ISR.03 ... S164 H4

11 ISR.02 H5 12 ISR.01 H6 13 ISR.OO H7

RCRCZero'

-...:~CWE

---:::-fMR

P' ^{ER 13}

GND

CK CL' #m12 RClk

8

1

9

1

InO"l .

VT . l

I

D :)' 0

1

⁵ ReadFuliReset

.

-

..

^,

Read Port Data' 3 LS74 C Q'

.;

ILOC' 5

t#q58a

ECReset' 4 ;JLS 11 6 3 ~'

r

^#e47b

L1.Lc~

11 ENetReadReadv LS374

ISRFull

~9~

^ISR.OO ³ ^DO ⁰⁰² ECCouBus.OO

,Ch'50d

ISR.01 4 5 ECCouBus.01

D1 Q1

RClk' ISR.02 7

D2 02 6 ECCouBus.02

ISR.03 8 9 ECCou Bus.03

#k58a ISR.04 13 D3 D4 03 Q4 12 ECCou Bus.04 ISR.05 14

D5 Q5 15 ECCouBus.05 ILOC'

ISR.06 17

D6 06 16 ECCouBus.06

~

ISR.07 18 19 ECCouBus.07

D7 07

VPull 12 S' ReadBuffFull

CK OC' #m1

o

^{0 9}

111

¹ ^LS74

LoadlnoutRea 11

LS04 10 LoadlnoutRea' 11

O'~

C q50e

~#q58b

ReadFullReset 9 13

ReadPortData'

81LS02 10 ECReset

#a57c

ISR.08 3 LS374

2 ECCouBus.08

ISR.09 4 ...,0 00

5 ECCouBus.09 VPull

...,1 01

-.L

ISR.10 7 6 ECCou Bus.1 0

ISR.11 8 1J2 02

9 ECCouBus.11

ISR.12 13 1J3 03 12 ECCouBus.12 2 S' 5 InoutDataOverrun

..,4 04 D

a

ISR.13 14 _~5

05 15 ECCouBus.13

LS74 ISR.14 17 _~6

06 16 ECCpuBus.14

ISR.15 18 ';;7 Q7 19 ECCou Bus.15 3 C

.R

a'

CK OC' #01 ^_R~#g17a

111

¹ ¹

ReadPortData' ENReset'

XEROX I

^Project

^NoteTaker E-Net Controller

^File ^Date Drawing No. Rev Page

S PG I

^Designer

_FREEMAN

_~-1nlltl1l.9,g

i c ENET05.sil 11/16/79 217737 A 05

~,.~

(7)

-

VPull1

CRCGo

^:J:~~ __

^m^{_ _ _ _}^I 11 5

-osto-a-ct-- - ¹⁴

S'

_1-0---0ttt--0n-'- ² --0tI-t 14

--;j---

U k 5 0 a 0

Other' 13 TClk' 12

C-

^S1O ^TClk' ⁴ ^{TClk' 12}

XmtOn 12

8 13 K' 0' 9 OutOn

VPull1 3 0 VPull1 13

WriteBuffFull 10

,

R' #029b R' #m30a

Carrier' 9

XmtOn 15

TClk 3

XClock' 5

OutOn' 4

VPull1 ECReset

2 6 14

5.88Mhz Other' 4 TClk' 12

1..[;([~:q66

^TClk

'3~'2

^TClk' ^VPull1 ³ ^VPull1 ¹³

GND

#q50f

XmtOn

Note: The SIP resistor packs use the P2 connector pins for their sockets and the Dipswitch straddles the P2 connector between pins 33 and 48. R-Packs are to be installed with the VCC connection end in pins 20 and 50.

P2 P2

'33)

<34'

ENetAddr.OO ENetAddr.01

~

^{(36 (} ENetAddr.02

~

^{(38 (}

~

^{(40 (} ENetAdd r.03

~

^~ ENetAddr.04

~

^ENetAddⁱ^.05

I ~ ^~

ENetAddr.06

~

ENetAdd r .07

47

~

^VCC

~

3 4 7 8 13

...

.'->

17 18

ECSeIENetCtl'

I This is the Control Reg

ECCpuBus.08 3 LS273

~

ECCpuBus.09 4 DO 00 ECCpuBus.10 7 D1 01

ECCpu Bus.11 8 D2 02 ReadOverride ECCpuBus.12 13 D3 03

12 ECProcLock ECCpu Bus.13 14 D4 04

15 ECBootSeQDone D5 05

ECCpuBus.14 17 16 RcvOn

ECCpuBus.15 18 D6 06

19 XmtOn ILOC 3

D7 Q7 InputDataOverrun 4

#i23 In completeX mission 7

CK CL'

RCRCZero' 8

11

1

¹ ^Call ¹³

LoadCtlReg' ECBootSeQDone 14

RcvOn 17

XmtOn 18

I

ECReset' 4

~llS08

⁶ ^{EN Reset'}

ReadStatusReg'

5~

ECSelENetCtl'

I

^-: ^#k50b

LS373 DO 00 D1 01 D2 02 D3 03 D4 04 D5 05 D6 06 D7 07 EN DC' 11

I

¹

LS373 DO 00 D1 01 D2 02 D3 03 ...,4 04 ...,5 05

1 .... 6 06

1::;7 07

EN OC'

11

I

¹

11

S' 1-0-- ---GtttRGo- -.:1----

0

C-

^S1O

OutEnd'

10 Coli

9 Coli'

2 ECCpuBus.OO 5 ECCpuBus.01 6 ECCEu8us.02 9 ECCQuBus.03 12 ECCpuBus.04 15 ECC-uSus.05 16 ECCpuBus.06 19 ECCpuBus.07

#941

2 ECCpu Bus .08 5 t:CCpuBus.09 6 ECCpuBus.10 9 ECCpu Bus. 11 12 ECCpuBus.12 15 ECCpuBus.13 16 ECCpuBus.14 19 ECCpuBus.15

#952

XEROX I

^Project

NoieTaker E-Net Controller

^File ^Date Drawing No.

I

^Rev ^Page

SPG ,"<"JDesigne~ ^FREEMAN 1.o.9J.1 ..

~~

... Status ENET06.sil .. _"k ___

^:;_~

12/04/79 217737

^~·^___&:"'-::~~.IIe:E.i.'

A 06

(8)

ECCpuBus.07 3 LS273

2 11 ^I

ECCpu Bus.06 4 DO 00

5 12

l C ECCpu Bus.05 7 01 01

6 13

ECCpuBus.04 8 D2 02

9 14 \l...S1

1=('r:nIlRu~ 03 13 03 03

12 3 ^I

vtt---_··· ... ^---_^..^_--_._--

ECCpuBus.02 14 15 4

ECCpuBus.01 17 05 05

16 5

ECCpu Bus.OO 18 06 06

19 6

07 07 Msb

65

1

9 OSOata

CK CL' #q1

10 11

1

I

^OSLoad' ¹

WritePortOata' ECReset'

OSOataG

#q32

~X~C~lo~C~k

^______

~1

¹⁵

1 ~

ECCpuBus.15 3 LS273

2 11

•

DO 00

-

ECCpuBus.14 4

01 01 5 12 lC

ECCpuBus.13 7 6 13

ECCpuBus.12 8 02 02

9 14 \l...S1

ECCpu Bus.11 13 03 03

12 3 ^I

ECCpu Bus.1 0 14 04 04

15 4

ECCpuBus.09 17 05 05 16 5

ECCpuBus.08 18 06 07 07 06 19 6 Msb

65

OSOataG F9401

0 0 12 XClock'

CK' CRCGo'

OutOn' CWE MR P' ER :13 9

1

CK CL' #q12 GNO 10

WritePortData' 11

1

₁

1

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VPull 2

WritePortOata' 3

OSLoad' ECReset' Coli'

Coli ECReset

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OCntrO 19 S472

OCntr1 18 AOO

01 6

A01 7

OCntr2 17 02

A02 8

OCntr3 16 03

A03 9

XClock 5 04

A04 11

XOata 4 05

OutGo 3 A05

06 12

A06 13

OSOataG 2 07

A07 14

L:.[

_A08 08

#e63

XEROX

^Project

NoteTaker

SPG

_Designer

_FREEMAN

4

OSLoad' 1

• • #q41...

I

^GNO

~X~C~IO~C~k ___________ 2_1~_1_541 ______ ~51~

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VPuii1 7 CRCGo·

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1

0

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• r- Write Buff Full

OSLoad' LS74

-===--"':"";-fC o'ra:::..---~ ^OutEnd' R' #k34b

8 ENetW riteRead WritePortOata'

Regulator plugs in here.

P2~

P2 ([[)~ _____ G~N~D~_

LS273

SOCntrO 3 DO 00 2

SOCntr1 4

01 01 5

SOCntr2 7

02 02 6

SOCntr3 8 03 03 9

SXClock 13

04 04 12

SXOata 14

05 05 15

SOSLoad 17

06 06 16

SOSLoad' 18 19

07 07 CK CL' #963 11

1

¹

TClk' OutEnd'

E-Net Controller

^File

OCntrO OCntr1 OCntr2 OCntr3 XClock XOata OSLoad OSLoad'

Coli'

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113 P3

9

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Date Drawing

No.

~

^P3

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^P3

----<II9

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GND.

<II§>

P3

Rev Page

J).JJ.1ru.Ll.S.b.i.f1.Re 9 i

5

t e r ENET07.sil 12/04/79 217737 A 07

(9)

i

_Revisions

I

I J

^LAL

Rev Description Chk Date Approved

A ENGINEERING RELEASE

_{. = '} _--,^11/2/79_"='1-_____ . _____________________

I

...

I

^{Dist Code}

^SPG

I

These drawings and specifkcations Notes Unless Specified Drawn

R. FREEMAN

Xerox Corporation

,and the data contained therein, EI Segundo, California

XEROX

are the exclusive property of

Check Xerox Corporaton and/or Rank 1. Tolerances

Xerox,Ltd. issued in strict confi· .xx + .03 Angular

dence and shall not, without the . xxx + .010 ₊1/2⁰ Appr .

PROGRAMMING SPECS

prior written permission of Xerox

Corporation or Rank Xerox,Ltd. be 2. Break All Sharp Edges

Material

t reproduced,copied or used for .010 Approx

- ETHERNET CONTROLLER

1ny purpose whatsoever except

3. Mach. Surfaces \ I 1e manufactureof articles for

i

Xerox Corporation or Rank Xerox.

NOTETAKER1

I

4.AU Dim. in Inches

.

Code Ident Size Dwg. No. Change Letter

I

^{Model No.}_{Frst Use}

_NT1

^Finish

38338 A A

i

Next Assy.

Scale Do Not Scale Drawing

I

^Sheet

a

fi rst Use

(10)

1.0 SCOPE

This document is an attempt to define the programming format, idiosyncrasies, and timing requirements of the Ethernet Controller interface for the Notetaker system. As such, it is a volatile document and will be changed as often as necessary to keep it current with the ongoing development effort.

1. -I The basic processor used by the Ethernet Controiler is the Intel 8086 micro- processor.

2.0 DESIGN CONSIDERATIONS

2.1 The design of the Controller was done based on the following considerations with regard to Main Memory, Local RAM, Ethernet Data transfers, Et.hernet control and status and Interrupt Controller addressing assignments:

ILl

These drawings and specifications,and the data contained therein, are the exclusive property of Xerox Corporation and or Rank Xerox,Ltd.

issued in strict confidence and shall not, without the prior written permissiOn of Xerox Corpora- tion Rank Xerox,Ltd., be reproduced, copied or used for any purpose whatsoever, except the manufacture of articles for Xerox Corporation J. or Rank Xerox, Ltd.

FFOOO - FFFFF FEOOO - FEFFF FDOOO - FDFFF FC800 - FCFFF FCOOO - FC7FF

3FFFF

- reserved for I/O processor 8086 initialization procedures. ROM - Ethernet Controller Local RAM

Used for Data Storage - Ethernet Controller Pseudo

addresses for Data Transfers - Ethernet Addresses for Status

and Control functions I - - 8259 Interrupt Controller

Addresses

r---

Main memory-Data Storage and Program Storage

r---

Ethernet Controller initializes

~---~ from this cell on booting

OOOOO-FBFFF

^- Main memory-Data Storage and Program Storage

Title. Xerox Corporation

PROGRAMMING SPEC

El Segundo, California

ETHERNET CONTROLLER NOTETAKER

Sheet

2

^Of

XEROX

(11)

3.0 8086 PROCESSOR INITIALIZATION

The Ethernet 8086 microprocessor must be initialized by the I/O Processor before any Ethernet transactions can occur.

3.1 The method employed to initialize the 8086 processor is to issue a Processor Boot with the MData.12 • MData.15 bits equal to Hex 1.

3.2 The Ethernet microprocessor will access location 3FFFFH in memory upon being booted. Presumably the I/O Processor will have put a pointer in that location to direct the Ethernet microprocessor to the initialization code. After the boot sequence is complete, the Ethernet microprocessor must set the Boot Sequence Done bit in the Ethernet Cont rolle rs inte rnal cont rol registe r. See specific add ress and bit assignments in the descriptions following in sections 4.0 and 4.1.

3.3 The Ethernet microprocessor can access the entire megabyte of memory addresses once the Boot Sequence Done bit has been set, however, for sending and receiving data the Ethernet logic will use the add ress block FDOOO . FDFFF as shown under 2.1

.~ These drawings and specifications,and the data

I

contained therein, are the exclusive property of Xerox Corporation and or Rank Xerox,Ltd.

I

issued in strict confidence and shall not, without the prior written permissiOn of Xerox Corpora-

; tion Rank Xerox,Ltd., be reproduced, copied or

~ used for any purpose whatsoever, except the

~ manufacture of articles for Xerox Corporation

~ or Rank Xerox, Ltd.

Title Xerox Corporation

PROGRAMMING SPEC

EI Segundo, California

ETHERNET CONTROLLER

Sheet

NOTETAKER 3

Of

XEROX

(12)

zt.-crmTEtmtjPT--co-NT~OttER

The Interrupt Controller is addressed as memory location FCOOO - FC002 and can be written into or read from in the same fashion as any memory location. See the 8259 specifications for initializing the Interrupt Con- troller. The bit assignments for reading the Interrupt Request Register are shown in the following chart:

o ⁷ ⁸ ⁹ ¹⁰ ¹¹ ¹² ¹³ ¹⁴ ¹⁵

NOT USED

1 INDICATES PARITY ERROR IN MAIN MEMORY - , ~ I J

BIT 9 = 1 INDICATES SYSTEM INTERRU PT

BIT 10 = 1 INDICATES VERTICAL SYNC INTERRUPT BIT8 =

~"

BIT 11 = 1 !ND!CATES LOSS OF CARRlER ON E-NET BIT 12 = 1 !NDICATES COLLISION DETECTED ON E-NET BIT 13 = ¹ INDICATES FIRSTWORD IS IN RECEJVE BUFFER

WHEN IN READ OVERRIDE MODE

(rfhese drawings and specifications,and the data

I

contained therein, are the exclusive property of Xerox Corporation and or Rank Xerox,Ltd.

issued in strict confidence and shall not, without the prior written permissiOn of Xerox Corpora·

I

tion Rank Xerox,Ltd., be reproduced, copied or used for any purpose whatsoever, except the manufacture of articles for Xerox Corporation or Rank Xerox, Ltd.

Title

PROGRAMMING SPEC ETHERNET CONTROLLER NOTETAKER

I

Xerox Corporation

I

XEROX

Sheet

4

^Of

I I

I

(13)

S~OE

I HERNET

MiCROPROCESSO~

The Ethernet microprocessor uses main memory addresses for passing Control and Status information between the microprocessor and the Controller logic.

The address used for reading status information or writing control information is FC800H.

5.1 CONTROL OPERATION

A "Write" to adress FC800H will load a four bit register within the controller in accordance with the following format:

i

7 8 10 11 12 13 14

I

. 15

OVER PROC BOOT ReV XMT ED NOT USED

RIDE LOCK DONE ON ON

I

BIT 11 = 1 CAUSES THE ETHERNET READ OPERAT!ON TO END AFTER THE FIRST WORD IS !NPUT

BIT 12 = 1 CAUSES THE ETHERNET CONTROLLER TO "LOCK" OUT OTHER PROCESSORS FROM ACCESSING THE SYSTEM BUS.

BIT 13 = 1 REMOVES THE FORCED "00" CONDITION FROM THE TWO MOST SIGNIFICANT BITS OF THE SEGMENT ADDRESS TO MAIN MEMORY, ALLOWING A FULL MEGABYTE ADDRESS CAPABILITY FOR THE ETHERNET MICROPROCESSOR BIT 14 = ¹ ENABLES THE RECEIVE LOGIC WITHIN THE ETHERNET

CONTROLLER.

BIT 15 = 1 ENABLES THE TRANSMIT LOGIC WITHIN THE ETHERNET CONTROLLER.

~'; These drawings and specifications,ar.d the data contained therein, are the exclusive property

Title. Xerox Corporation

EI Segundo, California of Xerox Corporation and or Rank Xerox,Ltd.

issued in strict confidence and shall not, without the prior written permissiOn of Xerox Corpora- tion Rank Xerox,Ltd., be reproduced, copied or used for any purpose whatsoever, except the manufacture of articles for Xerox Corporation , or Rank Xerox, Ltd.

PROGRAMMiNG SPEC ETHERNET CONTROLLER NOTETAKER

Sheet

5

^Of

I

I I

XEROX

(14)

5:TSTA I OS OPER~ ^{I iON}

A "Read" of address FC800H will cause the status word to be input from the cont.roller logic to the 8086. The "format is as follows:

a ⁷ ⁸

ETHERNET ADDRESS

LOC 100 NW8 CRC COL BSD MSB FROM DIPSWITCHES LSB

BIT8 = 1 INDICATES LOSS OF CARRIER ~

BIT9 = 1 INDICATES INPUT DATA NOT TAKEN FAST ENOUGH BY 8086 (INPUT DATA OVERRUN)

-~

^J

·1 I

BIT 10 = 1 INDICATES RECEIVED DATA DID I

NOT END ON WORD BOUNDARY

~ ^I

- - -

BIT 11 = 1 INDICATES A CRC ERROR ON

I

INCOMING MESSAGE

I BIT 12 = 1 !NDICATES A COLLISION WHEN I

TRANSMITTING DATA - -

r---

BIT 13 = 1 INDICATES BOOT SEQUENCE DONE

- - ^-

- ^{BIT 14} ₌ ¹ INDICATES RECEIVE IS ACTIVE - -

- - -

BIT 15 = ¹ INDICATES TRANSMIT IS ACTIVE

"---

--

NOTE THAT THESE THREE BITS REFLECT THE COMMAND WORD BITS.

Title

I

Xerox Corporation

I

These drawings and specifications,and the data contained therein, are the exclusive property of Xerox Corporation and or Rank Xerox,Ltd.

ssued in strict confidence and shall not, without he prior written permissiOn of Xerox Corpora- ion Rank Xerox,Ltd., be reproduced, copied or

PROGRAMMING SPEC

used for any purpose whatsoever, except the manufacture of articles for Xerox Corporation or Rank Xerox, Ltd.

ETHERNET CONTROLLER

NOTETAJ<ER

^Sheet

6 J

15 Rev XM •

I I

I

,

XEROX

Of

(15)

I

6.0 DATA TRANSFERS

Data is transferred under 8086 control using the MOVW - REP instructions to transfer full 16 bit words from memory to the Ethernet Controller logic and vice versa.

6.1 TRANSMIT OPERATION

To send data out over the Ethernet the 8086 must issue a control word to the Ethernet Controller logic with the XMT ON bit = 1.

This should be followed by the 8086 entering into the MOVW - REP loop with the source address equal to FEOOOH (or some other area of main memory if the local RAM has not been loaded with the data biock to be transmitted) and the destination address equai to FOOOOH.

The first data word transferred will enter a buffer register and remain there until deference has been met. If other writes occur while there is still data in the buffer, the 8086 will enter a wait state suspending operation until the buffer has been transferred to the parallel - to- serial output shift register.

"'Jhen the MOVW - REP loop completes, the Ethernet controller will automatically append the CRC word to the outgoing message

In case of a collision occu ring while the Ethernet microprocessor is in the wait state, the Write ready condition is forced, permitting the microprocessor to finish the cycle and sense the impending interrupt.

- These drawings and specifications,and the data contained therein, are the exclusive property of Xerox Corporation and or Rank Xerox,Ltd.

issued in strict confidence and shall not, without the prior written permissIOn of Xerox Corpora- tion Rank Xerox,Ltd., be reproduced, copied or

I

used for any purpose whatsoever, except the

I

manufacture of articles for Xerox Corporation or Rank Xerox, Ltd.

Title

PROGRAMMING SPEC ETHERNET CONTROLLER NOTETAKER

Xerox Corporation EI Segundo, California

Sheet

7

^Of

XEROX

I I

I

(16)

6.2 RECEIVE OPERATION

To receive data the 8086 must issue a control word to the Ethernet Controller logic with the RCV ON bit = 1. Two options are available for controlling the receive operation; Read normal or Read Override.

In the Read Normal mode, the Read Override bit in the control register is left = ^O. The 8086, after tu rning on the RCV ON bit, enters into a loop testing the state of the Test' pin with a WAIT instruction until the pin is taken low by

th~

occurence of the assembly of the first word in the input buffer. Upon exiting the WAIT instruction, the 8086 should enter the MOVW - REP sequence with the sou rce address equal to FDOOOH and the destination address FEOOOH or some other Main

The read cycle of the MOVW instruction will hang until the next word has been received from the Ethernet. Subsequent reads must occur within less than one word time (S.44 microseconds) or a Data Overrun error will be reported in the Status word.

In the Read Override mode, the Read Override bit should be set = 1 at the same time the RCV ON bit is set = 1. In this mode the 8086 is free to run other processes and under program control can enable the IRS interrupt so that when an incoming word has been assembled the 8086 is interrupted. At this time the 8086 can read the first wo rd assem bled c.:.ld check sou rce • destination add resses to decide if it wants to become actively engaged in Ethernet operations.

If so, the 8086 should reset both the RCV ON and Read Override bits followed by setting the RCV ON bit = ^1. The MOVVJ· REP sequence can then be entered in anticipation of the incoming message or the Read Normal mode can be entered as described above.

- These drawings and specifications,and the data contained therein, are the exclusive property

Title-

PROGRAMMING SPEC

Xerox Corporation EI Segundo, California of Xerox Corporation and or Rank Xerox,Ltd.

issued in strict confidence and shall not, without the prior written permissiOn of Xerox Corpora- tion Rank Xerox,Ltd., be reproduced, copied or used for any purpose whatsoever, except the manufacture of articles for Xerox Corporation or Rank Xerox, Ltd.

ETHERNET CONTROLLER

NOTETAKER

^Sheet

8

^Of

I

XEROX

(17)

7.0 OTHER CA VEA TS

The" normal" operation on Transmit will be terminated by the word count being reached (set up when the message is first started by the Ethernet BOB6) during the REP - MOVW operation.

An "Unusual End" will be manifested by the occu rence of an interrupt to the 8086 with the IR 4 bit = 1 from the Interrupt Controller.

The" normal" termination for the receive channel is for the IR 3 bit = 1 interrupt to occur, which it does upon seeing Loss of Carrier.

For safety's sake, the Receive channel should also be made to terminate on some maximum byte count so as not to overwrite areas of memory not intended for Data Storage.

Status should be read whenever an 1/0 operation terminates as the logic depends upon this for part of its reset.

CRC code is generated automatically on transmit operations and is appended to the data stream as soon as the 8086 stops the REP - MOVW operation (when the word count = 0).

CRC code is checked over incoming messages, but is not input as part of the data field. CRC errors are reported in the Status Word. See paragraph 5.3.

Software should inspect the Data block received to determine if the message is for that station and should checl< the Status Word to determine Normal or Unusual End conditions.

These drawings and specifications,and the data contained therein, are the exclusive property

Title

PROGRAMMING SPEC

Xerox Corporation EI Segundo, California of Xerox Corporation and or Rank Xerox,Ltd.

issued in strict confidence and shall not, without the prior written permissiOn of Xerox Corpora- tion Rank Xerox,Ltd., be reproduced, copied or used for any purpose whatsoever, except the manufacture of articles for Xerox Corporation or Rank Xerox, Ltd.

ETHERNET CONTROLLER

NOTETAKER

^Sheet

9 XEROX

Of

(18)

- 1 2 5 ns-

T1 T2

I

^T3

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^TW

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^TW

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ECALE

~

______________

+-____________________________ ~

ECCpuBus

ECAddr.xx

Valid by here PROM output

Valid by here ECRead

ECDEn'

Ch!pSe!ectto RAM

RAM OutEn'

RAM Data

I

^I

I r-

Stable by here

- Data on ECBus must be stable by here

ReadStatusReg' or ReadPortData'

I I

LS373's or LS374's Data

I

Stable by lela

SellntrCtlr

I

~---~---

InterruptControllerData

I

Stable by here

8086 Read Timing

Rle Designer

ENettiming01.sil RFreeman XEROX

Project

SPG NT1

Date

11/9/79

p:;---J

01 I

(19)

LILJLJ LILJLJ

ISR.15

r

ata15 Eata16 rata 1

I

^Data2

I

^Data3

I

^Data4

I

^Data5

ISR.OS

Eatas

I

^Data9 ^Eata10

ISR.OO

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^Start

I

^Data1

I

^Data2

IMIP

Counter contents

, ₁₃ _I ₁₄ ₁₅ _a ₁ ₂ ₃ ₄ ₅ ₆ ₇ ₈ ₉ ₁₀ ₁₁ ₁₂ ₁₃

ISRFun (Carry)

1"1

=L=o_a_dl_np_m_R_e_9 ________ ~1 I~

______________________________________________________________________________

1-

Pms third word in buffer here

Read 8uffe rFull

n

---~ ~---~

ReadPortData'

Read Full Reset

ENetReadReady

(LOC

1-

Data taken here by SOS6

This read hangs until data is available or

READTIMING WHEN DATA NOT AVAILABLE IN BUFFER OR WHEN LOSS OF CARRIER OCCURS DURING READ HANG TIME

File Rev Date

Garbage read here

Page

Ethemet Receive Timing ENettiming10.sil

Designer

R.Freeman A 11/1/79 10

(20)

-I I-

^{170 ns}

TClk'

~I

- - - - . . . Writes first word into buffer Writes second word into buffer

XmtOn

-W-rit-e-po-rt-D-m-a-,--~I~---~~rl---

WrtteBuffFull

ENetW riteReady

SetWriteFull

OmOn

I

- - - + - - - t ! 1--1

OmRGo

SOSLoad'

Loads first word into shift reg

---~----~.~I ----~i ~I--- I

OSLoad'

U

XC lock

OCntr contents

OS DataG

SXData

XData

XDataBitTimes

XEROX

^Project

SPG NT1

. 0 1

o

2 3 4 5

1 1 o ¹

Delay for deference

Delay between writing control word and first MOVW write operation

6 7 8

o o ¹

STARTUP TIMING SEQUENCE FOR TRANSMIT OPERATION

File Designer

Ethernet Transmit timing ENettiming02.sil RFreeman

9 10 11 12 13

ETC

Rev Date P

A 11/9/79

;;---J

02 I

(21)

-1 l-

^{170 ns}

nJ1IlJlJU

XmtOn

Writes third word into buffer

Write Po rt Data'

Write Buff Full

u

ENetW riteReady

Coli causes late drop if no OSLoad occurs SetWriteFull

OutOn

OutGo

OutRGo

SOSLoad'

u

Loads second word into shift reg

I

I i

OSLoad'

LJ

XClock

OCntr contents

I ¹³ I ¹⁴ ¹⁵ ^o ¹ ² ³ ⁴ ⁵ ⁶ ⁷ ⁸ ⁹

OS DataG

XDataBitTimes

12 I ¹³ ¹⁴ ¹⁵ ¹⁶ ¹ ² ³ ⁴ ⁵ ⁶ ⁷ ⁸

Coli

XEROX

^Project

SPG NT1

TIMING IF BUFFER IS STILL FULL WHEN WRITE OCCURS OR

IF COLLISION OCCURS WHILE HUNG IN WRITE CONDITION

Rle Designer

Ethemet Transmit timing ENettimingO 3. sil R.Freeman

10 11 12 13

9 10 11 12 13

Rev Date Page

A 11/9/79 03

(22)

XmtOn

WritePo rt Data'

Write Buff Full

ENetW riteReady

SetWriteFull

I

OutOn

OutGo

XClock

OCntr contents

I ¹³ I ¹⁴ ¹⁵ ⁰ ¹ ²

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DataG

XOataSitTimes

3 4

-1 I-

^{170 ns}

U1JlJlJ1

Writes third word into buffer

U

I

5 6 I 7 8 9 10 11 12 13

____ ~1_1_3~1 14~ 15~1 __ 1_6~_1~ ___ 2~_3 __ ~1_4 ~5 ~_6~ 7~ 8~~9 __ ~1_0~_1_1~_1_2~~13

TIMING IF BUFFER IS EMPTY WHEN WRITE OCCURS

Ethernet Transmit timing

^Rle

I

^Designer

ENettiming04.sil R. Freeman

Rev Date Page

A 11/9/79 04

(23)

CRCGo·

~ ~

¹⁷⁰^ns

o· 1

CRC

TIMING IF BUFFER IS EMPTY WHEN OSLOAD' OCCURS (\VORD COUNT HAS GONE TO ZERO)

File

Ethernet Transmit timing ENettiming05.sil

Designer

R.Freeman

Rev Date Page

A 11/9/79 05

(24)

-i ~

^{170 ns}

XmtOn

Write Po rt Data'

Write8uffFull

ENetW rite Ready

SetWriteFull

OutOn

OutGo

OutRGo

II~ ______________________________ _

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OSLoad'

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. XClock

CRCGo

OutEnd'

END TIMING SEQUENCE

I ^XEROX I

^Project

I ^SPG ^. ^NT1 Ethernet Transmit timing

File Designer Rev Date Page

ENettiming06. sit R. Freeman A 11/9/79 06

(25)

II

ReV-On Carrier

il

InOn

I~

Bit Cells

I ^Start I ¹ ² _I ³ ⁴ ⁵ ⁶ I ⁷ ⁸ I ⁹ I

RData

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Ethernet Receive Timing ENettimingO 7 .sil 11/9/79

Page

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I

^Rev

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^Date

I ^{XERO X} ^SPG ^I

^Project

^NT1

^File ^Designer

(26)

____________ J

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Counter=15

o ¹ ² 3 4 5 6 7 8 9 10 11 12 13

ISRFull (Carry)

__ Lo_a_d_ln_p'_rt_Re_g __ -= ______

~~I~ __________________________________________________________________________________

Read BufferFull

Read Po rt Data'

Read FullReset

1-

Puts first word in buffer here

This first Read must occur within one word time from IMIP going High

FIRST WORD RECEIVED TIMING

Ethernet Receive Timing

1 _

^File

ENettiming08.sil

Designer

R.Freeman

u

Date Page

"11/1/79 8

(27)

-_-,elk

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I ¹³ I ¹⁴ ¹⁵ ⁰ ¹ ² ³ ⁴ ⁵ ⁶ ⁷ ⁸ ⁹ ¹⁰ ¹¹ ¹² ¹³

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_L_o_a_dl_np_~

^__^Reg__________

~rl~ __________________________________________________________________________________

1--

Puts second word in buffer here Read BufferFull

Read Po rtData'

U

1-

Data taken here by 8086 Read FullReset

ENetReadReady

READ WHEN DATA IS AVAILABLE IN THE BUFFER REG

I ^XEROX I

^Project

SPG NT1 Ethernet Receive Timing

File Designe r

ENettimingO 9. sit R. Freeman

1~ __________

This read hangs until rata is aV<.lilable

Rev Date

A 11/1/79

Page

9

---~---.--_~ _ _ -.c

(28)

~

ISR15

Fata15 pata16 ISROS

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Counter contents

I ¹³ I ¹⁴ ¹⁵ ⁰ ¹ ² ³ ⁴ ⁵ ⁶ ⁷ ⁸ ⁹ ¹⁰ ¹¹ ¹² ¹³

ISRFull (Carry)

LoadlnputReg

1-

Puts last word in buffer here

Read BufferFull

n

---~ ~--- Read Po rt Data'

1-

Data taken here by SOS6 -R-e-ad-F-ul-I~-S-~---~U

ENetReadReady

ILOC

NORMAL ENDING SEQUENCE

I ^XEROX _SPG

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_NT1 Ethernet Receive Timing ENettiming11.sil

^Rle ^Designer

R.Freeman

^Rev

A

^Date

11 Ii 179

^Page

Boot Logic

Boot Logic

I

8284

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I I Function

Ethernet Decoder

Logic

Buffers

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Bus Addr.

and Output Data Latches

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Bus I

Timine Logic

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System I

Bus

Tol From Transceiver

XEROX

Ethernet Processor

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