BOO TOSHIBA

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TOSHIBA

http:/ /www.nuhorizons.com

2070 RINGVVOOO A~tJE

SAN.xJSE, CA 95131 (408) 43408CXJ FAX (408) 434O!135

16-Bit

M icrocontroller TLCS-900 MCU Series (1)

9 9

TMP96C141A F TMP96C041 AF TMP96CM40F TMP96PM40F TMP96031 NIF TMP96C081F

5 OAT A BOO K

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Toshiba products described in this document are not authorized for use as critical components in life support systems without the written consent of the appropriate officer of Toshiba America, Inc. Life support systems are either systems intended for surgical implant in the body or systems which sustain life. A critical component is any component of a life support system whose failure to perform may cause a malfunction or failure of the life support system, or may affect its safety or effectiveness.

The information in this document has been carefully checked and is believed to be reliable. However, no responsibility can be assumed for inaccuracies that may not have been caught.

All information in this document is subject to change without prior notice. Furthermore, Toshiba cannot assume responsibility for the use of any license under the patent rights of Toshiba or any third parties.

This technical data may be controlled under U.S. Export Administration Regulations and may be subject to the approval of the U.S. Department of Commerce prior to export. Any export or re-export, directly or indirectly, in contravention of the U.S. Export Administration Regulations is strictly prohibited.

Brand names and product names mentioned herein may be trademarks or registered trademarks of their respective

companies.

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The TLCS 900 microcontroller family of products is described in the following documents:

TLCS 900 Series CPU Ar.chitecture

The TLCS 900 user manual describes the 16-bit microcontroller TLCS 900 series system architecture. The scope of this document includes common topics to all derivitives of this family of products, such as CPU core operating modes, register organization, addressing modes, instruction set, timings and differences between the TLCS 90 and TLCS 900 series.

In addition, several databooks are available that cover the device specific topics such as package specifications and electrical characteristics. Depending on the TLCS 900 LSI device selected, the appropriate databook should be used in conjunction with the user manual. At the time of print, the following data books are available:

describes: TMP96C041~

TMP96CM40F TMP96PM40F TMP96C031 N/F TMP96C081F

TLCS 900/L MCU Series (2) describes: TMP93M40F TMP93M40AF TMP93M41F TMP93M41AF TMP96CS40F TMP96PS40F TLCS 900/H MCU Series (3) describes: TMP95C061 F

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Chapter 1 - LSI Devices TMP96C141AF

1 . Outline and Device Characteristics ... . 2. Pin Assignment and Functions ... . 2.1 Pin Assignment ... . 2.2 Pin Names and Functions ... . 3. Operation ... . 3.1 CPU ... . 3.2 Memory Map ... . 3.3 Interrupts ... .

MCU900-

MCU900- 3

MCU900- 4

MCU900- 7

MCU900- 8

MCU900- 9

3.4 Standby Function... ... ... ... .... ... ... ... .... ... ... ... ... ... MCU900- 21 3.5 Functions of Ports .. ... ... ... ... ... ... ... .... ... ... ... ... ... ... ... ... MCU900- 23 3.6 Chip SelectlWait Control ... MCU900- 47 3.7 8-bit Timers... ... MCU900- 54 3.8 8-bit PWM Timer .... ... ... .... .... ... ... ... ... ... ... ... ... ... ... ... MCU900- 70 3.9 16-bit Timers ... ... ... ... ... ... ... ... ... ... ... .... ... ... ... ... MCU900- 84 3.10 Stepping Motor Control/Pattern Generation Port ... ... ... ... ... ... .... ... ... MCU900-103 3.11 Serial Channel... ... MCU900-116 3.12 Analog/Digital Converter... ... MCU900-139 3.13 Watchdog Timer (Runaway Detecting Timer) ... MCU900-144 4. Electrical Characteristics. ... ... ... ... ... ... ... ... ... .... ... ... ... ... MCU900-150 4.1 Absolute Maximum. ... ... ... ... ... ... ... ... .... ... ... ... ... MCU900-150 4.2 DC Characteristics ... MCU900-151 4.3 AC Electrical Characteristics... ... ... ... ... .... ... ... ... ... ... MCU900-152 4.4 AID Conversion Characteristics... ... .... ... ... ... ... ... MCU900-155 4.5 Serial Channel Timing - I/O Interface Mode ... ... ... ... ... ... ... ... ... ... MCU900-155 4.6 Timer/Counter Input Clock .. ... .... .... ... ... ... ... ... ... ... ... ... .... ... MCU900-155 4.7 Interrupt Operation... ... MCU900-156 4.8 Timing Chart for I/O Interface Mode ... ... ... ... ... ... ... ... ... MCU900-157 4.9 Timing Chart for Bus Request/BUS Acknowledge ... ... ... .... ... ... ... ... ... MCU900-158 4.10 Typical Characteristics... ... MCU900-159 5. Table of Special Function Registers (SFRs)... MCU900-160 6. Port Section Equivalent Circuit Diagram... MCU900-174 7. Guidelines and Restrictions... ... MCU900-178

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TMP96C041AF

1. Outline and Device Characteristics... ... ... MCU900-179 2. Pin Assignment and Functions ... MCU900-181 2.1 Pin Assignment ... MCU900-181 2.2 Pin Names and Functions ... ... ... ... ... ... ... ... ... ... ... MCU900-182 3. Operation .. .... ... ... ... ... ... ... ... ... ... ... .... ... ... ... .... ... ... .... ... MCU900-185 3.1 CPU ... ... ... ... ... ... .... ... ... .... ... ... ... ... ... ... ... MCU900-185 3.2 Memory Map... MCU900-185 3.3 Bus Release Function... MCU900-187 3.4 Serial Function ... MCU900-188 4. Electrical Characteristics ... ... .... ... ... ... ... ... .... ... ... ... ... ... ... MCU900-189 4.1 Absolute Maximum. ... ... .... ... ... ... ... .... ... ... ... .... ... MCU900-189 4.2 DC Characteristics ... MCU900-190 4.3 AC Electrical Characteristics... MCU900-191 4.4 ND Conversion Characteristics... ... ... ... ... ... ... ... ... ... ... ... ... ... MCU900-194 4.5 Serial Channel Timing -1/0 Interface Mode... MCU900-194 4.6 Timer/Counter Input Clock (TIO, T14, T15, Tl6, T17) ... MCU900-194 4.7 Interrupt Operation ... ... ... .... ... ... ... ... ... ... ... ... ... MCU900-195 4.8 Timing Chart for 110 Interface Mode.... ... ... MCU900-196 4.9 Timing Chart for Bus Request/BUS Acknowledge ... MCU900-197 5. TMP96C141AFITMP96C041AF Differences ... MCU900-198 TMP96CM40F

1 . Outline and Device Characteristics... . MCU900-199 2. Pin Assignment and Functions ... MCU900-201 2.1 Pin Assignment ... MCU900-201 2.2 Pin Names and Functions ... ... ... ... ... ... ... MCU900-202 3. Operation. ... ... ... ... .... ... ... ... ... ... ... ... ... ... MCU900-205 3.1 CPU ... ... ... ... ... ... .... ... ... .... ... ... ... ... ... ... MCU900-205 3.2 Memory Map... MCU900-205 4. Electrical Characteristics ... MCU900-207 4.1 Absolute Maximum. ... ... ... ... ... ... ... ... .... ... ... ... ... MCU900-207 4.2 DC Characteristics ... ... ... ... ... ... ... ... ... MCU900-208 4.3 AC Electrical Characteristics... MCU900-209 4.4 ND Conversion Characteristics... MCU900-212 4.5 Serial Channel Timing -110 Interface Mode ... ... ... MCU900-212 4.6 Tlmer/Counter Input Clock (TIO, T14, T15, T16, TI7).. ... ... ... MCU900-212 4.7 Interrupt Operation ... ... ... ... ... ... ... ... MCU900-213 4.8 Timing Chart for 1/0 Interface Mode... ... ... ... ... ... ... ... MCU900-214 4.9 Timing Chart for Bus Request/BUS Acknowledge ... MCU900-215 4.10 Typical Characteristics ... ... ... ... ... ... ... ... ... ... ... MCU900-216 5. TMP96C141AFITMP96CM40FITMP96PM40F Differences ... MCU900-216 vi TOSHIBA AMERICA ELECTRONIC COMPONENTS, INC.

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TMP96PM40F

1. Outline and Device Characteristics.. ... ... ... ... ... ... ... MCU900-217 2. Pin Assignment and Functions... MCU900-219 2.1 Pin Assignment ... MCU900-219 2.2 Pin Names and Functions.. ... ... ... ... ... ... ... ... MCU900-220 3. Operation .... ... ... ... ... ... ... ... ... ... ... ... ... MCU900-223 3.1 MCU Mode . ... ... ... ... ... ... ... ... .... ... ... ... MCU900-223 3.2 PROM Mode ... ... ... ... ... ... ... ... ... ... ... MCU900-225 4. Electrical Characteristics ... ... ... ... ... ... ... ... MCU900-227 4.1 Absolute Maximum... ... ... ... ... ... ... ... ... MCU900-227 4.2 DC Characteristics ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... MCU900-228 4.3 AC Electrical Characteristics ... ... ... ... ... ... ... ... MCU900-229 4.4 AID Conversion Characteristics ... ... ... ... ... ... ... MCU900-232 4.5 Serial Channel Timing -I/O Interface Mode... MCU900-232 4.6 Timer/Counter Input Clock (TIO, T14, Tl5, T16, T17) ... ... ... ... ... ... ... .... .... ... MCU900-232 4.7 Interrupt Operation... MCU900-233 4.8 Timing Chart for I/O Interface Mode... MCU900-234 4.9 Timing Chart for Bus RequesVBUS Acknowledge ... ... ... ... MCU900-235 4.10 Read Operation (PROM Mode) ... ... ... ... ... ... .... ... ... MCU900-236 4.11 Programming Operation (PROM Mode) ... ... ... ... MCU900-236 4.12 Read Operation Timing Chart (PROM Mode) ... ... ... ... ... MCU900-237 4.13 Programming Operation Timing Chart (PROM Mode) ... ... ... ... ... ... MCU900-237 4.14 Typical Characteristics... MCU900-238 5. TMP96C 141 AFITMP96CM40FITMP96PM40F Differences... ... ... MCU900-239 TMP96C031 NITMP96C031 F

1. Outline and Device Characteristics... MCU900-241 2. Pin Assignment and Functions... ... ... ... ... MCU900-243

2.1 Pin Assignment.. ... ... ... ... MCU900-243 2.2 Pin Names and Functions... ... ... ... ... ... ... MCU900-244 3. Operation ... ... ... ... .... ... MCU900-246 3.1 CPU ... ... ... ... ... ... ... ... .... ... ... MCU900-246 3.2 Memory Map... MCU900-247 3.3 Interrupts... MCU900-249 3.4 Standby Function ... ... ... ... ... ... MCU900-261 3.5 Port Functions... MCU900-263 3.6 Chip SelectlWait Control... MCU900-282 3.7 8-bit Timers... ... MCU900-300 3.8 16-bit Timers. ... ... ... ... ... ... ... ... ... ... ... ... ... MCU900-320 3.9 Stepping Motor Control/Pattern Generation Port ... MCU900-337

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3.10 Serial Channel.. .... ... .... ... ... ... ... ... ... ... .... ... ... .... ... ... ... MCU900-350 3.11 AID Converter ... ... ... MCU900-375 3.12 Watchdog Timer... .... .... ... ... ... ... ... .... ... ... ... ... ... ... ... MCU900-379 3.13 DRAM Controller.... ... ... ... ... ... ... ... ... ... ... ... ... ... ... MCU900-385 4. Electrical Characteristics ... MCU900-396 4.1 Absolute Maximum ... ... ... MCU900-396 4.2 DC Characteristics ... ... ... ... ... ... ... ... ... ... ... ... ... MCU900-397 4.3 AC Electrical Characteristics... ... MCU900-398 4.4 DRAM Control AlC Characteristics ... ... MCU900-401 4.5 AID Conversion Characteristics... MCU900-403 4.6 Serial Channel Timing -I/O Interface Mode ... .'... MCU900-403 4.7 Timer/Counter Input Clock .. ... ... ... ... ... ... ... ... ... MCU900-403 4.8 Interrupt Operation ... ... ... .... ... ... ... ... ... ... ... MCU90D-404 4.9 Timing Chart for I/O Interface Mode... ... ... ... ... ... ... ... ... ... ... ... MCU900-405 4.10 Timing Chart for Bus Request/BUS Acknowledge... ... .... ... ... .... ... ... MCU900-406 5. Table of Special Function Registers (SFRs)... MCU900-407 6. Port Section Equivalent Circuit Diagram.. ... ... ... ... ... ... ... ... MCU900-422 7. Guidelines and Restrictions... MCU900-426 TMP96C081F

1. Outline and Device Characteristics.. ... ... ... ... ... .... .... ... ... ... ... ... MCU900-427 2. Pin Assignment and Functions... ... ... ... ... ... ... ... ... ... ... MCU900-429 2.1 Pin Assignment... ... ... ... ... ... ... ... ... ... ... ... MCU900-429 2.2 Pin Names and Functions... ... ... ... ... ... ... ... ... ... ... MCU900-430 3. Operation... ... ... ... ... ... ... ... ... ... ... ... ... MCU900-434 3.1 CPU ... MCU900-434 3.2 Memory Map ... MCU900-435 3.3 Interrupts.. ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... MCU900-436 3.4 Standby Function... ... ... ... ... ... ... ... ... ... ... MCU900-449 3.5 Functions of Ports ... MCU9OD-442 3.6 Chip SelectlWait Controller... MCU900-481 3.7 8-bit Timers... ... ... ... ... ... ... ... .... ... ... ... ... MCU90D-490 3.8 8-bit PWM Timer ... ... MCU900-519 3.9 16-bit PWM Timers ... ... ... MCU900-523 3.10 Stepping Motor Control/Pattern Generation Port... ... ... ... ... MCU900-543 3.11 Serial Channel.. ... ... ... ... ... ... ... ... ... ... ... ... .... ... MCU900-556 3.12 Analog/Digital Converter... MCU900-579 3.13 Watchdog Timer... ... ... ... ... ... ... ... ... MCU900-584 3.14 Direct Memory Access Controller ... MCU900-591 4. Electrical Characteristics... ... ... ... ... MCU900-632

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4.1 Absolute Maximum... MCU900-622 4.2 DC Characteristics ... ... ... ... ... ... ... ... ... ... MCU900-623 4.3 AC Electrical Characteristics... MCU900-624 4.4 AID Conversion Characteristics ... ... ... ... ... ... ... ... MCU900-629 4.5 Serial Channel Timing - I/O Interface Mode .. ... ... ... ... ... .... ... ... ... MCU900-629 4.6 Timer/Counter Input Clock ... MCU900-629 4.7 Interrupt Operation ... MCU900-630 4.8 Timing Chart for I/O Interface Mode ... MCU900-631 4.9 Timing Chart for Bus Request/BUS Acknowledge ... MCU900-632 4.10 DMAC ... ... ... ... ... ... ... ... ... ... ... MCU900-633 5. Table of Special Function Registers (SFRs) ... ... ... ... ... ... ... ... ... ... ... ... ... .... MCU900-635 6. Port Section Equivalent Circuit Diagram... MCU900-653 7. Guidelines and Restrictions... ... MCU900-658 Chapter 2

TLCS·900 Application Circuit ... ... ... ... ... .... ... ... ... ... ... ... ... ... ... APL900- Chapter 3

Package Dimensions ... ... ... ... ... ... ... ... ... ... ... PKG900-

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Notes

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TOSHIBA

CMOS 16-bit Microcontroller TMP96C141AF

1. Outline and Device Characteristics

The TMP96C141AF is high-speed advanced 16-bit microcontroller developed for controlling medium to large-scale equip- ment.

The TMP96C141 AF is housed in an 80-pin flat package.

Device characteristics are as follows:

(1) Original 16-bit CPU

• TLCS-90 instruction mnemonic upward compatible.

• 16M-byte linear address space

• General-purpose registers and register bank system

• 16-bit multiplication/division and bit transfer/arithmetic instructions

• High-speed micro DMA

- 4 channels (1 .6Jls/2 bytes @ 20M Hz) (2) Minimum instruction execution time

- 200ns @ 20MHz (3) Intemal RAM: 1 K byte

TMP96C141AF

Intemal ROM: None (4) Extemal memory expansion

• Can be expanded up to 16M bytes (for both programs and data).

• Can mix 8- and 16-bit extemal data buses . .. Dynamic data bus sizing

(5) 8-bit timers: 2 channels (6) 8-bit PWM timers: 2 channels (7) 16-bit timers: 2 channels

(8) Pattem generators: 4 bits, 2 channels (9) Serial interface: 2 channels

(10) 1 O-bit NO converter: 4 channels (11) Watchdog timer

(12) Chip selecVwait controller: 3 blocks (13) Interrupt functions

• 3 CPU interrupts'" '''SWI instruction, privileged violation, and Illegal instruction

• 14 intemal interrupts ] 7 -level priority can be set.

• 6 extemal interrupts (14) I/O ports

(15) Standby function : 3 halt modes (RUN, IDLE, STOP)

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MCU900-2

(ANO)P50 (AN1)P51 (AN2) P52 (AN3) P53

-fo.

-

VREF AGNo

:~

(TXoO) P90 (RXDO)P91 (CTSO) P92

.fo.

·

.f.

(TXD1) P93 (RXD1) P94 (5ClKl) P95

(PG 00) P60 (PG 01)P61 (PG 02) P62 (PG 03) P63 (PG 10)P64 (PG 11) P65 (PG 12) P66 (PG 13) P67

· _:~

.fo.

·

.~

:~

'.fo.

(TIO) P70

(T01)P7 1.f..

(T02)P72 I·

14fo.

(T03)P73

(INT 4IT14) PBO (lNT5IT15) PBl (TD4)PB2 (T05) PB3 (lNT6IT16) PB4 (lNT7IT17)PB5 (T06)P86 (INTO) P87

:~

.f.

cPu

·10-BIT4CH XWA W A

AID XBC 1,.- rC

CONVERTER XoE 101 E XHl ¹tiT

XIX IX

XIV IV

XIZ IZ

SERIAL 110 XSP SP

(CH.O) . . 32bit~

SRCITI SERIAlUO _(CH.l) I ^~

,

^I

PATTERN GENERATOR

(CH.O) PATTERN GENERATOR

(CH.l)

lKBRAM

BBITTIMER (TIMER 0) BBITTIMER

(TIMER 1)

BBITPWM (TIMER 2) BBITPWM (TIMER 3)

32KBROM (TMP96CM40)

or

16BITTIMER 32KBPROM

(TIMER 4) (TMP96PM40) 168ITTIMER

(TIMER 5)

.1-VCC[2]

VSS[3]

.1-

OSC

~t:

^Xl^X2

L

f.. ClK .1-EA

RESET ALE

.1-

-f..

INTERRUPT II.

CONTROllER

WATCH-DOG]

TIMER

I PORTO I·

B·

[~~~}

PORT3

CSNVAIT CoNTROllE

(3-BlOCK)

I-NMt

-

r.

t

^POO-P07ADO-Ao7) Pl0-P17

AoB-Aol51AB-A15)

~(

f..( P20-P27 AO-A7/A 16-A23)

~I ^P30(RO)_P31(Wii)

P32(HiNii) P33(WAif) P34(BUSRO) P3S(BU5AK) P36(R/W) P37(iiAS)

~I

f.. ~I

f..1

~:

P40(t5OiOOO) P41(ffiKASl) P42(CS2KAS2) f..1

Figure 1. TMP96C141AF Block Diagram

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2. Pin Assignment and Functions 2.1 Pin Assignment The assignment of input/output pins for TMP96C141 AF, their

name and outline functions are described below.

Figure 2.1 shows pin assignment of TMP96C141 AF.

(ANO)P50 7 3 - - - , (AN1)P51 7 4 - - - , (AN2)P52 75=====::::;l (AN3)P53 76

vee 7 7 - - - , VREF 7 S - - - - , AGND 79

VSS SO (PGOO)P60 (PG01)P61 (PG02)P62 (PG03)P63 4 (PG10)P64 5 (PGll)P65 6 (PG12)P66 7 (PG13)P67 8 (TlO)P70 9 (T01)P71 10 (T02)P72 II (T03)P73 12 (INT4fT14)PSO 13 (lNT5fT15)PSl 14 (T04)P82 15 (T05)P83 16 (lNT6fT16)PS4 17 (INT7fT17)P85 18 (T06)P86 19 (lNTO)P87 20 iliMl 21 WDTOUT 22 RESET 23 CLK 24 VSS 25 Xl 26 X 2 2 7 - - - - ' Ell 2 8 - - - ' (TXDO)P90 2 9 - - - ' (RXDO)P91 3 0 - - - '

(eTSO)P92 3 1 - - - ' (TXD1)P93 3 2 - - - . . . l

. - - - 7 2 P42(eS2/eAS2) . - - - 7 1 P41(eSlfeAS1) . - - - 7 0 P40(eSOfeASO)

69 P37(RAS) . - - - 6 8 P36(BmL

, - - - - 6 7 P35(BUSAK 66 P34 BUSR ) 65 P33(WAIT) 64 P32(flW1i) 63 P31(WR) 62 P30(RD) 61 P27(A7fA23) 60 P26(A6fA22) 59 P25(A5fA21) 58 P24(A4fA20) 57 P23(AlfA 19) 56 P22(A2fA 18) 55 P21(AlfAI7) 54 P20(AOfA 16) 53 VSS 52 P17(AD15fA15) 51 P16(ADI4fA14) 50 P15(AD13fA13) P14(ADI2fAI2) P13(ADI If A 1 I) P12(AD10fAl0) P I1(AD9fA9) Pl0(AD8fA8) P07(AD7) P06(AD6) P05(AD5) P04(AD4) P03(AD3) P02(AD2) P01(AD1) POO(ADO) vee ALE P95(SeLK1) P94(RXD1) Note: Because the TMP96Cl4lAF has an external ROM, POO to Pl7 pins are fixed to ADO

to ADI5; P30 to RD; and P31 to WR.

Figure 2.1 Pin Assignment (SO-pin QFP)

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2.2 Pin Names and Functions

The names of inpuVoutput pins and their functions are described below.

Table 2.2. Pin Names and Functions Pin Name Number

I/O Functions

01 Pins POO - P07

8 I/O Port 0: I/O port that allows I/O to be selected on a bit basis ADO - A07 Tri-state Address / data (lower): 0 - 7 for address / data bus P10 - P17 I/O Port 1: I/O port that allows I/O to be selected on a bit basis ADa -A015 8 Tri-state Address data (upper): 8 -15 for address / data bus

A8 - A15 Output Address: 8 to 15 for address bus

P20 - P27 I/O Port 2: I/O port that allows selection of I/O on a bit basis (with pull-down resistor)

AO-A7 8 Output Address: 0 - 7 for address bus

A16 - A23 Output Address: 16 - 23 for address bus

P30 1 Output Port 30: Output port

RO Output Read: Strobe signal for reading external memory

P31 1 Output Port 31: Output port

WR Output Write: Strobe signal for writing data on pins AOO-7

P32 1 I/O Port 32: I/O port (with pull-up resistor)

HWR Output High write: Strobe signal for writing data on pins A08 -15

WAIT Input Wait: Pin used to request

epu

bus wait

P34 I/O Port 34: I/O port (with pull-up resistor)

BUSRQ 1 Bus request: Signal used to request high impedance for ADO -15, AO - 23, RD, WR, HWR, RfjJ, RAS,

eso,

Input CS1, and CS2 pins. (For external DMAC)

P35 I/O Port 35: I/O (with pull-up resistor)

BUSAK 1 Bus acknowledge: Signal indicating that ADO -15, AO - 23, RD, WR, HWR, RfjJ, RAS, CSO, CS1, and CS2 Output

pins are at high impedance after receiving BUSRQ. (For external DMAC)

R/W Output Read/write: 1 represents read or dummy cycle; 0, write cycle.

RAS Output Row address strobe: Outputs RAS strobe for DRAM.

CSO 1 Output Chip select 0: Outputs 0 when address is within specified address area.

CASO Output Column address strobe 0: Outputs CAS strobe for DRAM when address is within specified address area.

Note: With the external DMA controller, this device's built-in memory or built-in I/O cannot be accessed using the BUSRQ and BUSAK pins.

MCU900-4 TOSHIBA AMERICA ELECTRONIC COMPONENTB, INC.

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Pin Name Number

1/0 Functions

01 Pins

P41 110 Port 41: 110 port (with pull-up resistor)

CS1 1 Output Chip select 1: Outputs 0 if address is within specified address area.

CAS1 Output Column address strobe 1: Outputs CAS strobe for DRAM if address is within specified address area.

CS2 1 Output Chip select 2: Outputs 0 if address is within specified address area.

CAS2 Output Column address strobe 2: Outputs CAS strobe for DRAM if address is within specified address area.

P50 - P53

4 Input Port 5: Input port

ANO - AN3 Input Analog input: Input to ND converter

VREF 1 Input Pin for reference voltage input to ND converter

AGND 1 Input Ground pin for ND converter

P50 - P53

4 I/O Ports 50 - 63: I/O ports that allow selection of I/O on a bit basis (with pull-up resistor)

PGOO- PG03 Output Pattern generator ports: 00 - 03

P54 - P57

4 I/O Ports 54 - 67: I/O ports that allow selection of I/O on a bit basis (with pull-up resistor)

PG10 - PG13 Output Pattern generator ports: 10 -13

T10 Input Timer input 0: Timer 0 input

P71 1 I/O Port 71 : I/O port (with pull-up resistor)

T01 Output Timer output 1: Timer 0 or 1 output

T02 Output PWM output 2: 8-bit PWM timer 2 output

T03 Output PWM output 3: 8-bit PWM timer 3 output

TI4 1 Input Timer input 4: Timer 4 count/capture trigger signal input

INT4 Input Interrupt request pin 4: Interrupt request pin with programmable rising/falling edge

P81 I/O Port 81 : I/O port (with pull-up resistor)

TI5 1 Input Timer input 5: Timer 4 count/capture trigger Signal input INT5 Input Interrupt request pin 5: Interrupt request pin with rising edge

T04 Output Timer output 4: Timer 4 output pin

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Pin Name Number of Pins I/O Functions

P84 I/O Port 84: 110 port (with pull-up resistor)

Tl6 1 Input Timer input 6: Timer 5 couni/capture trigger signal input

INT6 Input Interrupt request pin 6: Interrupt request pin with programmable rising/falling edge

P85 110 Port 85: I/O port (with pull-up resistor)

TI7 1 Input Timer input 7: Timer 5 couni/capture trigger signal input INT7 Input Interrupt request pin 7: Interrupt request pin with rising edge

INTO Input Interrupt request pin 0: Interrupt request pin with programmable level/rising edge

P90 1 110 Port 90: I/O port (with pull-up resistor)

TXDO Output Serial send data 0

RXDO Input Serial receive data 0

CTSO Input Serial data send enable 0 (Clear to Send)

P93 1 110 Port 93: I/O port (with pull-up resistor)

TXD1 Output Serial send data 1

RXD1 Input Serial receive data 1

SCLK1 I/O Serial clock I/O 1

WDTOUT 1 Output Watchdog timer output pin

NMI 1 Input Non-maskable interrupt request pin: Interrupt request pin with falling edge.

Can also be operated at rising edge by program.

ClK 1 Output Clock output: Outputs rX1 +

4J

clock. Pulled-up during reset.

EA 1 Input External access: 0 should be inputted with TMP96C141AF

1, with TMP96CM40F/TMP96PM40F.

ALE 1 Output Address latch enable

RESET 1 Input Reset: Initializes lSI. (With pull-up resistor)

X1/X2 2 I/O Oscillator connecting pin

VCC 2 Power supply pin (+ 5V)

VSS 3 GND pin (OV)

Note: Pull-up/pull-down resistor can be released from the pin by software.

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3. Operation

This section describes in blocks the functions and basic oper- ations of the TMP96C141AF device.

Check the chapter Guidelines and Restrictions for proper care of the device.

3.1 CPU

The TMP96C141 AF device has a built-in high-performance 16-bit CPU. (For CPU operation, see TlCS-9oo CPU in the book Core Manual Architecture User Manual.)

This section describes CPU functions unique to TMP96C141 AF that are not described in that manual.

3.1.1 Reset

To reset the TMP96C141 AF, the RESET input must be kept at

o

for at least 10 system clocks (10 states: 1 J.IS with a 20MHz system clock) within an operating voltage range and with a stable oscillation.

When reset is accepted, the CPU sets as follows:

• Program counter (PC) to 8000H.

• Stack pointer (XSP) for system mode to 1OOH.

• SYSM bit of status register (SR) to 1. (Sets to system mode.)

• IFF2 to 0 bits of status register to 111. (Sets mask register to interrupt level 7.)

• MAX bit of status register to O. (Sets to minimum mode.)

• Bits RFP2 to 0 of status register to 000. (Sets register banks to 0.)

When reset is released, instruction execution starts from address 8oo0H. CPU intemal registers other than the above are not changed.

When reset is accepted, processing for built-in I/Os, ports, and other pins is as follows:

• Initializes built-in I/O registers as per specifications.

• Sets port pins (including pins also used as built-in I/Os) to general-purpose input/output port mode (sets I/O ports to input ports).

• Sets the W"'""'D""T"'O""'U=T pin to O. (Watchdog timer is set to enable after reset.)

• Pulls up the ClK pin to 1.

• Sets the ALE pin to O.

(20)

3.2 Memory Map

Figure 3.2 is a memory map of the TMP96C141 AF.

MCU900·8

OOOOOOH

OOOOBOH 1-, - - - ' ' ' ' '

000100H 0004BOH

OOB200H

010000H

External memory (16M-byte)

Direct area (n)

t

64K-byte area (nn)

16M-byte area (R) (-R) (R+) (R + RB/16) (R +d8/16) (nnn)

FFFFFFH ' -_ _ _ _ _ _ _ --' _ _ _ _ _ _ _ _ _ - ' - _

(I '.' : <·r:\!

= Internal area)

Note: The start address after reset is 8000H. Resetting sets the stack pointer (XSP) on the system mode side to lOOH.

Figure 3.2 Memory Map

(21)

3.3 Interrupts

The TLCS-900 interrupts are controlled by the CPU interrupt mask flip-flop (IFF2 to 0) and the built-in interrupt controller.

The TMP96C141 AF have altogether the following 23 interrupt sources:

• Interrupts from the CPU"'3

A fixed individual interrupt vector number is assigned to each interrupt source; six levels of priority (variable) can also be assigned to each maskable interrupt. Non-maskable interrupts have a fixed priority of 7.

When an interrupt is generated, the interrupt controller

(Software interrupts, privileged violations, and Illegal (undefined) instruction execution)

• Interrupts from extemal pins (NMI, INTO, and INT4 to 7)"'6

• Interrupts from built-in I/Os"'14

sends the value of the priority of the interrupt source to the CPU. When more than one interrupt is generated simUlta- neously, the interrupt controller sends the value of the highest priority

rr

for non-maskable interrupts is the highest) to the CPU.

The CPU compares the value of the priority sent with the value in the CPU interrupt mask register (IFF2 to 0). If the value is greater than that of the CPU interrupt mask register, the interrupt is accepted. The value in the CPU interrupt mask register (IFF2 to 0) can be changed using the EI instruction (contents of the EI num/IFF<2:0> = num). For example,

programming EI 3 enables acceptance of maskable interrupts with a priority of 3 or greater, and non-maskable interrupts which are set in the interrupt controller. The 01 instruction

(IFF<2:0> = 7) operates in the same way as the EI 7 instruction. Since the priority values for maskable interrupts are 0 to 6, the 01 instruction is used to disable maskable interrupts to be accepted. The EI instruction becomes effective immediately after execution. (With the TLCS-90, the EI instruction becomes effective after execution of the subsequent instruction.)

In addition to the general-purpose interrupt processing mode described above, there is also a high-speed micro OMA processing mode. High-speed micro OMA is a mode used by the CPU to automatically transfer byte or word data. It enables the CPU to process interrupts such as data saves to built-in II0s at high speed.

Figure 3.3 (1) is a flowchart showing overall interrupt processing.

(22)

MCU900-10

General-purpose interrupt processing

PUSH PUSH

PC SR SR<IFF2-0><-- Accepted

interruput level + 1

RETI Instruction ( POP SR)

POP PC

NO

MicroDMA processing

Note1: In read-only mode.

always branches to NO without conditional branch.

Figure 3.3 (1) Interrupt Processing Flowchart

(23)

3.3.1 General-Purpose Interrupt Processing When accepting an interrupt, the CPU operates as follows:

(1) The CPU reads the interrupt vector from the interrupt controller. When more than one interrupt with the same level is generated simultaneously, the interrupt controller generates interrupt vectors in accordance with the default priority (which is fixed as follows: the smaller the vector value, the higher the priority), then clears the interrupt request.

(2) The CPU pushes the program counter and the status register to the system stack area (area indicated by the system mode stack pointer).

(3) The CPU sets a value in the CPU interrupt mask register

<IFF2 to 0> that is higher by 1 than the value of the accepted interrupt level. However, if the value is 7, 7 is set without an increment.

(4) The CPU sets the <SYSM> flag of the status register to 1 and enters the system mode.

(5) The CPU jumps to address 8000H + interrupt vector, then starts the interrupt processing routine.

In minimum mode, all the above processing is completed in (1.5118 @ 20M Hz). In maximum mode, it is completed in 17 states.

Bus Width of Stack Interrupt Processing State Number

Area MAX mode Min mode

8 bit 23 19

16 bit 17 15

To retum to the main routine after completion of the interrupt processing, the REll instruction is usually used. Executing this instruction restores the contents of the program counter and the status registers.

Though acceptance of non-maskable interrupts cannot be disabled by program, acceptance of maskable interrupts can. A priority can be set for each source of maskable interrupts. The CPU accepts an interrupt request with a priority higher than the value in the CPU mask register <IFF2 to 0>.

The CPU mask register <IFF2 to 0> is set to a value higher by 1 than the priority of the accepted interrupt. Thus, if an interrupt with a level higher than the interrupt being processed is generated, the CPU accepts the interrupt with the higher level, causing interrupt processing to nest. The CPU does not accept an interrupt request of the same level as that of the interrupt being processed.

Resetting initializes the CPU mask registers <IFF2 to 0>

to 7; therefore, maskable interrupts are disabled.

The addresses 008000H to 0081 FFH (512 bytes) of the TLCS-900 are assigned for interrupt processing entry area.

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Table 3.3 (1) TMP96C141AF Interrupt Table

Vector Value High·Speed Default Priority Type Interrupt Source UV" Start Address Micro DMA Start Vector

1 Reset , or SW1 0 instruction 00 0 0 H 8 0 0 0 H -

2 INTPREV: Privileged violation, or SWl1

o

0 1 0 H 8 0 1 0 H -

3 INTUNOEF: Illegal instruction, or SWI2

o

0 2 0 H 8 0 2 0 H -

4 SWI 3 Instruction 00 3 0 H 8 0 3 0 H -

5 Non- SWI4 Instruction

o

0 4 0 H 8 0 4 0 H -

6 Maskable SWI5 Instruction

o

0 5 0 H 8 0 5 0 H -

7 SWI 6 Instruction 00 60 H 8 0 60 H -

8 SWI 7 Instruction

o

0 70 H 8 0 70 H ^-

9 NMI Pin

o

0 8 0 H 8 0 8 0 H 08H

10 INTWO: Watchdog timer

o

0 9 0 H 8 0 9 0 H 09H

11 INTO pin

o

0 A 0 H 8 0 A 0 H OAH

12 INT4 pin

o

0 B 0 H 8 0 B 0 H OBH

13 INT5 pin

o

0 C 0 H 8 0 C 0 H OCH

14 INT6 pin

o

0 DOH 8 0 0 0 H OOH

15 INT? pin

o

0 E 0 H 80 E 0 H OEH

- (Reserved)

o

0 F 0 H 80 F 0 H OFH

16 INTIO: 8-bit timer 0

o

1 0 0 H 8 1 0 0 H 10H

17 INTT1: 8-bit timer 1

o

1 1 0 H 8 1 1 0 H llH

18 INTI2: 8-bit timer 2/PWMO

o

1 20 H 8 1 2 0 H 12H

19 INTI3: 8-bit timer 3/PWMl

o

1 3 0 H 8 1 3 0 H 13H

20 INTIR4 16-bit timer 4 (TREG4)

o

1 4 0 H 81 40 H 14H

21 Maskable

16-bit timer 4 (TREG5)

INTIR5:

o

1 SOH 8 1 5 0 H 15H

22 INTIR6: 16-bit timer 5 (TREG6)

o

1 6 0 H 8 1 60 H 16H

23 INTIR7: 16-bit timer 5 (TREG7)

o

1 7 0 H 8 1 7 0 H 17H

24 INTRXO Serial receive (ChanneI.O)

o

1 8 0 H 8 1 8 0 H 18H

25 INTIXO: Serial send (ChanneI.O)

o

1 9 0 H 8 1 9 0 H 19H

26 INTRX1: Serial receive (Channel.l)

o

1 A 0 H 8 1 A 0 H lAH

27 INTIX1: Serial send (Channel.l)

o

1 B 0 H 8 1 B 0 H lBH

28 INTAD: A /0 conversion completion

o

1 C 0 H 8 1 C 0 H lCH

- (Reserved) OlD 0 H 8 1 0 0 H lDH

- (Reserved) OlE 0 H 8 1 E 0 H lEH

- (Reserved)

o

1 F 0 H 8 1 F 0 H lFH

3.3.2 High-Speed Micro DMA

In addition to the conventional interrupt processing, the TLCS- 900 also has a high-speed micro DMA function. When an interrupt is accepted, in addition to an interrupt vector, the CPU receives data indicating whether processing is high-speed micro DMA mode or general-purpose interrupt. If high-speed micro DMA mode is requested, the CPU performs high-speed micro DMA processing.

The TLCS-900 can process at very high speed com- pared with the TLCS-90 micro DMA because it has transfer parameters in dedicated registers in the CPU. Since those dedicated registers are assigned as CPU control registers, they can only be accessed by the LDC (privileged) instruction.

MCU900-12 TOSHIBA AMERICA ELECTRONIC COMPONENTS, INC.

(25)

(1) High-Speed Micro DMA Operation

High-speed micro DMA operation starts when the accepted interrupt vector value matches the micro DMA start vector value set in the interrupt controller. The high-speed micro DMA has four channels so that it can be set for up to four types of interrupt source.

When a high-speed micro DMA interrupt is accepted, data is automatically transferred from the transfer source address to the transfer destination address set in the control register, and the transfer counter is decremented. If the value in the counter after decrementing is other than 0, high-speed micro DMA processing is completed. If the value in the counter after decrementing is 0, general-purpose interrupt processing is performed. In read-only mode, which is provided for DRAM refresh, the value in the counter is ignored and dummy read is repeated.

The 32-bit control registers are used for setting transfer source/destination addresses. However, the TLCS-900 has only 24 address pins for output. A 16M-byte space is available for the high-speed micro DMA. Also in normal mode operation, the all address space (in other words, the space for system

(Note 1) (Note 2)

mode which is set by the CSNVAJT controller) can be accessed by high-speed micro DMA processing.

There are two data transfer modes: one-byte mode and one-word mode. Incrementing, decrementing, and fixing the transfer source/destination address after transfer can be done in both modes. Therefore data can easily be transferred betweenllO and memory and between liDs. For details of transfer modes, see the description of transfer mode registers.

The transfer counter has 16 bits, so up to 65536 trans- fers (the maximum when the initial value of the transfer counter is OOOOH) can be performed for one interrupt source by high- speed micro DMA processing.

A the data transferred by the ~DMA function, the transfer nter was decreased.

When this counter is "O"H, the processor operates general interrupt processing. At this time if the same channel of interrupt is required next interrupt, the transfer counter starts from 65536.

Interrupt sources processed by high-speed micro DMA processing are those with the high-speed micro DMA start vectors listed in Table 3.3 (1).

(Note 3) (Note 3)

~I

^~

Xl ALE

OMl OM2 OM3 OM4 OMS OM6 OM7 OMS OM9 OM10 OMll OM12 OM13 OM14

AOO-1S

r--o.-t----~F=~=:~~~~~~~~~~~~

A16-23 _RO~===¥====~===f====~==~~~~==~~==~===Du~m~y==~==~~----~==~~~~==~~~~ _r

WR,HWR

r---t---+---+---+---~==~+---,

Xl ALE

High·Speed pOMA cycle (COUNT* 0)

AOO-1SI __

-o._t----~~~F=--~f===g§~~~~~~~~~~~

A16-23~1===+~=9~==~~~~ff==~====~==~~~~~~~~~=

_{RO I}

WR,HWR

r---~---+---_+---~----~==~~

___

Xl ALE

AOO-1SI_-n~~_{==~~==~==~~=9~~{:~~~~~~~~~

A16-23Y

~====F===~===9====~====~==~~_.~==~~_.J

RO I-____ _+---~----_

WR,HWR

High-Speed pOMA cycle (COUNT

=

⁰⁾

(Note 1) This is added 2 states the case of the bus width of source address area is Sbit

(Note2) This is added 2 states the case of the bus width of destination address area is 8bit

(Note3) This may be a dummy cycle with instruction queue buffer.

(Note4) ~~~~irs ~i1;d 2 states the case of the bus width ofstack address

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The following timing chart is a high-speed

IIDMA

cycle of the Transfer Address Increment mode (the other mode exe-

cept the Read-only mode is same as this)

(Condition: MIN mode, 16bit Bus width for 16M Byte, 0 wait)

(2) Register Configuration (CPU Control Register)

I I

Channel2 DMAS2 DMAD2

I

Channel3

~

DMAC2

~

Transfer counter register 0 Transfer mode register 0

Transfer mode register 1

Transfer source address register 2 Transfer destination address register 2 Transfer counter register 2 Transfer mode register 2

DMAS3 Transfer source address register 3

~---~

DMAD3 Transfer destination address register 3

~---.---~

I

^DMAC3 Transfercounterregister 3

~ Transfer mode register 3

1-16~-==1

1"""---32 bit

~

These Control Registers cannot be set only "LCD cr, r" instruction.

(1-65536)

MCU900-14 TOSHISA AMERICA ELECTRONIC COMPONENTS, INC.

(27)

(3) Transfer Mode Register Details

(OMAMO-3)

0 0 0 Mode

I I Note: When specifying values for this register, set the upper 4 bits to O.

r

Z· 0 byte transfer 1 word transfer execution time (Min.) @20MHz

= =

0 0 0 Z Transfer destination address INC mode . for 1/0 to memory (OMAOn + ) +- (OMASn)

OMACn+-OMACn - 1 if OMACn = 0 then INT.

0 0 1 Z Transfer destination address OEC mode for I/O to memory (OMAOn - ) .... (OMASn)

OMACn .... OMACn - 1 if OMACn = 0 then INT.

0 1 0 Z Transfer source address INC mode for I/O to memory (OMADn) +- (OMASn + )

OMACn+-OMACn - 1 if DMACn = 0 then INT.

0 1 1 Z Transfer source address OEC mode for I/O to memory (OMADn) .... (OMASn -)

OMACn .... OMACn - 1 if OMACn = 0 then INT.

1 0 0 Z Fixed address mode I/O to I/O

(OMADn) +- (OMASn) OMACn .... OMACn - 1 if OMACn = 0 then INT.

1 0 1 0 Read-only mode. for DRAM refresh

Oummy .... (OMASn) Reads 4 bytes.

OMASn+-OMASn + 4 Increments lower word only.

OMACn .... OMACn - 1

1 0 1 1 Counter mode. for interrupt counter

OMASn .... OMASn + 1 OMACn .... OMACn - 1 if DMACn = 0 then INT.

This condition is 16-bit bus width and 0 wait of source/destination address space.

Note: n: corresponds to high-speed IJDMA channels 0 - 3.

DMADn +/DMASn + : Post -increment (Increments register value after transfer.) DMADn -IDMASn - : Post-decrement (Decrement register value after transfer.)

All address space (the space for system mode) can be accessed by high-speed IlDMA. Do not use undefined codes

for transfer mode control.

~ 16 states

(1.6ps) 16 states

(1.6ps) 14 states

(1.4pS) 11 states

(Ups) (1 state = lOOns)

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~-~"-~---- - - --~-~- ~

(28)

<Usage of read only mode (DRAM refresh»

When the hardware configuration is as follows:

DRAM mapping size: 1 M8

DRAM data bus size: 8 bits

DRAM mapping address range: = 100000H to 1FFFFFH Set the following registers first; refresh is performed automatically.

(j) Register initial value setting LD

LDC LD LDC

XIX, 100000H DMASO,XIX A,000010108 DMAMO,.

® Timer Setting

"'mapping start address A"read only mode (for DRAM refresh)

Set the timers so that interrupts are generated at inteNals of 62.51JS or less.

@ Interrupt controller setting

Set the timer interrupt mask h other interrupt mask.

Write the above timer interrupt vector value in the High-Speed I1DMA start vector register, DMAOV.

(Operation description)

The DRAM data bus is an 8-bit bus and the micro DMA is in read-only mode (4 bytes), so refresh is performed four times per interrupt.

When a 512 refresh/8ms DRAM is connected, DRAM refresh is performed sufficiently if the micro DMA is started every 15.6251JS x 4 = 62.41JS or less, since the timing is 15.625J1S1refresh.

(Overhead)

Each processing time by the micro DMA is 1.81JS (18 states) @ 20M Hz with an 8-bit data bus.

In the above example, the micro DMA is started every 62.51JS, 1.8J1S162.51JS = 0.029; thus, the overhead is 2.9%.

3.3.3 Interrupt Controller

Figure 3.3.3 (1) is a block diagram of the interrupt circuits. The left half of the diagram shows the interrupt controller; the right half includes the CPU interrupt request signal circuit and the HALT release signal circuit.

Each interrupt channel (total of 20 channels) in the interrupt controller has an interrupt request flip-flop, interrupt prior-

ity setting register, and a register for storing the high-speed micro DMA start vector. The interrupt request flip-flop is used to latch interrupt requests from peripheral devices. The flip-flop is cleared to 0 at reset, when the CPU reads the interrupt channel vector after the acceptance of interrupt, or when the CPU executes an instruction that clears the interrupt of that channel (writes 0 in the clear bit of the interrupt priority setting

registe~.

For example, to dear the INTO interrupt request, set the register after the . as follows.

INTEOAD~----0 --- Zero-clears the INTO Rip-Flop.

The status of the interrupt request flip-flop is detected by reading the clear bit. Detects whether there is an interrupt request for an interrupt channel.

The interrupt priority can be set by writing the priority in the interrupt priority setting register (e.g., INTEOAD, INTE45, etc.) provided for each interrupt source. Interrupt levels to be . set are from 1 to 6. Writing 0 or 7 as the interrupt priority dis- ables the corresponding interrupt request. The priority of the . non-maskable interrupt (NMI pin, watchdog timer, etc.) is fixed to 7. If interrupt requests with the same interrupt level are generated simultaneously, interrupts are accepted in accordance with the default priority (the smaller the vector value, the higher the priority).

The interrupt controller sends the interrupt request with the highest priOrity among the simultaneous interrupts and its vector address to the CPU. The CPU compares the priority value <IFF2.to 0> set in the Status Register by the interrupt request signal with the priority value sent; if the latter is higher, the interrupt is accepted. Then the CPU sets a value higher than the priority value by 1 in the CPU SR<IFF2 to 0>. Interrupt requests where the priority value equals or is higher than the set value are accepted simultaneously during the previous interrupt routine. When interrupt processing is completed (after execution of the RET! instruction), the CPU restores the priority value saved in the stack before the interrupt was generated to the CPU SR<IFF2 to 0>.

The interrupt controller also has four registers used to store the high-speed micro other DMA start vector. These are II

o

registers; unlike other DMA registers (DMAS, DMAD, DMAM, and DMAC), they can be accessed in either normal or system mode. Writing the start vector of the interrupt sourCe for the . micro DMA processing (see Table 3.3 (1 )), enables the corresponding interrupt to be processed by micro DMA processing.

The values must be set in the micro DMA parameter registers (e.g., DMAS and DMAD) prior to the micro DMA processing ..

(29)

Interrupt controller CPU

HM'

RESET

'NTWO

-t-o.~==~===I=====y~iti:i-J

tNT.

INT4 INTS INT6 INT7

.NIT.

INTTI INTT2 INTTl INTTR4 INTTR5 INTTR6 INTTR1 INTRXO INTTXO INTRXI INTTXT INTAD

V=AOH V=BOH V=eOH V=DOH V=E H V= 100H V=110H V=l H V= 130H V= 140H V= 150H V=l60H

•

^{V= 170H}

•

^{V=l H}

•

^{V= 190H}

•

^{V= lAOH}

•

^V=lBOH

•

^V.leOH ^NM. ^INTO

Interrupt request .igna'

)-____________ r-

^~~~

______________

^~Hi~~~::~

Figure 3.3.3 (1) Block Diagram of Interrupt Controller

(30)

(1) Interrupt Priority Setting Register

L

L...o-

I I

MCU900-18

Symbol

INTEOAD

INTE4S

INTE67

INTEnO

INTEPWIO

INTET54

INTET76

INTESO

INTES'

IxxM2 0 0 0 0

, , ,

I hexC

0 I

,

_I

(Read-modify-write prohibited.)

Address 7 6 S 4 3 2 ,

I ,

0

INTAD INTO

0070H lADe ' IADM2 ' IADMI ' IADMO loe 10M2 IOMI IOMO R/W ,

W ._---_.,- R/W W

0 0 0 0 0 0 ,

0 0

INTS INT4

Ise 15M2 15M' ISMO 14e 14M2 14M. 14MO 0071H

R/W W R/W W

0 0 0 0 0 0 0 0

INH INT6

17e 17M2 17M. 17MO 16e 16M2 16M I 16MO 0072H

R/W W R/W W

0 0 0 0 0 0 0 0

INTTliTimerl INTTO TimerO

IT1C ~ ITlM2 ITiMI ITiMO ITOe ITOM2 ITOMI ITOMO 0073H

R/W W R/W W

0 0 0 0 0 0 0 0

INTT3 Timer3/PWM 1 INTT2 Timer2/PWMO

IPWle :tPWIM2 'IPWIMI :tPWIMO IPWoe ,'PWOM2dPWOM' 'IPWOMO 0074H

R/W W R/W W

0 0 0 0 0 0 0 0

INnR5 TREGS INTTR4 TREG4

ITSe , _IT5M2 _IT5MI_{: ITSMO} _IT4e , _1T4M2_{. IT4Ml} _IT4MO

0075H

R/W W R/W W

0 0 0 0 0 0 0 ,

0

INTTRWREGZL INTTR6 (TREG6)

IT7e IT7M2 IT7M, IHMO 1T6e IT6M2 ' IT6M' IT6MO 0076H

R/W W R/W W

0 0 0 0 0 0 0 0

INTTXO INTRXO

ITXoe ~ ITXOM2 ' ITXOM' ~ ITXOMO IRXOe ~ IRXOM2 ' IRXOM' ~ IRXOMO 0077H

R/W W R/W W

0 0 0 0 0 0 0 0

INTTX, INTRXI

ITXlC ~ ITX'M2 ' ITX'M' ~ ITX'MO IRXlC ~ IRX,M2 ~ IRX'M, ~ IRX'MO

0078H R/W W R/W W

0 0 0 0 0 0 0 0

~

IxxMl IxxMO Function (Write)

0 0 Prohibits interrupt request.

0

,

Sets interrupt request level to "1".

I 0 Sets interrupt request level to "2".

,

I Sets interrupt request level to "r.

0 0 Sets interrupt request level to "4·.

0

,

Sets interrupt request level to "5".

I 0 Sets interrupt request level to "6".

, ,

Prohibits interrupt request.

Function (Read)

1

Function (Write)

J

Indicates no Interrupt request I Clears interrupt request flag I

Indicates interrupt request. I • -. - - Don't care- - - .. I

HnterruJ)t source +-bit Symbol +-Read/Write if-Afterreset

(31)

(2) External Interrupt Control

IIMC

(007BH ) bit Symbol

---

ReadlWrite After reset

Function 7

---...

Interrupt Input Mode Control Register

6 5 4 3 2

---...

---... ---... ---... ^10lE

W 0 1: INTO input enable

1 0

IOLE NMIREE

W W

0 0

0: INTO 1: Can be edge operated mode inNMi 1: INTO rising

level edge.

mod.

ify-writeis Read-mod prohibited

C

INTO input enable (Note)

L

^I NMi

^T

rising edge enable

^I

I 0 I INTO disable (P87function only) I 0 Interrupt request generation at I 1 Iinputenable I 'ailing edge

1 Interrupt request generation at Nol

.

^:The INTO pin can also be used. ror standby release as described later. risinglfalling edge

Even ifthe pin is not used tor standby release, seLling this register Lo

"0" maintains the port function during standby mode.

L - - INTO level enable I 0 Rising edge detect interrupt 11 High level interrupt

Setting of External Interrupt Pin Functions

Interrupt Pin name Mode Setting method

L Falling edge IIMC(NMIREE) =0 NMI

-

~ Rising and 'ailing

edges IIMC(NMIREE) = 1

.F Rising edge IIMC(IOlE) = 0, (IOIE> = 1 INTO PS7

J'C

^level IIMC(IOlE) = 1, (IDlE) = 1

.F Rising edge T4MOC<CAPI2Ml,0> = 0,0 orO, lor 1,1 INT4 PSO

L Falling edge T4MOO(CAPI2Ml, D) = 1, 0

INT5 PSI .F Rising edge

--

.F Rising edge TSMOC<CAP34Ml,O> = O,OorO,1 or 1,1 INT6 P84

L Falling edge TSMOO(CAP34Ml, D) = 1,0

INT7 P8S .F Rising edge

--

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BOO TOSHIBA

TOSHIBA

16-Bit

M icrocontroller TLCS-900 MCU Series (1)

9 9

TMP96C141A F TMP96C041 AF TMP96CM40F TMP96PM40F TMP96031 NIF TMP96C081F

5

OAT A BOO K

---

TOSHIBA

TMP96C141AF

:~

·

· :~

·

:~

:~

:~

,

~t:

L

B·

[~~~}

-

t

~I

~:

epu

eso,

4J

o

(I '.' : <·r:\!

rr

o

o

o

o

o

o

o

o

o

o

o

o

o

o

o

o

o

o

o

o

o

o

o

o

o

o

o

~I

r--o.~~-t--~~--~~~~~F=~~~~~~~=:~~~~~~~~~~~~~~

WR,HWR

-o.~~_t--~~--~~~~~F=~~~~--~~~f===g§~~~~~~~~~~~

A16-23~1===+~=9~==~~~~ff==~==~~==~~~~~==~~~~~~~~~~~=

WR,HWR

___

~====F===~===9====~==~~==~~~==~~_.~==~~_.J

WR,HWR

=

IIDMA

I I

I

~

~

I

1-16~-==1

~

(1-65536)

r

· _:~

r--o.-t----~F=~=:~~~~~~~~~~~~

-o._t----~~~F=--~f===g§~~~~~~~~~~~

A16-23~1===+~=9~==~~~~ff==~====~==~~~~~~~~~=

~====F===~===9====~====~==~~_.~==~~_.J

)-____________ r-

^T

^I